ISSDK  1.8
IoT Sensing Software Development Kit
fxpq3115.h
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 #ifndef FXPQ3115_H_
9 #define FXPQ3115_H_
10 
11 /**
12  **
13  ** FXPQ3115 Sensor Internal Registers
14  */
15 enum {
16  FXPQ3115_STATUS = 0x00,
17  FXPQ3115_OUT_P_MSB = 0x01,
18  FXPQ3115_OUT_P_CSB = 0x02,
19  FXPQ3115_OUT_P_LSB = 0x03,
20  FXPQ3115_OUT_T_MSB = 0x04,
21  FXPQ3115_OUT_T_LSB = 0x05,
22  FXPQ3115_DR_STATUS = 0x06,
23  FXPQ3115_OUT_P_DELTA_MSB = 0x07,
24  FXPQ3115_OUT_P_DELTA_CSB = 0x08,
25  FXPQ3115_OUT_P_DELTA_LSB = 0x09,
26  FXPQ3115_OUT_T_DELTA_MSB = 0x0A,
27  FXPQ3115_OUT_T_DELTA_LSB = 0x0B,
28  FXPQ3115_WHO_AM_I = 0x0C,
29  FXPQ3115_F_STATUS = 0x0D,
30  FXPQ3115_F_DATA = 0x0E,
31  FXPQ3115_F_SETUP = 0x0F,
32  FXPQ3115_TIME_DLY = 0x10,
33  FXPQ3115_SYSMOD = 0x11,
34  FXPQ3115_INT_SOURCE = 0x12,
35  FXPQ3115_PT_DATA_CFG = 0x13,
36  FXPQ3115_BAR_IN_MSB = 0x14,
37  FXPQ3115_BAR_IN_LSB = 0x15,
38  FXPQ3115_P_TGT_MSB = 0x16,
39  FXPQ3115_P_TGT_LSB = 0x17,
40  FXPQ3115_T_TGT = 0x18,
41  FXPQ3115_P_WND_MSB = 0x19,
42  FXPQ3115_P_WND_LSB = 0x1A,
43  FXPQ3115_T_WND = 0x1B,
44  FXPQ3115_P_MIN_MSB = 0x1C,
45  FXPQ3115_P_MIN_CSB = 0x1D,
46  FXPQ3115_P_MIN_LSB = 0x1E,
47  FXPQ3115_T_MIN_MSB = 0x1F,
48  FXPQ3115_T_MIN_LSB = 0x20,
49  FXPQ3115_P_MAX_MSB = 0x21,
50  FXPQ3115_P_MAX_CSB = 0x22,
51  FXPQ3115_P_MAX_LSB = 0x23,
52  FXPQ3115_T_MAX_MSB = 0x24,
53  FXPQ3115_T_MAX_LSB = 0x25,
54  FXPQ3115_CTRL_REG1 = 0x26,
55  FXPQ3115_CTRL_REG2 = 0x27,
56  FXPQ3115_CTRL_REG3 = 0x28,
57  FXPQ3115_CTRL_REG4 = 0x29,
58  FXPQ3115_CTRL_REG5 = 0x2A,
59  FXPQ3115_OFF_P = 0x2B,
60  FXPQ3115_OFF_T = 0x2C,
61  FXPQ3115_OFF_H = 0x2D,
62 };
63 
64 #define FXPQ3115_I2C_ADDRESS (0x60) /* FXPQ3115BV I2C Slave Address. */
65 #define FXPQ3115_WHOAMI_VALUE (0xC5) /* FXPQ3115BV WHO_AM_I Value. */
66 
67 
68 /*--------------------------------
69 ** Register: STATUS
70 ** Enum: FXPQ3115_STATUS
71 ** --
72 ** Offset : 0x00 - Alias for DR_STATUS or F_STATUS.
73 ** ------------------------------*/
74 typedef uint8_t FXPQ3115_STATUS_t;
75 
76 
77 
78 /*--------------------------------
79 ** Register: OUT_P_MSB
80 ** Enum: FXPQ3115_OUT_P_MSB
81 ** --
82 ** Offset : 0x01 - Bits 12-19 of 20-bit real-time Pressure sample.
83 ** ------------------------------*/
84 typedef uint8_t FXPQ3115_OUT_P_MSB_t;
85 
86 
87 /*--------------------------------
88 ** Register: OUT_P_CSB
89 ** Enum: FXPQ3115_OUT_P_CSB
90 ** --
91 ** Offset : 0x02 - Bits 4-11 of 20-bit real-time Pressure sample.
92 ** ------------------------------*/
93 typedef uint8_t FXPQ3115_OUT_P_CSB_t;
94 
95 
96 /*--------------------------------
97 ** Register: OUT_P_LSB
98 ** Enum: FXPQ3115_OUT_P_LSB
99 ** --
100 ** Offset : 0x03 - Bits 0-3 of 20-bit real-time Pressure sample.
101 ** ------------------------------*/
102 typedef union {
103  struct {
104  uint8_t _reserved_ : 4;
105  uint8_t pd : 4; /* - 20-bit pressure sample measurement data bits 3:0 */
106 
107  } b;
108  uint8_t w;
109 } FXPQ3115_OUT_P_LSB_t;
110 
111 
112 /*
113 ** OUT_P_LSB - Bit field mask definitions
114 */
115 #define FXPQ3115_OUT_P_LSB_PD_MASK ((uint8_t) 0xF0)
116 #define FXPQ3115_OUT_P_LSB_PD_SHIFT ((uint8_t) 4)
117 
118 
119 /*------------------------------*/
120 
121 
122 
123 /*--------------------------------
124 ** Register: OUT_T_MSB
125 ** Enum: FXPQ3115_OUT_T_MSB
126 ** --
127 ** Offset : 0x04 - Bits 4-11 of 12-bit real-time Temperature sample.
128 ** ------------------------------*/
129 typedef uint8_t FXPQ3115_OUT_T_MSB_t;
130 
131 
132 /*--------------------------------
133 ** Register: OUT_T_LSB
134 ** Enum: FXPQ3115_OUT_T_LSB
135 ** --
136 ** Offset : 0x05 - Bits 0-3 of 12-bit real-time Temperature sample.
137 ** ------------------------------*/
138 typedef union {
139  struct {
140  uint8_t _reserved_ : 4;
141  uint8_t pd : 4; /* - 12-bit temperature sample measurement data bits 3:0 */
142 
143  } b;
144  uint8_t w;
145 } FXPQ3115_OUT_T_LSB_t;
146 
147 
148 /*
149 ** OUT_T_LSB - Bit field mask definitions
150 */
151 #define FXPQ3115_OUT_T_LSB_PD_MASK ((uint8_t) 0xF0)
152 #define FXPQ3115_OUT_T_LSB_PD_SHIFT ((uint8_t) 4)
153 
154 
155 /*------------------------------*/
156 
157 
158 
159 /*--------------------------------
160 ** Register: DR_STATUS
161 ** Enum: FXPQ3115_DR_STATUS
162 ** --
163 ** Offset : 0x06 - Data-ready status information
164 ** ------------------------------*/
165 typedef union {
166  struct {
167  uint8_t _reserved_ : 1;
168  uint8_t tdr : 1; /* Temperature new Data Available. */
169 
170  uint8_t pdr : 1; /* Pressure/Altitude new data available. */
171 
172  uint8_t ptdr : 1; /* Pressure/Altitude OR Temperature data ready. */
173 
174  uint8_t _reserved_1 : 1;
175  uint8_t tow : 1; /* Temperature data overwrite. */
176 
177  uint8_t pow : 1; /* Pressure/Altitude data overwrite. */
178 
179  uint8_t ptow : 1; /* Pressure/Altitude OR Temperature data overwrite. */
180 
181  } b;
182  uint8_t w;
183 } FXPQ3115_DR_STATUS_t;
184 
185 
186 /*
187 ** DR_STATUS - Bit field mask definitions
188 */
189 #define FXPQ3115_DR_STATUS_TDR_MASK ((uint8_t) 0x02)
190 #define FXPQ3115_DR_STATUS_TDR_SHIFT ((uint8_t) 1)
191 
192 #define FXPQ3115_DR_STATUS_PDR_MASK ((uint8_t) 0x04)
193 #define FXPQ3115_DR_STATUS_PDR_SHIFT ((uint8_t) 2)
194 
195 #define FXPQ3115_DR_STATUS_PTDR_MASK ((uint8_t) 0x08)
196 #define FXPQ3115_DR_STATUS_PTDR_SHIFT ((uint8_t) 3)
197 
198 #define FXPQ3115_DR_STATUS_TOW_MASK ((uint8_t) 0x20)
199 #define FXPQ3115_DR_STATUS_TOW_SHIFT ((uint8_t) 5)
200 
201 #define FXPQ3115_DR_STATUS_POW_MASK ((uint8_t) 0x40)
202 #define FXPQ3115_DR_STATUS_POW_SHIFT ((uint8_t) 6)
203 
204 #define FXPQ3115_DR_STATUS_PTOW_MASK ((uint8_t) 0x80)
205 #define FXPQ3115_DR_STATUS_PTOW_SHIFT ((uint8_t) 7)
206 
207 
208 /*
209 ** DR_STATUS - Bit field value definitions
210 */
211 #define FXPQ3115_DR_STATUS_TDR_DRDY ((uint8_t) 0x02) /* Set to 1 whenever a Temperature data acquisition */
212  /* is completed. Cleared anytime OUT_T_MSB register */
213  /* is read, when F_MODE is zero */
214 #define FXPQ3115_DR_STATUS_PDR_DRDY ((uint8_t) 0x04) /* Set to 1 whenever a new Pressure/Altitude data */
215  /* acquisition is completed. Cleared anytime */
216  /* OUT_P_MSB register is read, when F_MODE is zero */
217 #define FXPQ3115_DR_STATUS_PTDR_DRDY ((uint8_t) 0x08) /* Signals that a new acquisition for either */
218  /* Pressure/Altitude or Temperature is available. */
219  /* Cleared anytime OUT_P_MSB or OUT_T_MSB register is */
220  /* read, when F_MODE is zero */
221 #define FXPQ3115_DR_STATUS_TOW_OWR ((uint8_t) 0x20) /* Set to 1 whenever a new Temperature acquisition is */
222  /* completed before the retrieval of the previous */
223  /* data. When this occurs the previous data is */
224  /* overwritten. Cleared anytime OUT_T_MSB register is */
225  /* read, when F_MODE is zero */
226 #define FXPQ3115_DR_STATUS_POW_OWR ((uint8_t) 0x40) /* Set to 1 whenever a new Pressure/Altitude */
227  /* acquisition is completed before the retrieval of */
228  /* the previous data. When this occurs the previous */
229  /* data is overwritten. POW is cleared anytime */
230  /* OUT_P_MSB register is read, when F_MODE is zero */
231 #define FXPQ3115_DR_STATUS_PTOW_OWR ((uint8_t) 0x80) /* Set to 1 whenever new data is acquired before */
232  /* completing the retrieval of the previous set. This */
233  /* event occurs when the content of at least one data */
234  /* register (i.e. OUT_P, OUT_T) has been overwritten. */
235  /* PTOW is cleared when the high-bytes of the data */
236  /* (OUT_P_MSB or OUT_T_MSB) are read, when F_MODE is */
237  /* zero */
238 /*------------------------------*/
239 
240 
241 
242 /*--------------------------------
243 ** Register: OUT_P_DELTA_MSB
244 ** Enum: FXPQ3115_OUT_P_DELTA_MSB
245 ** --
246 ** Offset : 0x07 - Bits 12-19 of 20-bit Pressure change data.
247 ** ------------------------------*/
248 typedef uint8_t FXPQ3115_OUT_P_DELTA_MSB_t;
249 
250 
251 /*--------------------------------
252 ** Register: OUT_P_DELTA_CSB
253 ** Enum: FXPQ3115_OUT_P_DELTA_CSB
254 ** --
255 ** Offset : 0x08 - Bits 4-11 of 20-bit Pressure change data.
256 ** ------------------------------*/
257 typedef uint8_t FXPQ3115_OUT_P_DELTA_CSB_t;
258 
259 
260 /*--------------------------------
261 ** Register: OUT_P_DELTA_LSB
262 ** Enum: FXPQ3115_OUT_P_DELTA_LSB
263 ** --
264 ** Offset : 0x09 - Bits 0-3 of 20-bit Pressure change data.
265 ** ------------------------------*/
266 typedef union {
267  struct {
268  uint8_t _reserved_ : 4;
269  uint8_t pcd : 4; /* - 20-bit pressure change measurement data bits 3:0 */
270 
271  } b;
272  uint8_t w;
273 } FXPQ3115_OUT_P_DELTA_LSB_t;
274 
275 
276 /*
277 ** OUT_P_DELTA_LSB - Bit field mask definitions
278 */
279 #define FXPQ3115_OUT_P_DELTA_LSB_PCD_MASK ((uint8_t) 0xF0)
280 #define FXPQ3115_OUT_P_DELTA_LSB_PCD_SHIFT ((uint8_t) 4)
281 
282 
283 /*------------------------------*/
284 
285 
286 
287 /*--------------------------------
288 ** Register: OUT_T_DELTA_MSB
289 ** Enum: FXPQ3115_OUT_T_DELTA_MSB
290 ** --
291 ** Offset : 0x0A - Bits 4-11 of 12-bit Temperature change data.
292 ** ------------------------------*/
293 typedef uint8_t FXPQ3115_OUT_T_DELTA_MSB_t;
294 
295 
296 /*--------------------------------
297 ** Register: OUT_T_DELTA_LSB
298 ** Enum: FXPQ3115_OUT_T_DELTA_LSB
299 ** --
300 ** Offset : 0x0B - Bits 0-3 of 12-bit Temperature change data.
301 ** ------------------------------*/
302 typedef union {
303  struct {
304  uint8_t _reserved_ : 4;
305  uint8_t tcd : 4; /* - 12-bit temperature change measurement data bits 3:0 */
306 
307  } b;
308  uint8_t w;
309 } FXPQ3115_OUT_T_DELTA_LSB_t;
310 
311 
312 /*
313 ** OUT_T_DELTA_LSB - Bit field mask definitions
314 */
315 #define FXPQ3115_OUT_T_DELTA_LSB_TCD_MASK ((uint8_t) 0xF0)
316 #define FXPQ3115_OUT_T_DELTA_LSB_TCD_SHIFT ((uint8_t) 4)
317 
318 
319 /*------------------------------*/
320 
321 
322 
323 /*--------------------------------
324 ** Register: WHO_AM_I
325 ** Enum: FXPQ3115_WHO_AM_I
326 ** --
327 ** Offset : 0x0C - Fixed Device ID Number.
328 ** ------------------------------*/
329 typedef uint8_t FXPQ3115_WHO_AM_I_t;
330 
331 
332 
333 /*--------------------------------
334 ** Register: F_STATUS
335 ** Enum: FXPQ3115_F_STATUS
336 ** --
337 ** Offset : 0x0D - FIFO Status: No FIFO event detected.
338 ** ------------------------------*/
339 typedef union {
340  struct {
341  uint8_t f_cnt : 6; /* FIFO sample counter. F_CNT[5:0] bits indicate the number of samples */
342  /* currently stored in the FIFO buffer */
343 
344  uint8_t f_wmkf_flag : 1; /* FIFO Watermark event */
345 
346  uint8_t f_ovf : 1; /* FIFO overflow event. */
347 
348  } b;
349  uint8_t w;
350 } FXPQ3115_F_STATUS_t;
351 
352 
353 /*
354 ** F_STATUS - Bit field mask definitions
355 */
356 #define FXPQ3115_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F)
357 #define FXPQ3115_F_STATUS_F_CNT_SHIFT ((uint8_t) 0)
358 
359 #define FXPQ3115_F_STATUS_F_WMKF_FLAG_MASK ((uint8_t) 0x40)
360 #define FXPQ3115_F_STATUS_F_WMKF_FLAG_SHIFT ((uint8_t) 6)
361 
362 #define FXPQ3115_F_STATUS_F_OVF_MASK ((uint8_t) 0x80)
363 #define FXPQ3115_F_STATUS_F_OVF_SHIFT ((uint8_t) 7)
364 
365 
366 /*
367 ** F_STATUS - Bit field value definitions
368 */
369 #define FXPQ3115_F_STATUS_F_WMKF_FLAG_NOEVT ((uint8_t) 0x00) /* No FIFO watermark event detected. */
370 #define FXPQ3115_F_STATUS_F_WMKF_FLAG_EVTDET ((uint8_t) 0x40) /* FIFO Watermark event has been detected. */
371 #define FXPQ3115_F_STATUS_F_OVF_NOOVFL ((uint8_t) 0x00) /* No FIFO overflow events detected. */
372 #define FXPQ3115_F_STATUS_F_OVF_OVFLDET ((uint8_t) 0x80) /* FIFO Overflow event has been detected. */
373 /*------------------------------*/
374 
375 
376 
377 /*--------------------------------
378 ** Register: F_DATA
379 ** Enum: FXPQ3115_F_DATA
380 ** --
381 ** Offset : 0x0E - FIFO 8-bit data access.
382 ** ------------------------------*/
383 typedef uint8_t FXPQ3115_F_DATA_t;
384 
385 
386 
387 /*--------------------------------
388 ** Register: F_SETUP
389 ** Enum: FXPQ3115_F_SETUP
390 ** --
391 ** Offset : 0x0F - FIFO setup.
392 ** ------------------------------*/
393 typedef union {
394  struct {
395  uint8_t f_wmrk : 6; /* FIFO Event Sample Count Watermark. */
396 
397  uint8_t f_mode : 2; /* FIFO buffer overflow mode. */
398 
399  } b;
400  uint8_t w;
401 } FXPQ3115_F_SETUP_t;
402 
403 
404 /*
405 ** F_SETUP - Bit field mask definitions
406 */
407 #define FXPQ3115_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F)
408 #define FXPQ3115_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0)
409 
410 #define FXPQ3115_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0)
411 #define FXPQ3115_F_SETUP_F_MODE_SHIFT ((uint8_t) 6)
412 
413 
414 /*
415 ** F_SETUP - Bit field value definitions
416 */
417 #define FXPQ3115_F_SETUP_F_MODE_FIFO_OFF ((uint8_t) 0x00) /* FIFO is disabled. */
418 #define FXPQ3115_F_SETUP_F_MODE_CIR_MODE ((uint8_t) 0x40) /* FIFO contains the most recent samples when */
419  /* overflowed (circular buffer). */
420 #define FXPQ3115_F_SETUP_F_MODE_STOP_MODE ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed. */
421 /*------------------------------*/
422 
423 
424 
425 /*--------------------------------
426 ** Register: TIME_DLY
427 ** Enum: FXPQ3115_TIME_DLY
428 ** --
429 ** Offset : 0x10 - Time since FIFO overflow.
430 ** ------------------------------*/
431 typedef uint8_t FXPQ3115_TIME_DLY_t;
432 
433 
434 
435 /*--------------------------------
436 ** Register: SYSMOD
437 ** Enum: FXPQ3115_SYSMOD
438 ** --
439 ** Offset : 0x11 - Current system mode.
440 ** ------------------------------*/
441 typedef union {
442  struct {
443  uint8_t sysmod : 1; /* - System mode data bit 0. (Bits 7-1 are reserved, will always read 0.) */
444 
445  } b;
446  uint8_t w;
447 } FXPQ3115_SYSMOD_t;
448 
449 
450 /*
451 ** SYSMOD - Bit field mask definitions
452 */
453 #define FXPQ3115_SYSMOD_SYSMOD_MASK ((uint8_t) 0x01)
454 #define FXPQ3115_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0)
455 
456 
457 /*
458 ** SYSMOD - Bit field value definitions
459 */
460 #define FXPQ3115_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* STANDBY Mode. */
461 #define FXPQ3115_SYSMOD_SYSMOD_ACTIVE ((uint8_t) 0x01) /* ACTIVE Mode. */
462 /*------------------------------*/
463 
464 
465 
466 /*--------------------------------
467 ** Register: INT_SOURCE
468 ** Enum: FXPQ3115_INT_SOURCE
469 ** --
470 ** Offset : 0x12 - Interrupt status. The bits that are set (logic ‘1’) indicate which function has asserted its interrupt and conversely, bits that are cleared (logic ‘0’) indicate which function has not asserted its interrupt.
471 ** ------------------------------*/
472 typedef union {
473  struct {
474  uint8_t src_tchg : 1; /* Delta T interrupt status bit. */
475 
476  uint8_t src_pchg : 1; /* Delta P interrupt status bit. */
477 
478  uint8_t src_tth : 1; /* Temperature threshold interrupt. */
479 
480  uint8_t src_pth : 1; /* Altitude/Pressure threshold interrupt. */
481 
482  uint8_t src_tw : 1; /* Temperature alerter status bit near or equal to target temperature. */
483 
484  uint8_t src_pw : 1; /* Altitude/Pressure alerter status bit near or equal to target */
485  /* Pressure/Altitude. */
486 
487  uint8_t src_fifo : 1; /* FIFO interrupt status bit. */
488 
489  uint8_t src_drdy : 1; /* Data ready interrupt status bit. */
490 
491  } b;
492  uint8_t w;
493 } FXPQ3115_INT_SOURCE_t;
494 
495 
496 /*
497 ** INT_SOURCE - Bit field mask definitions
498 */
499 #define FXPQ3115_INT_SOURCE_SRC_TCHG_MASK ((uint8_t) 0x01)
500 #define FXPQ3115_INT_SOURCE_SRC_TCHG_SHIFT ((uint8_t) 0)
501 
502 #define FXPQ3115_INT_SOURCE_SRC_PCHG_MASK ((uint8_t) 0x02)
503 #define FXPQ3115_INT_SOURCE_SRC_PCHG_SHIFT ((uint8_t) 1)
504 
505 #define FXPQ3115_INT_SOURCE_SRC_TTH_MASK ((uint8_t) 0x04)
506 #define FXPQ3115_INT_SOURCE_SRC_TTH_SHIFT ((uint8_t) 2)
507 
508 #define FXPQ3115_INT_SOURCE_SRC_PTH_MASK ((uint8_t) 0x08)
509 #define FXPQ3115_INT_SOURCE_SRC_PTH_SHIFT ((uint8_t) 3)
510 
511 #define FXPQ3115_INT_SOURCE_SRC_TW_MASK ((uint8_t) 0x10)
512 #define FXPQ3115_INT_SOURCE_SRC_TW_SHIFT ((uint8_t) 4)
513 
514 #define FXPQ3115_INT_SOURCE_SRC_PW_MASK ((uint8_t) 0x20)
515 #define FXPQ3115_INT_SOURCE_SRC_PW_SHIFT ((uint8_t) 5)
516 
517 #define FXPQ3115_INT_SOURCE_SRC_FIFO_MASK ((uint8_t) 0x40)
518 #define FXPQ3115_INT_SOURCE_SRC_FIFO_SHIFT ((uint8_t) 6)
519 
520 #define FXPQ3115_INT_SOURCE_SRC_DRDY_MASK ((uint8_t) 0x80)
521 #define FXPQ3115_INT_SOURCE_SRC_DRDY_SHIFT ((uint8_t) 7)
522 
523 
524 /*------------------------------*/
525 
526 
527 
528 /*--------------------------------
529 ** Register: PT_DATA_CFG
530 ** Enum: FXPQ3115_PT_DATA_CFG
531 ** --
532 ** Offset : 0x13 - Data event flag configuration.
533 ** ------------------------------*/
534 typedef union {
535  struct {
536  uint8_t tdefe : 1; /* Data event flag enable on new Temperature data. */
537 
538  uint8_t pdefe : 1; /* Data event flag enable on new Pressure/Altitude data. */
539 
540  uint8_t drem : 1; /* Data ready event mode. */
541 
542  } b;
543  uint8_t w;
544 } FXPQ3115_PT_DATA_CFG_t;
545 
546 
547 /*
548 ** PT_DATA_CFG - Bit field mask definitions
549 */
550 #define FXPQ3115_PT_DATA_CFG_TDEFE_MASK ((uint8_t) 0x01)
551 #define FXPQ3115_PT_DATA_CFG_TDEFE_SHIFT ((uint8_t) 0)
552 
553 #define FXPQ3115_PT_DATA_CFG_PDEFE_MASK ((uint8_t) 0x02)
554 #define FXPQ3115_PT_DATA_CFG_PDEFE_SHIFT ((uint8_t) 1)
555 
556 #define FXPQ3115_PT_DATA_CFG_DREM_MASK ((uint8_t) 0x04)
557 #define FXPQ3115_PT_DATA_CFG_DREM_SHIFT ((uint8_t) 2)
558 
559 
560 /*
561 ** PT_DATA_CFG - Bit field value definitions
562 */
563 #define FXPQ3115_PT_DATA_CFG_TDEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
564 #define FXPQ3115_PT_DATA_CFG_TDEFE_ENABLED ((uint8_t) 0x01) /* Event detection enabled. Raise event flag on new */
565  /* Temperature data. */
566 #define FXPQ3115_PT_DATA_CFG_PDEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
567 #define FXPQ3115_PT_DATA_CFG_PDEFE_ENABLED ((uint8_t) 0x02) /* Event detection enabled. Raise event flag on new */
568  /* Pressure/Altitude data. */
569 #define FXPQ3115_PT_DATA_CFG_DREM_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
570 #define FXPQ3115_PT_DATA_CFG_DREM_ENABLED ((uint8_t) 0x04) /* Event detection enabled. Generate data ready */
571  /* event flag on new Pressure/Altitude or */
572  /* Temperature data. */
573 /*------------------------------*/
574 
575 
576 
577 /*--------------------------------
578 ** Register: BAR_IN_MSB
579 ** Enum: FXPQ3115_BAR_IN_MSB
580 ** --
581 ** Offset : 0x14 - Bits 8-15 of Barometric input for Altitude calculation.
582 ** ------------------------------*/
583 typedef uint8_t FXPQ3115_BAR_IN_MSB_t;
584 
585 
586 /*--------------------------------
587 ** Register: BAR_IN_LSB
588 ** Enum: FXPQ3115_BAR_IN_LSB
589 ** --
590 ** Offset : 0x15 - Bits 0-7 of Barometric input for Altitude calculation.
591 ** ------------------------------*/
592 typedef uint8_t FXPQ3115_BAR_IN_LSB_t;
593 
594 
595 
596 /*--------------------------------
597 ** Register: P_TGT_MSB
598 ** Enum: FXPQ3115_P_TGT_MSB
599 ** --
600 ** Offset : 0x16 - Bits 8-15 of Pressure/Altitude target value.
601 ** ------------------------------*/
602 typedef uint8_t FXPQ3115_P_TGT_MSB_t;
603 
604 
605 /*--------------------------------
606 ** Register: P_TGT_LSB
607 ** Enum: FXPQ3115_P_TGT_LSB
608 ** --
609 ** Offset : 0x17 - Bits 0-7 of Pressure/Altitude target value.
610 ** ------------------------------*/
611 typedef uint8_t FXPQ3115_P_TGT_LSB_t;
612 
613 
614 
615 /*--------------------------------
616 ** Register: T_TGT
617 ** Enum: FXPQ3115_T_TGT
618 ** --
619 ** Offset : 0x18 - Temperature target value.
620 ** ------------------------------*/
621 typedef uint8_t FXPQ3115_T_TGT_t;
622 
623 
624 
625 /*--------------------------------
626 ** Register: P_WND_MSB
627 ** Enum: FXPQ3115_P_WND_MSB
628 ** --
629 ** Offset : 0x19 - Bits 8-15 of Pressure/Altitude window value.
630 ** ------------------------------*/
631 typedef uint8_t FXPQ3115_P_WND_MSB_t;
632 
633 
634 /*--------------------------------
635 ** Register: P_WND_LSB
636 ** Enum: FXPQ3115_P_WND_LSB
637 ** --
638 ** Offset : 0x1A - Bits 0-7 of Pressure/Altitude window value.
639 ** ------------------------------*/
640 typedef uint8_t FXPQ3115_P_WND_LSB_t;
641 
642 
643 
644 /*--------------------------------
645 ** Register: T_WND
646 ** Enum: FXPQ3115_T_WND
647 ** --
648 ** Offset : 0x1B - Temperature window value.
649 ** ------------------------------*/
650 typedef uint8_t FXPQ3115_T_WND_t;
651 
652 
653 
654 /*--------------------------------
655 ** Register: P_MIN_MSB
656 ** Enum: FXPQ3115_P_MIN_MSB
657 ** --
658 ** Offset : 0x1C - Bits 12-19 of 20-bit Minimum Pressure/Altitude data.
659 ** ------------------------------*/
660 typedef uint8_t FXPQ3115_P_MIN_MSB_t;
661 
662 
663 /*--------------------------------
664 ** Register: P_MIN_CSB
665 ** Enum: FXPQ3115_P_MIN_CSB
666 ** --
667 ** Offset : 0x1D - Bits 4-11 of 20-bit Minimum Pressure/Altitude data.
668 ** ------------------------------*/
669 typedef uint8_t FXPQ3115_P_MIN_CSB_t;
670 
671 
672 /*--------------------------------
673 ** Register: P_MIN_LSB
674 ** Enum: FXPQ3115_P_MIN_LSB
675 ** --
676 ** Offset : 0x1E - Bits 0-3 of 20-bit Minimum Pressure/Altitude data.
677 ** ------------------------------*/
678 typedef union {
679  struct {
680  uint8_t _reserved_ : 4;
681  uint8_t minpad : 4; /* - 20-bit Minimum Pressure/Altitude data bits 3:0. */
682 
683  } b;
684  uint8_t w;
685 } FXPQ3115_P_MIN_LSB_t;
686 
687 
688 /*
689 ** P_MIN_LSB - Bit field mask definitions
690 */
691 #define FXPQ3115_P_MIN_LSB_MINPAD_MASK ((uint8_t) 0xF0)
692 #define FXPQ3115_P_MIN_LSB_MINPAD_SHIFT ((uint8_t) 4)
693 
694 
695 /*------------------------------*/
696 
697 
698 
699 /*--------------------------------
700 ** Register: T_MIN_MSB
701 ** Enum: FXPQ3115_T_MIN_MSB
702 ** --
703 ** Offset : 0x1F - Bits 4-11 of 12-bit Minimum Temperature data.
704 ** ------------------------------*/
705 typedef uint8_t FXPQ3115_T_MIN_MSB_t;
706 
707 
708 /*--------------------------------
709 ** Register: T_MIN_LSB
710 ** Enum: FXPQ3115_T_MIN_LSB
711 ** --
712 ** Offset : 0x20 - Bits 0-3 of 12-bit Minimum Temperature data.
713 ** ------------------------------*/
714 typedef union {
715  struct {
716  uint8_t _reserved_ : 4;
717  uint8_t mintd : 4; /* - 12-bit Minimum Temperature data bits 3:0. */
718 
719  } b;
720  uint8_t w;
721 } FXPQ3115_T_MIN_LSB_t;
722 
723 
724 /*
725 ** T_MIN_LSB - Bit field mask definitions
726 */
727 #define FXPQ3115_T_MIN_LSB_MINTD_MASK ((uint8_t) 0xF0)
728 #define FXPQ3115_T_MIN_LSB_MINTD_SHIFT ((uint8_t) 4)
729 
730 
731 /*------------------------------*/
732 
733 
734 
735 /*--------------------------------
736 ** Register: P_MAX_MSB
737 ** Enum: FXPQ3115_P_MAX_MSB
738 ** --
739 ** Offset : 0x21 - Bits 12-19 of 20-bit Maximum Pressure/Altitude data.
740 ** ------------------------------*/
741 typedef uint8_t FXPQ3115_P_MAX_MSB_t;
742 
743 
744 /*--------------------------------
745 ** Register: P_MAX_CSB
746 ** Enum: FXPQ3115_P_MAX_CSB
747 ** --
748 ** Offset : 0x22 - Bits 4-11 of 20-bit Maximum Pressure/Altitude data.
749 ** ------------------------------*/
750 typedef uint8_t FXPQ3115_P_MAX_CSB_t;
751 
752 
753 /*--------------------------------
754 ** Register: P_MAX_LSB
755 ** Enum: FXPQ3115_P_MAX_LSB
756 ** --
757 ** Offset : 0x23 - Bits 0-3 of 20-bit Maximum Pressure/Altitude data.
758 ** ------------------------------*/
759 typedef union {
760  struct {
761  uint8_t _reserved_ : 4;
762  uint8_t maxpad : 4; /* - 20-bit Maximum Pressure/Altitude data bits 3:0. */
763 
764  } b;
765  uint8_t w;
766 } FXPQ3115_P_MAX_LSB_t;
767 
768 
769 /*
770 ** P_MAX_LSB - Bit field mask definitions
771 */
772 #define FXPQ3115_P_MAX_LSB_MAXPAD_MASK ((uint8_t) 0xF0)
773 #define FXPQ3115_P_MAX_LSB_MAXPAD_SHIFT ((uint8_t) 4)
774 
775 
776 /*------------------------------*/
777 
778 
779 
780 /*--------------------------------
781 ** Register: T_MAX_MSB
782 ** Enum: FXPQ3115_T_MAX_MSB
783 ** --
784 ** Offset : 0x24 - Bits 4-11 of 12-bit Maximum Temperature data.
785 ** ------------------------------*/
786 typedef uint8_t FXPQ3115_T_MAX_MSB_t;
787 
788 
789 /*--------------------------------
790 ** Register: T_MAX_LSB
791 ** Enum: FXPQ3115_T_MAX_LSB
792 ** --
793 ** Offset : 0x25 - Bits 0-3 of 12-bit Maximum Temperature data.
794 ** ------------------------------*/
795 typedef union {
796  struct {
797  uint8_t _reserved_ : 4;
798  uint8_t maxtd : 4; /* - 12-bit Maximum Temperature data bits 3:0. */
799 
800  } b;
801  uint8_t w;
802 } FXPQ3115_T_MAX_LSB_t;
803 
804 
805 /*
806 ** T_MAX_LSB - Bit field mask definitions
807 */
808 #define FXPQ3115_T_MAX_LSB_MAXTD_MASK ((uint8_t) 0xF0)
809 #define FXPQ3115_T_MAX_LSB_MAXTD_SHIFT ((uint8_t) 4)
810 
811 
812 /*------------------------------*/
813 
814 
815 
816 /*--------------------------------
817 ** Register: CTRL_REG1
818 ** Enum: FXPQ3115_CTRL_REG1
819 ** --
820 ** Offset : 0x26 - Control Register 1: Modes, Oversampling.
821 ** ------------------------------*/
822 typedef union {
823  struct {
824  uint8_t sbyb : 1; /* Operation Mode. */
825 
826  uint8_t ost : 1; /* OST bit to initiate a measurement immediately, If the SBYB bit is set to */
827  /* active. */
828 
829  uint8_t rst : 1; /* Software Reset. This bit is used to activate the software reset. */
830 
831  uint8_t os : 3; /* Oversample Ratio. These bits select the oversampling ratio. */
832 
833  uint8_t raw : 1; /* RAW output mode. RAW bit will output ADC data with no post processing, */
834  /* except for oversampling. */
835 
836  uint8_t alt : 1; /* Altimeter-Barometer mode. */
837 
838  } b;
839  uint8_t w;
840 } FXPQ3115_CTRL_REG1_t;
841 
842 
843 /*
844 ** CTRL_REG1 - Bit field mask definitions
845 */
846 #define FXPQ3115_CTRL_REG1_SBYB_MASK ((uint8_t) 0x01)
847 #define FXPQ3115_CTRL_REG1_SBYB_SHIFT ((uint8_t) 0)
848 
849 #define FXPQ3115_CTRL_REG1_OST_MASK ((uint8_t) 0x02)
850 #define FXPQ3115_CTRL_REG1_OST_SHIFT ((uint8_t) 1)
851 
852 #define FXPQ3115_CTRL_REG1_RST_MASK ((uint8_t) 0x04)
853 #define FXPQ3115_CTRL_REG1_RST_SHIFT ((uint8_t) 2)
854 
855 #define FXPQ3115_CTRL_REG1_OS_MASK ((uint8_t) 0x38)
856 #define FXPQ3115_CTRL_REG1_OS_SHIFT ((uint8_t) 3)
857 
858 #define FXPQ3115_CTRL_REG1_RAW_MASK ((uint8_t) 0x40)
859 #define FXPQ3115_CTRL_REG1_RAW_SHIFT ((uint8_t) 6)
860 
861 #define FXPQ3115_CTRL_REG1_ALT_MASK ((uint8_t) 0x80)
862 #define FXPQ3115_CTRL_REG1_ALT_SHIFT ((uint8_t) 7)
863 
864 
865 /*
866 ** CTRL_REG1 - Bit field value definitions
867 */
868 #define FXPQ3115_CTRL_REG1_SBYB_STANDBY ((uint8_t) 0x00) /* Standby Mode. */
869 #define FXPQ3115_CTRL_REG1_SBYB_ACTIVE ((uint8_t) 0x01) /* Active Mode. */
870 #define FXPQ3115_CTRL_REG1_OST_RESET ((uint8_t) 0x00) /* Reset OST Bit. */
871 #define FXPQ3115_CTRL_REG1_OST_SET ((uint8_t) 0x02) /* SET OST Bit. */
872 #define FXPQ3115_CTRL_REG1_RST_DIS ((uint8_t) 0x00) /* Device reset disabled. */
873 #define FXPQ3115_CTRL_REG1_RST_EN ((uint8_t) 0x04) /* Device reset enabled. */
874 #define FXPQ3115_CTRL_REG1_OS_OSR_1 ((uint8_t) 0x00) /* OSR = 1 and Minimum Time Between Data Samples 6 ms */
875 #define FXPQ3115_CTRL_REG1_OS_OSR_2 ((uint8_t) 0x08) /* OSR = 2 and Minimum Time Between Data Samples 10 */
876  /* ms */
877 #define FXPQ3115_CTRL_REG1_OS_OSR_4 ((uint8_t) 0x10) /* OSR = 4 and Minimum Time Between Data Samples 18 */
878  /* ms */
879 #define FXPQ3115_CTRL_REG1_OS_OSR_8 ((uint8_t) 0x18) /* OSR = 8 and Minimum Time Between Data Samples 34 */
880  /* ms */
881 #define FXPQ3115_CTRL_REG1_OS_OSR_16 ((uint8_t) 0x20) /* OSR = 16 and Minimum Time Between Data Samples 66 */
882  /* ms */
883 #define FXPQ3115_CTRL_REG1_OS_OSR_32 ((uint8_t) 0x28) /* OSR = 32 and Minimum Time Between Data Samples 130 */
884  /* ms */
885 #define FXPQ3115_CTRL_REG1_OS_OSR_64 ((uint8_t) 0x30) /* OSR = 64 and Minimum Time Between Data Samples 258 */
886  /* ms */
887 #define FXPQ3115_CTRL_REG1_OS_OSR_128 ((uint8_t) 0x38) /* OSR = 128 and Minimum Time Between Data Samples */
888  /* 512 ms */
889 #define FXPQ3115_CTRL_REG1_RAW_DIS ((uint8_t) 0x00) /* Raw output disabled. */
890 #define FXPQ3115_CTRL_REG1_RAW_EN ((uint8_t) 0x40) /* Raw output enabled. */
891 #define FXPQ3115_CTRL_REG1_ALT_ALT ((uint8_t) 0x80) /* Altimeter Mode. */
892 #define FXPQ3115_CTRL_REG1_ALT_BAR ((uint8_t) 0x00) /* Barometer Mode. */
893 /*------------------------------*/
894 
895 
896 
897 /*--------------------------------
898 ** Register: CTRL_REG2
899 ** Enum: FXPQ3115_CTRL_REG2
900 ** --
901 ** Offset : 0x27 - Control Register 2: Acquisition time step.
902 ** ------------------------------*/
903 typedef union {
904  struct {
905  uint8_t st : 4; /* Auto acquisition time step.. */
906 
907  uint8_t alarm_sel : 1; /* The bit selects the Target value for SRC_PW/SRC_TW and SRC_PTH/SRC_TTH. */
908 
909  uint8_t load_output : 1; /* This is to load the target values for SRC_PW/SRC_TW and SRC_PTH/SRC_TTH. */
910 
911  } b;
912  uint8_t w;
913 } FXPQ3115_CTRL_REG2_t;
914 
915 
916 /*
917 ** CTRL_REG2 - Bit field mask definitions
918 */
919 #define FXPQ3115_CTRL_REG2_ST_MASK ((uint8_t) 0x0F)
920 #define FXPQ3115_CTRL_REG2_ST_SHIFT ((uint8_t) 0)
921 
922 #define FXPQ3115_CTRL_REG2_ALARM_SEL_MASK ((uint8_t) 0x10)
923 #define FXPQ3115_CTRL_REG2_ALARM_SEL_SHIFT ((uint8_t) 4)
924 
925 #define FXPQ3115_CTRL_REG2_LOAD_OUTPUT_MASK ((uint8_t) 0x20)
926 #define FXPQ3115_CTRL_REG2_LOAD_OUTPUT_SHIFT ((uint8_t) 5)
927 
928 
929 /*
930 ** CTRL_REG2 - Bit field value definitions
931 */
932 #define FXPQ3115_CTRL_REG2_ALARM_SEL_USE_TGT ((uint8_t) 0x00) /* The values in P_TGT_MSB, P_TGT_LSB and T_TGT are */
933  /* used. */
934 #define FXPQ3115_CTRL_REG2_ALARM_SEL_USE_OUT ((uint8_t) 0x10) /* The values in OUT_P/OUT_T are used for calculating */
935  /* the interrupts SRC_PW/SRC_TW and SRC_PTH/SRC_TTH. */
936 #define FXPQ3115_CTRL_REG2_LOAD_OUTPUT_DNL ((uint8_t) 0x00) /* Do not load OUT_P/OUT_T as target values. */
937 #define FXPQ3115_CTRL_REG2_LOAD_OUTPUT_NXT_VAL ((uint8_t) 0x20) /* The next values of OUT_P/OUT_T are used to set the */
938  /* target values for the interrupts. */
939 /*------------------------------*/
940 
941 
942 
943 /*--------------------------------
944 ** Register: CTRL_REG3
945 ** Enum: FXPQ3115_CTRL_REG3
946 ** --
947 ** Offset : 0x28 - Control Register 3: Interrupt pin configuration.
948 ** ------------------------------*/
949 typedef union {
950  struct {
951  uint8_t pp_od2 : 1; /* This bit configures the interrupt pad INT2 to Push-Pull or in Open Drain */
952  /* mode. */
953 
954  uint8_t ipol2 : 1; /* Interrupt Polarity active high, or active low on interrupt pad INT2. */
955 
956  uint8_t _reserved_ : 2;
957  uint8_t pp_od1 : 1; /* This bit configures the interrupt pad INT1 to Push-Pull or in Open Drain */
958  /* mode. */
959 
960  uint8_t ipol1 : 1; /* Interrupt Polarity active high, or active low on interrupt pad INT1. */
961 
962  } b;
963  uint8_t w;
964 } FXPQ3115_CTRL_REG3_t;
965 
966 
967 /*
968 ** CTRL_REG3 - Bit field mask definitions
969 */
970 #define FXPQ3115_CTRL_REG3_PP_OD2_MASK ((uint8_t) 0x01)
971 #define FXPQ3115_CTRL_REG3_PP_OD2_SHIFT ((uint8_t) 0)
972 
973 #define FXPQ3115_CTRL_REG3_IPOL2_MASK ((uint8_t) 0x02)
974 #define FXPQ3115_CTRL_REG3_IPOL2_SHIFT ((uint8_t) 1)
975 
976 #define FXPQ3115_CTRL_REG3_PP_OD1_MASK ((uint8_t) 0x10)
977 #define FXPQ3115_CTRL_REG3_PP_OD1_SHIFT ((uint8_t) 4)
978 
979 #define FXPQ3115_CTRL_REG3_IPOL1_MASK ((uint8_t) 0x20)
980 #define FXPQ3115_CTRL_REG3_IPOL1_SHIFT ((uint8_t) 5)
981 
982 
983 /*
984 ** CTRL_REG3 - Bit field value definitions
985 */
986 #define FXPQ3115_CTRL_REG3_PP_OD2_INTPULLUP ((uint8_t) 0x00) /* Internal Pull-up. */
987 #define FXPQ3115_CTRL_REG3_PP_OD2_OPENDRAIN ((uint8_t) 0x01) /* Open drain. */
988 #define FXPQ3115_CTRL_REG3_IPOL2_LOW ((uint8_t) 0x00) /* Active low. */
989 #define FXPQ3115_CTRL_REG3_IPOL2_HIGH ((uint8_t) 0x02) /* Active high. */
990 #define FXPQ3115_CTRL_REG3_PP_OD1_INTPULLUP ((uint8_t) 0x00) /* Internal Pull-up. */
991 #define FXPQ3115_CTRL_REG3_PP_OD1_OPENDRAIN ((uint8_t) 0x10) /* Open drain. */
992 #define FXPQ3115_CTRL_REG3_IPOL1_LOW ((uint8_t) 0x00) /* Active low. */
993 #define FXPQ3115_CTRL_REG3_IPOL1_HIGH ((uint8_t) 0x20) /* Active high. */
994 /*------------------------------*/
995 
996 
997 
998 /*--------------------------------
999 ** Register: CTRL_REG4
1000 ** Enum: FXPQ3115_CTRL_REG4
1001 ** --
1002 ** Offset : 0x29 - Control Register 4: Interrupt enables.
1003 ** ------------------------------*/
1004 typedef union {
1005  struct {
1006  uint8_t int_en_tchg : 1; /* Temperature Change Interrupt Enable. */
1007 
1008  uint8_t int_en_pchg : 1; /* Pressure Change Interrupt Enable. */
1009 
1010  uint8_t int_en_tth : 1; /* Temperature Threshold Interrupt Enable. */
1011 
1012  uint8_t int_en_pth : 1; /* Pressure Threshold Interrupt Enable. */
1013 
1014  uint8_t int_en_tw : 1; /* Temperature window Interrupt Enable. */
1015 
1016  uint8_t int_en_pw : 1; /* Pressure window Interrupt Enable. */
1017 
1018  uint8_t int_en_fifo : 1; /* FIFO Interrupt Enable. */
1019 
1020  uint8_t int_en_drdy : 1; /* Data Ready Interrupt Enable. */
1021 
1022  } b;
1023  uint8_t w;
1024 } FXPQ3115_CTRL_REG4_t;
1025 
1026 
1027 /*
1028 ** CTRL_REG4 - Bit field mask definitions
1029 */
1030 #define FXPQ3115_CTRL_REG4_INT_EN_TCHG_MASK ((uint8_t) 0x01)
1031 #define FXPQ3115_CTRL_REG4_INT_EN_TCHG_SHIFT ((uint8_t) 0)
1032 
1033 #define FXPQ3115_CTRL_REG4_INT_EN_PCHG_MASK ((uint8_t) 0x02)
1034 #define FXPQ3115_CTRL_REG4_INT_EN_PCHG_SHIFT ((uint8_t) 1)
1035 
1036 #define FXPQ3115_CTRL_REG4_INT_EN_TTH_MASK ((uint8_t) 0x04)
1037 #define FXPQ3115_CTRL_REG4_INT_EN_TTH_SHIFT ((uint8_t) 2)
1038 
1039 #define FXPQ3115_CTRL_REG4_INT_EN_PTH_MASK ((uint8_t) 0x08)
1040 #define FXPQ3115_CTRL_REG4_INT_EN_PTH_SHIFT ((uint8_t) 3)
1041 
1042 #define FXPQ3115_CTRL_REG4_INT_EN_TW_MASK ((uint8_t) 0x10)
1043 #define FXPQ3115_CTRL_REG4_INT_EN_TW_SHIFT ((uint8_t) 4)
1044 
1045 #define FXPQ3115_CTRL_REG4_INT_EN_PW_MASK ((uint8_t) 0x20)
1046 #define FXPQ3115_CTRL_REG4_INT_EN_PW_SHIFT ((uint8_t) 5)
1047 
1048 #define FXPQ3115_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40)
1049 #define FXPQ3115_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6)
1050 
1051 #define FXPQ3115_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x80)
1052 #define FXPQ3115_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 7)
1053 
1054 
1055 /*
1056 ** CTRL_REG4 - Bit field value definitions
1057 */
1058 #define FXPQ3115_CTRL_REG4_INT_EN_TCHG_INTDISABLED ((uint8_t) 0x00) /* Temperature Change interrupt disabled. */
1059 #define FXPQ3115_CTRL_REG4_INT_EN_TCHG_INTENABLED ((uint8_t) 0x01) /* Temperature Change interrupt enabled */
1060 #define FXPQ3115_CTRL_REG4_INT_EN_PCHG_INTDISABLED ((uint8_t) 0x00) /* Pressure Change interrupt disabled. */
1061 #define FXPQ3115_CTRL_REG4_INT_EN_PCHG_INTENABLED ((uint8_t) 0x02) /* Pressure Change interrupt enabled */
1062 #define FXPQ3115_CTRL_REG4_INT_EN_TTH_INTDISABLED ((uint8_t) 0x00) /* Temperature Threshold interrupt disabled. */
1063 #define FXPQ3115_CTRL_REG4_INT_EN_TTH_INTENABLED ((uint8_t) 0x04) /* Temperature Threshold interrupt enabled */
1064 #define FXPQ3115_CTRL_REG4_INT_EN_PTH_INTDISABLED ((uint8_t) 0x00) /* Pressure Threshold interrupt disabled. */
1065 #define FXPQ3115_CTRL_REG4_INT_EN_PTH_INTENABLED ((uint8_t) 0x08) /* Pressure Threshold interrupt enabled */
1066 #define FXPQ3115_CTRL_REG4_INT_EN_TW_INTDISABLED ((uint8_t) 0x00) /* Temperature window interrupt disabled. */
1067 #define FXPQ3115_CTRL_REG4_INT_EN_TW_INTENABLED ((uint8_t) 0x10) /* Temperature window interrupt enabled */
1068 #define FXPQ3115_CTRL_REG4_INT_EN_PW_INTDISABLED ((uint8_t) 0x00) /* Pressure window interrupt disabled. */
1069 #define FXPQ3115_CTRL_REG4_INT_EN_PW_INTENABLED ((uint8_t) 0x20) /* Pressure window interrupt enabled */
1070 #define FXPQ3115_CTRL_REG4_INT_EN_FIFO_INTDISABLED ((uint8_t) 0x00) /* FIFO interrupt disabled. */
1071 #define FXPQ3115_CTRL_REG4_INT_EN_FIFO_INTENABLED ((uint8_t) 0x40) /* FIFO interrupt enabled */
1072 #define FXPQ3115_CTRL_REG4_INT_EN_DRDY_INTDISABLED ((uint8_t) 0x00) /* Data Ready interrupt disabled. */
1073 #define FXPQ3115_CTRL_REG4_INT_EN_DRDY_INTENABLED ((uint8_t) 0x80) /* Data Ready interrupt enabled. */
1074 /*------------------------------*/
1075 
1076 
1077 
1078 /*--------------------------------
1079 ** Register: CTRL_REG5
1080 ** Enum: FXPQ3115_CTRL_REG5
1081 ** --
1082 ** Offset : 0x2A - Control Register 5: Interrupt output pin assignment.
1083 ** ------------------------------*/
1084 typedef union {
1085  struct {
1086  uint8_t int_cfg_tchg : 1; /* Temperature Change INT1/INT2 Configuration. */
1087 
1088  uint8_t int_cfg_pchg : 1; /* Pressure Change INT1/INT2 Configuration. */
1089 
1090  uint8_t int_cfg_tth : 1; /* Temperature Threshold INT1/INT2 Configuration. */
1091 
1092  uint8_t int_cfg_pth : 1; /* Pressure Threshold INT1/INT2 Configuration. */
1093 
1094  uint8_t int_cfg_tw : 1; /* Temperature window INT1/INT2 Configuration. */
1095 
1096  uint8_t int_cfg_pw : 1; /* Pressure window INT1/INT2 Configuration. */
1097 
1098  uint8_t int_cfg_fifo : 1; /* FIFO INT1/INT2 Configuration. */
1099 
1100  uint8_t int_cfg_drdy : 1; /* Data Ready INT1/INT2 Configuration. */
1101 
1102  } b;
1103  uint8_t w;
1104 } FXPQ3115_CTRL_REG5_t;
1105 
1106 
1107 /*
1108 ** CTRL_REG5 - Bit field mask definitions
1109 */
1110 #define FXPQ3115_CTRL_REG5_INT_CFG_TCHG_MASK ((uint8_t) 0x01)
1111 #define FXPQ3115_CTRL_REG5_INT_CFG_TCHG_SHIFT ((uint8_t) 0)
1112 
1113 #define FXPQ3115_CTRL_REG5_INT_CFG_PCHG_MASK ((uint8_t) 0x02)
1114 #define FXPQ3115_CTRL_REG5_INT_CFG_PCHG_SHIFT ((uint8_t) 1)
1115 
1116 #define FXPQ3115_CTRL_REG5_INT_CFG_TTH_MASK ((uint8_t) 0x04)
1117 #define FXPQ3115_CTRL_REG5_INT_CFG_TTH_SHIFT ((uint8_t) 2)
1118 
1119 #define FXPQ3115_CTRL_REG5_INT_CFG_PTH_MASK ((uint8_t) 0x08)
1120 #define FXPQ3115_CTRL_REG5_INT_CFG_PTH_SHIFT ((uint8_t) 3)
1121 
1122 #define FXPQ3115_CTRL_REG5_INT_CFG_TW_MASK ((uint8_t) 0x10)
1123 #define FXPQ3115_CTRL_REG5_INT_CFG_TW_SHIFT ((uint8_t) 4)
1124 
1125 #define FXPQ3115_CTRL_REG5_INT_CFG_PW_MASK ((uint8_t) 0x20)
1126 #define FXPQ3115_CTRL_REG5_INT_CFG_PW_SHIFT ((uint8_t) 5)
1127 
1128 #define FXPQ3115_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40)
1129 #define FXPQ3115_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6)
1130 
1131 #define FXPQ3115_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x80)
1132 #define FXPQ3115_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 7)
1133 
1134 
1135 /*
1136 ** CTRL_REG5 - Bit field value definitions
1137 */
1138 #define FXPQ3115_CTRL_REG5_INT_CFG_TCHG_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1139 #define FXPQ3115_CTRL_REG5_INT_CFG_TCHG_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 Pin. */
1140 #define FXPQ3115_CTRL_REG5_INT_CFG_PCHG_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1141 #define FXPQ3115_CTRL_REG5_INT_CFG_PCHG_INT1 ((uint8_t) 0x02) /* Interrupt is routed to INT1 Pin. */
1142 #define FXPQ3115_CTRL_REG5_INT_CFG_TTH_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1143 #define FXPQ3115_CTRL_REG5_INT_CFG_TTH_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 Pin. */
1144 #define FXPQ3115_CTRL_REG5_INT_CFG_PTH_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1145 #define FXPQ3115_CTRL_REG5_INT_CFG_PTH_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 Pin. */
1146 #define FXPQ3115_CTRL_REG5_INT_CFG_TW_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1147 #define FXPQ3115_CTRL_REG5_INT_CFG_TW_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 Pin. */
1148 #define FXPQ3115_CTRL_REG5_INT_CFG_PW_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1149 #define FXPQ3115_CTRL_REG5_INT_CFG_PW_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 Pin. */
1150 #define FXPQ3115_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1151 #define FXPQ3115_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 Pin. */
1152 #define FXPQ3115_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1153 #define FXPQ3115_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 Pin. */
1154 /*------------------------------*/
1155 
1156 
1157 
1158 /*--------------------------------
1159 ** Register: OFF_P
1160 ** Enum: FXPQ3115_OFF_P
1161 ** --
1162 ** Offset : 0x2B - Pressure data offset.
1163 ** ------------------------------*/
1164 typedef uint8_t FXPQ3115_OFF_P_t;
1165 
1166 
1167 
1168 /*--------------------------------
1169 ** Register: OFF_T
1170 ** Enum: FXPQ3115_OFF_T
1171 ** --
1172 ** Offset : 0x2C - Temperature data offset.
1173 ** ------------------------------*/
1174 typedef uint8_t FXPQ3115_OFF_T_t;
1175 
1176 
1177 
1178 /*--------------------------------
1179 ** Register: OFF_H
1180 ** Enum: FXPQ3115_OFF_H
1181 ** --
1182 ** Offset : 0x2D - Altitude data offset.
1183 ** ------------------------------*/
1184 typedef uint8_t FXPQ3115_OFF_H_t;
1185 
1186 
1187 #endif /* FXPQ3115_H_ */
FXPQ3115_P_TGT_MSB_t
uint8_t FXPQ3115_P_TGT_MSB_t
Definition: fxpq3115.h:602
FXPQ3115_P_MAX_CSB_t
uint8_t FXPQ3115_P_MAX_CSB_t
Definition: fxpq3115.h:750
FXPQ3115_WHO_AM_I_t
uint8_t FXPQ3115_WHO_AM_I_t
Definition: fxpq3115.h:329
FXPQ3115_P_WND_LSB_t
uint8_t FXPQ3115_P_WND_LSB_t
Definition: fxpq3115.h:640
FXPQ3115_OUT_P_MSB_t
uint8_t FXPQ3115_OUT_P_MSB_t
Definition: fxpq3115.h:84
FXPQ3115_P_TGT_LSB_t
uint8_t FXPQ3115_P_TGT_LSB_t
Definition: fxpq3115.h:611
FXPQ3115_T_MAX_MSB_t
uint8_t FXPQ3115_T_MAX_MSB_t
Definition: fxpq3115.h:786
FXPQ3115_OUT_P_DELTA_MSB_t
uint8_t FXPQ3115_OUT_P_DELTA_MSB_t
Definition: fxpq3115.h:248
FXPQ3115_OUT_P_DELTA_CSB_t
uint8_t FXPQ3115_OUT_P_DELTA_CSB_t
Definition: fxpq3115.h:257
FXPQ3115_STATUS_t
uint8_t FXPQ3115_STATUS_t
Definition: fxpq3115.h:74
FXPQ3115_P_MIN_CSB_t
uint8_t FXPQ3115_P_MIN_CSB_t
Definition: fxpq3115.h:669
FXPQ3115_P_MAX_MSB_t
uint8_t FXPQ3115_P_MAX_MSB_t
Definition: fxpq3115.h:741
FXPQ3115_BAR_IN_MSB_t
uint8_t FXPQ3115_BAR_IN_MSB_t
Definition: fxpq3115.h:583
FXPQ3115_OUT_T_MSB_t
uint8_t FXPQ3115_OUT_T_MSB_t
Definition: fxpq3115.h:129
FXPQ3115_OFF_T_t
uint8_t FXPQ3115_OFF_T_t
Definition: fxpq3115.h:1174
FXPQ3115_T_TGT_t
uint8_t FXPQ3115_T_TGT_t
Definition: fxpq3115.h:621
FXPQ3115_OUT_P_CSB_t
uint8_t FXPQ3115_OUT_P_CSB_t
Definition: fxpq3115.h:93
FXPQ3115_T_MIN_MSB_t
uint8_t FXPQ3115_T_MIN_MSB_t
Definition: fxpq3115.h:705
FXPQ3115_P_MIN_MSB_t
uint8_t FXPQ3115_P_MIN_MSB_t
Definition: fxpq3115.h:660
FXPQ3115_SYSMOD_t::sysmod
uint8_t sysmod
Definition: fxpq3115.h:443
FXPQ3115_F_DATA_t
uint8_t FXPQ3115_F_DATA_t
Definition: fxpq3115.h:383
FXPQ3115_P_WND_MSB_t
uint8_t FXPQ3115_P_WND_MSB_t
Definition: fxpq3115.h:631
FXPQ3115_F_STATUS_t::f_wmkf_flag
uint8_t f_wmkf_flag
Definition: fxpq3115.h:344
FXPQ3115_T_WND_t
uint8_t FXPQ3115_T_WND_t
Definition: fxpq3115.h:650
FXPQ3115_TIME_DLY_t
uint8_t FXPQ3115_TIME_DLY_t
Definition: fxpq3115.h:431
FXPQ3115_OFF_H_t
uint8_t FXPQ3115_OFF_H_t
Definition: fxpq3115.h:1184
FXPQ3115_OFF_P_t
uint8_t FXPQ3115_OFF_P_t
Definition: fxpq3115.h:1164
FXPQ3115_BAR_IN_LSB_t
uint8_t FXPQ3115_BAR_IN_LSB_t
Definition: fxpq3115.h:592
FXPQ3115_OUT_T_DELTA_MSB_t
uint8_t FXPQ3115_OUT_T_DELTA_MSB_t
Definition: fxpq3115.h:293
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