ISSDK  1.8
IoT Sensing Software Development Kit
fxls896x.h
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1 /*
2  * Copyright 2021 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 /**
8  * @file fxls896x.h
9  * @brief This file contains the FXLS896XAF Accelerometer register definitions, access macros, and
10  * device access functions.
11  */
12 #ifndef FXLS896X_H_
13 #define FXLS896X_H_
14 #include <stddef.h>
15 #include <stdint.h>
16 #include <stdbool.h>
17 /**
18  * @brief The FXLS896x types
19  */
20 
21 /**
22  **
23  ** @brief The FXLS896x Sensor Internal Register Map.
24  */
25 enum
26 {
27  FXLS896x_INT_STATUS = 0x00,
28  FXLS896x_TEMP_OUT = 0x01,
29  FXLS896x_VECM_LSB = 0x02,
30  FXLS896x_VECM_MSB = 0x03,
31  FXLS896x_OUT_X_LSB = 0x04,
32  FXLS896x_OUT_X_MSB = 0x05,
33  FXLS896x_OUT_Y_LSB = 0x06,
34  FXLS896x_OUT_Y_MSB = 0x07,
35  FXLS896x_OUT_Z_LSB = 0x08,
36  FXLS896x_OUT_Z_MSB = 0x09,
37  FXLS896x_BUF_STATUS = 0x0B,
38  FXLS896x_BUF_X_LSB = 0x0C,
39  FXLS896x_BUF_X_MSB = 0x0D,
40  FXLS896x_BUF_Y_LSB = 0x0E,
41  FXLS896x_BUF_Y_MSB = 0x0F,
42  FXLS896x_BUF_Z_LSB = 0x10,
43  FXLS896x_BUF_Z_MSB = 0x11,
44  FXLS896x_PROD_REV = 0x12,
45  FXLS896x_WHO_AM_I = 0x13,
46  FXLS896x_SYS_MODE = 0x14,
47  FXLS896x_SENS_CONFIG1 = 0x15,
48  FXLS896x_SENS_CONFIG2 = 0x16,
49  FXLS896x_SENS_CONFIG3 = 0x17,
50  FXLS896x_SENS_CONFIG4 = 0x18,
51  FXLS896x_SENS_CONFIG5 = 0x19,
52  FXLS896x_WAKE_IDLE_LSB = 0x1A,
53  FXLS896x_WAKE_IDLE_MSB = 0x1B,
54  FXLS896x_SLEEP_IDLE_LSB = 0x1C,
55  FXLS896x_SLEEP_IDLE_MSB = 0x1D,
56  FXLS896x_ASLP_COUNT_LSB = 0x1E,
57  FXLS896x_ASLP_COUNT_MSB = 0x1F,
58  FXLS896x_INT_EN = 0x20,
59  FXLS896x_INT_PIN_SEL = 0x21,
60  FXLS896x_OFF_X = 0x22,
61  FXLS896x_OFF_Y = 0x23,
62  FXLS896x_OFF_Z = 0x24,
63  FXLS896x_BUF_CONFIG1 = 0x26,
64  FXLS896x_BUF_CONFIG2 = 0x27,
65  FXLS896x_ORIENT_STATUS = 0x28,
66  FXLS896x_ORIENT_CONFIG = 0x29,
67  FXLS896x_ORIENT_DBCOUNT = 0x2A,
68  FXLS896x_ORIENT_BF_ZCOMP = 0x2B,
69  FXLS896x_ORIENT_THS_REG = 0x2C,
70  FXLS896x_SDCD_INT_SRC1 = 0x2D,
71  FXLS896x_SDCD_INT_SRC2 = 0x2E,
72  FXLS896x_SDCD_CONFIG1 = 0x2F,
73  FXLS896x_SDCD_CONFIG2 = 0x30,
74  FXLS896x_SDCD_OT_DBCNT = 0x31,
75  FXLS896x_SDCD_WT_DBCNT = 0x32,
76  FXLS896x_SDCD_LTHS_LSB = 0x33,
77  FXLS896x_SDCD_LTHS_MSB = 0x34,
78  FXLS896x_SDCD_UTHS_LSB = 0x35,
79  FXLS896x_SDCD_UTHS_MSB = 0x36,
80  FXLS896x_SELF_TEST_CONFIG1 = 0x37,
81  FXLS896x_SELF_TEST_CONFIG2 = 0x38,
82 };
83 
84 #define FXLS896x_DEVICE_ADDRESS_SA0_0 (0x18) /*!< Device Address Value. */
85 #define FXLS896x_DEVICE_ADDRESS_SA0_1 (0x19) /*!< Device Address Value. */
86 #define FXLS8962_WHOAMI_VALUE (0x62) /*!< Who AM I Value. */
87 #define FXLS8964_WHOAMI_VALUE (0x84) /*!< Who AM I Value.of FXLS8964AF */
88 #define FXLS8967_WHOAMI_VALUE (0x87) /*!< Who AM I Value.of FXLS8967AF */
89 #define FXLS8968_WHOAMI_VALUE (0x88) /*!< Who AM I Value.of FXLS8968CF */
90 #define FXLS8974_WHOAMI_VALUE (0x86) /*!< Who AM I Value.of FXLS8974CF */
91 #define FXLS896x_TBOOT_MAX 20 /*!< Maximum safe value for TBOOT1/2 in ms (1ms, 17.7ms)=~20ms. */
92 
93 /*--------------------------------
94 ** Register: INT_STATUS
95 ** Enum: FXLS896x_INT_STATUS
96 ** --
97 ** Offset : 0x00 Interrupt and system status event flags.
98 ** ------------------------------*/
99 typedef union
100 {
101  struct
102  {
103  uint8_t src_boot : 1; /* System boot complete event flag. */
104 
105  uint8_t src_aslp : 1; /* Auto-Wake/Sleep event status flag. */
106 
107  uint8_t src_orient : 1; /* Orientation change event flag. */
108 
109  uint8_t src_sdcd_wt : 1; /* SDCD within thresholds condition event flag. */
110 
111  uint8_t src_sdcd_ot : 1; /* SDCD outside of threshold condition event flag. */
112 
113  uint8_t src_buf : 1;/* Output data buffer status event flag. */
114 
115  uint8_t src_ovf : 1; /* Output data overflow event flag. */
116 
117  uint8_t src_drdy : 1; /* Output data ready event flag. */
118 
119  } b;
120  uint8_t w;
121 } FXLS896x_INT_STATUS_t;
122 
123 /*
124 ** INT_STATUS - Bit field mask definitions
125 */
126 #define FXLS896x_INT_STATUS_SRC_BOOT_MASK ((uint8_t)0x01)
127 #define FXLS896x_INT_STATUS_SRC_BOOT_SHIFT ((uint8_t)0)
128 
129 #define FXLS896x_INT_STATUS_SRC_ASLP_MASK ((uint8_t)0x02)
130 #define FXLS896x_INT_STATUS_SRC_ASLP_SHIFT ((uint8_t)1)
131 
132 #define FXLS896x_INT_STATUS_SRC_ORIENT_MASK ((uint8_t)0x04)
133 #define FXLS896x_INT_STATUS_SRC_ORIENT_SHIFT ((uint8_t)2)
134 
135 #define FXLS896x_INT_STATUS_SRC_SDCD_WT_MASK ((uint8_t)0x08)
136 #define FXLS896x_INT_STATUS_SRC_SDCD_WT_SHIFT ((uint8_t)3)
137 
138 #define FXLS896x_INT_STATUS_SRC_SDCD_OT_MASK ((uint8_t)0x10)
139 #define FXLS896x_INT_STATUS_SRC_SDCD_OT_SHIFT ((uint8_t)4)
140 
141 #define FXLS896x_INT_STATUS_SRC_BUF_MASK ((uint8_t)0x20)
142 #define FXLS896x_INT_STATUS_SRC_BUF_SHIFT ((uint8_t)5)
143 
144 #define FXLS896x_INT_STATUS_SRC_OVF_MASK ((uint8_t)0x40)
145 #define FXLS896x_INT_STATUS_SRC_OVF_SHIFT ((uint8_t)6)
146 
147 #define FXLS896x_INT_STATUS_SRC_DRDY_MASK ((uint8_t)0x80)
148 #define FXLS896x_INT_STATUS_SRC_DRDY_SHIFT ((uint8_t)7)
149 
150 /*------------------------------*/
151 
152 /*--------------------------------
153 ** Register: TEMP_OUT
154 ** Enum: FXLS896x_TEMP_OUT
155 ** --
156 ** Offset : 0x01 Temperature output data.
157 ** ------------------------------*/
158 typedef uint8_t FXLS896x_TEMP_OUT_t;
159 
160 /*--------------------------------
161 ** Register: VECM_LSB
162 ** Enum: FXLS896x_VECM_LSB
163 ** --
164 ** Offset : 0x02 12-bit unsigned vector magnitude LSB.
165 ** ------------------------------*/
166 typedef uint8_t FXLS896x_VECM_LSB_t;
167 
168 /*--------------------------------
169 ** Register: VECM_MSB
170 ** Enum: FXLS896x_VECM_MSB
171 ** --
172 ** Offset : 0x03 12-bit unsigned vector magnitude MSB.
173 ** ------------------------------*/
174 typedef uint8_t FXLS896x_VECM_MSB_t;
175 
176 /*--------------------------------
177 ** Register: OUT_X_LSB
178 ** Enum: FXLS896x_OUT_X_LSB
179 ** --
180 ** Offset : 0x04 LSB of current 12-bit X-axis accelerometer output data.
181 ** ------------------------------*/
182 typedef uint8_t FXLS896x_OUT_X_LSB_t;
183 
184 /*--------------------------------
185 ** Register: OUT_X_MSB
186 ** Enum: FXLS896x_OUT_X_MSB
187 ** --
188 ** Offset : 0x05 MSB of current 12-bit X-axis accelerometer output data.
189 ** ------------------------------*/
190 typedef uint8_t FXLS896x_OUT_X_MSB_t;
191 
192 /*--------------------------------
193 ** Register: OUT_Y_LSB
194 ** Enum: FXLS896x_OUT_Y_LSB
195 ** --
196 ** Offset : 0x06 LSB of current 12-bit Y-axis accelerometer output data.
197 ** ------------------------------*/
198 typedef uint8_t FXLS896x_OUT_Y_LSB_t;
199 
200 /*--------------------------------
201 ** Register: OUT_Y_MSB
202 ** Enum: FXLS896x_OUT_Y_MSB
203 ** --
204 ** Offset : 0x07 MSB of current 12-bit Y-axis accelerometer output data.
205 ** ------------------------------*/
206 typedef uint8_t FXLS896x_OUT_Y_MSB_t;
207 
208 /*--------------------------------
209 ** Register: OUT_Z_LSB
210 ** Enum: FXLS896x_OUT_Z_LSB
211 ** --
212 ** Offset : 0x08 LSB of current 12-bit Z-axis accelerometer output data.
213 ** ------------------------------*/
214 typedef uint8_t FXLS896x_OUT_Z_LSB_t;
215 
216 /*--------------------------------
217 ** Register: OUT_Z_MSB
218 ** Enum: FXLS896x_OUT_Z_MSB
219 ** --
220 ** Offset : 0x09 MSB of current 12-bit Z-axis accelerometer output data.
221 ** ------------------------------*/
222 typedef uint8_t FXLS896x_OUT_Z_MSB_t;
223 
224 /*--------------------------------
225 ** Register: BUF_STATUS
226 ** Enum: FXLS896x_BUF_STATUS
227 ** --
228 ** Offset : 0x0B Buf status.
229 ** ------------------------------*/
230 typedef union {
231  struct {
232  uint8_t buf_cnt : 6; /* Count of the acceleration data samples */
233 
234  uint8_t buf_ovf : 1; /* Buffer Overflow Event Flag */
235 
236  uint8_t buf_wmrk : 1; /* Buffer Watermark Event Flag */
237 
238  } b;
239  uint8_t w;
240 } FXLS896x_BUF_STATUS_t;
241 
242 
243 /*
244 ** BUF_STATUS - Bit field mask definitions
245 */
246 #define FXLS896x_BUF_STATUS_BUF_CNT_MASK ((uint8_t) 0x3F)
247 #define FXLS896x_BUF_STATUS_BUF_CNT_SHIFT ((uint8_t) 0)
248 
249 #define FXLS896x_BUF_STATUS_BUF_OVF_MASK ((uint8_t) 0x40)
250 #define FXLS896x_BUF_STATUS_BUF_OVF_SHIFT ((uint8_t) 6)
251 
252 #define FXLS896x_BUF_STATUS_BUF_WMRK_MASK ((uint8_t) 0x80)
253 #define FXLS896x_BUF_STATUS_BUF_WMRK_SHIFT ((uint8_t) 7)
254 
255 
256 
257 /*--------------------------------
258 ** Register: BUF_X_LSB
259 ** Enum: FXLS896x_BUF_X_LSB
260 ** --
261 ** Offset : 0x0C LSB Head Tail output buffer buffer X axis.
262 ** ------------------------------*/
263 typedef uint8_t FXLS896x_BUF_X_LSB_t;
264 
265 
266 /*--------------------------------
267 ** Register: BUF_X_MSB
268 ** Enum: FXLS896x_BUF_X_MSB
269 ** --
270 ** Offset : 0x0D MSB Head Tail output buffer buffer Z axis.
271 ** ------------------------------*/
272 typedef uint8_t FXLS896x_BUF_X_MSB_t;
273 
274 
275 /*--------------------------------
276 ** Register: BUF_Y_LSB
277 ** Enum: FXLS896x_BUF_Y_LSB
278 ** --
279 ** Offset : 0x0E LSB Head Tail output buffer buffer Y axis.
280 ** ------------------------------*/
281 typedef uint8_t FXLS896x_BUF_Y_LSB_t;
282 
283 
284 /*--------------------------------
285 ** Register: BUF_Y_MSB
286 ** Enum: FXLS896x_BUF_Y_MSB
287 ** --
288 ** Offset : 0x0F MSB Head Tail output buffer buffer Y axis.
289 ** ------------------------------*/
290 typedef uint8_t FXLS896x_BUF_Y_MSB_t;
291 
292 
293 /*--------------------------------
294 ** Register: BUF_Z_LSB
295 ** Enum: FXLS896x_BUF_Z_LSB
296 ** --
297 ** Offset : 0x10 LSB Head Tail output buffer buffer Z axis.
298 ** ------------------------------*/
299 typedef uint8_t FXLS896x_BUF_Z_LSB_t;
300 
301 
302 /*--------------------------------
303 ** Register: BUF_Z_MSB
304 ** Enum: FXLS896x_BUF_Z_MSB
305 ** --
306 ** Offset : 0x11 MSB Head Tail output buffer buffer Z axis.
307 ** ------------------------------*/
308 typedef uint8_t FXLS896x_BUF_Z_MSB_t;
309 
310 /*--------------------------------
311 ** Register: PROD_REV
312 ** Enum: FXLS896x_PROD_REV
313 ** --
314 ** Offset : 0x12 Product revision number in BCD format.
315 ** ------------------------------*/
316 typedef union
317 {
318  struct
319  {
320  uint8_t prod_rev_min : 4; /* Product revision info, minor product revision value with range 0 to 9 in */
321  /* BCD format. */
322 
323  uint8_t prod_rev_maj : 4; /* Product revision info, major product revision value with range 1 to 9 in */
324  /* BCD format. */
325 
326  } b;
327  uint8_t w;
328 } FXLS896x_PROD_REV_t;
329 
330 /*
331 ** PROD_REV - Bit field mask definitions
332 */
333 #define FXLS896x_PROD_REV_PROD_REV_MIN_MASK ((uint8_t)0x0F)
334 #define FXLS896x_PROD_REV_PROD_REV_MIN_SHIFT ((uint8_t)0)
335 
336 #define FXLS896x_PROD_REV_PROD_REV_MAJ_MASK ((uint8_t)0xF0)
337 #define FXLS896x_PROD_REV_PROD_REV_MAJ_SHIFT ((uint8_t)4)
338 
339 /*--------------------------------
340 ** Register: WHO_AM_I
341 ** Enum: FXLS896x_WHO_AM_I
342 ** --
343 ** Offset : 0x13 8-bit NXP unique sensor Product ID.
344 ** ------------------------------*/
345 typedef uint8_t FXLS896x_WHO_AM_I_t;
346 
347 /*--------------------------------
348 ** Register: SYS_MODE
349 ** Enum: FXLS896x_SYS_MODE
350 ** --
351 ** Offset : 0x14 Current System Operating Mode.
352 ** ------------------------------*/
353 typedef union
354 {
355  struct
356  {
357  uint8_t sys_mode : 2; /* Current System operating mode. */
358 
359  uint8_t buf_gate_cnt : 5; /* number of OOR periods that have elapsed since the BUF _GATE_ERR flag was asserted. */
360 
361  uint8_t buf_gate_error : 1; /* Buffer gate error flag. */
362 
363  } b;
364  uint8_t w;
365 } FXLS896x_SYS_MODE_t;
366 
367 /*
368 ** SYS_MODE - Bit field mask definitions
369 */
370 #define FXLS896x_SYS_MODE_BUF_GATE_ERROR_MASK ((uint8_t)0x03)
371 #define FXLS896x_SYS_MODE_BUF_GATE_ERROR_SHIFT ((uint8_t)0)
372 
373 #define FXLS896x_SYS_MODE_BUF_GATE_CNT_MASK ((uint8_t)0x7C)
374 #define FXLS896x_SYS_MODE_BUF_GATE_CNT_SHIFT ((uint8_t)2)
375 
376 #define FXLS896x_SYS_MODE_SYS_MODE_MASK ((uint8_t)0x80)
377 #define FXLS896x_SYS_MODE_SYS_MODE_SHIFT ((uint8_t)7)
378 
379 /*
380 ** SYS_MODE - Bit field value definitions
381 */
382 #define FXLS896x_SYS_MODE_BUF_GARE_ERROR_NO ((uint8_t)0x00) /* Not Detected. */
383 #define FXLS896x_SYS_MODE_BUF_GARE_ERROR_YES ((uint8_t)0x80)/* Detected. */
384 #define FXLS896x_SYS_MODE_SYS_MODE_STANDBY ((uint8_t)0x00) /* Standby Mode. */
385 #define FXLS896x_SYS_MODE_SYS_MODE_WAKE ((uint8_t)0x01) /* Wake Mode. */
386 #define FXLS896x_SYS_MODE_SYS_MODE_SLEEP ((uint8_t)0x02) /* Sleep Mode. */
387 #define FXLS896x_SYS_MODE_SYS_MODE_EXT_TRIG ((uint8_t)0x03) /* External Trigger Mode. */
388  /*------------------------------*/
389 
390 /*--------------------------------
391 ** Register: SENS_CONFIG1
392 ** Enum: FXLS896x_SENS_CONFIG1
393 ** --
394 ** Offset : 0x15 Configuration register 1.
395 ** ------------------------------*/
396 typedef union
397 {
398  struct
399  {
400  uint8_t active : 1; /* Standby/Active mode selection */
401 
402  uint8_t fsr : 2; /* Full-scale measurement range (FSR) selection. */
403 
404  uint8_t spi_m : 1; /* SPI interface mode selection; selects between 3- and 4-wire operating */
405  /* modes for the SPI interface. */
406 
407  uint8_t st_pol : 1; /* Self-Test Displacement Polarity */
408 
409  uint8_t st_axis_sel : 2; /* Self-Test Axis Selection */
410 
411  uint8_t rst : 1; /* The RST bit may be used to initiate a software reset. */
412 
413  } b;
414  uint8_t w;
415 } FXLS896x_SENS_CONFIG1_t;
416 
417 /*
418 ** SENS_CONFIG1 - Bit field mask definitions
419 */
420 #define FXLS896x_SENS_CONFIG1_ACTIVE_MASK ((uint8_t)0x01)
421 #define FXLS896x_SENS_CONFIG1_ACTIVE_SHIFT ((uint8_t)0)
422 
423 #define FXLS896x_SENS_CONFIG1_FSR_MASK ((uint8_t)0x06)
424 #define FXLS896x_SENS_CONFIG1_FSR_SHIFT ((uint8_t)1)
425 
426 #define FXLS896x_SENS_CONFIG1_SPI_M_MASK ((uint8_t)0x08)
427 #define FXLS896x_SENS_CONFIG1_SPI_M_SHIFT ((uint8_t)3)
428 
429 #define FXLS896x_SENS_CONFIG1_ST_POL_MASK ((uint8_t)0x10)
430 #define FXLS896x_SENS_CONFIG1_ST_POL_SHIFT ((uint8_t)4)
431 
432 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_MASK ((uint8_t)0x60)
433 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_SHIFT ((uint8_t)5)
434 
435 #define FXLS896x_SENS_CONFIG1_RST_MASK ((uint8_t)0x80)
436 #define FXLS896x_SENS_CONFIG1_RST_SHIFT ((uint8_t)7)
437 
438 /*
439 ** SENS_CONFIG1 - Bit field value definitions
440 */
441 #define FXLS896x_SENS_CONFIG1_RST_RST ((uint8_t)0x80) /* Trigger Reset */
442 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_DISABLED \
443  ((uint8_t)0x00) /* Self-Test function is disabled */
444 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_EN_X ((uint8_t)0x20) /* Self-Test function is enabled for X-axis */
445 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_EN_Y ((uint8_t)0x40) /* Self-Test function is enabled for Y-axis */
446 #define FXLS896x_SENS_CONFIG1_ST_AXIS_SEL_EN_Z ((uint8_t)0x60) /* Self-Test function is enabled for Z-axis */
447 #define FXLS896x_SENS_CONFIG1_ST_POL_POSITIVE ((uint8_t)0x00) /* Proof mass displacement for the selected axis */
448  /* is in the positive direction. */
449 #define FXLS896x_SENS_CONFIG1_ST_POL_NEGATIVE ((uint8_t)0x10) /* Proof mass displacement for the selected axis */
450  /* is in the negative direction. */
451 #define FXLS896x_SENS_CONFIG1_SPI_M_FOUR ((uint8_t)0x00) /* 4-wire interface mode is selected. */
452 #define FXLS896x_SENS_CONFIG1_SPI_M_THREE ((uint8_t)0x08) /* 3-wire interface mode is selected. */
453 #define FXLS896x_SENS_CONFIG1_FSR_2G ((uint8_t)0x00) /* ±2g; 0.98 mg/LSB (1024 LSB/g) nominal */
454  /* sensitivity. */
455 #define FXLS896x_SENS_CONFIG1_FSR_4G ((uint8_t)0x02) /* ±4g; 1.95 mg/LSB (512 LSB/g) nominal */
456  /* sensitivity. */
457 #define FXLS896x_SENS_CONFIG1_FSR_8G ((uint8_t)0x04) /* ±8g; 3.91 mg/LSB (256 LSB/g) nominal */
458  /* sensitivity. */
459 #define FXLS896x_SENS_CONFIG1_FSR_16G ((uint8_t)0x06) /* ±16g; 7.81 mg/LSB (128 LSB/g) nominal */
460  /* sensitivity. */
461 #define FXLS896x_SENS_CONFIG1_ACTIVE_STANDBY ((uint8_t)0x00) /* Standby mode. */
462 #define FXLS896x_SENS_CONFIG1_ACTIVE_ACTIVE ((uint8_t)0x01) /* Active mode. */
463  /*------------------------------*/
464 
465 /*--------------------------------
466 ** Register: SENS_CONFIG2
467 ** Enum: FXLS896x_SENS_CONFIG2
468 ** --
469 ** Offset : 0x16 Configuration register 2.
470 ** ------------------------------*/
471 typedef union
472 {
473  struct
474  {
475  uint8_t f_read : 1; /* Fast-read mode selection. */
476 
477  uint8_t anic_temp : 1; /* Temperature output data auto-increment control. */
478 
479  uint8_t _reserved_ : 1;
480  uint8_t le_be : 1; /* Little/Big-endian output mode selection. */
481 
482  uint8_t sleep_pm : 2; /* SLEEP power mode selection. */
483 
484  uint8_t wake_pm : 2; /* WAKE power mode selection. */
485 
486  } b;
487  uint8_t w;
488 } FXLS896x_SENS_CONFIG2_t;
489 
490 /*
491 ** SENS_CONFIG2 - Bit field mask definitions
492 */
493 #define FXLS896x_SENS_CONFIG2_F_READ_MASK ((uint8_t)0x01)
494 #define FXLS896x_SENS_CONFIG2_F_READ_SHIFT ((uint8_t)0)
495 
496 #define FXLS896x_SENS_CONFIG2_ANIC_TEMP_MASK ((uint8_t)0x02)
497 #define FXLS896x_SENS_CONFIG2_ANIC_TEMP_SHIFT ((uint8_t)1)
498 
499 #define FXLS896x_SENS_CONFIG2_LE_BE_MASK ((uint8_t)0x08)
500 #define FXLS896x_SENS_CONFIG2_LE_BE_SHIFT ((uint8_t)3)
501 
502 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_MASK ((uint8_t)0x30)
503 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_SHIFT ((uint8_t)4)
504 
505 #define FXLS896x_SENS_CONFIG2_WAKE_PM_MASK ((uint8_t)0xC0)
506 #define FXLS896x_SENS_CONFIG2_WAKE_PM_SHIFT ((uint8_t)6)
507 
508 /*
509 ** SENS_CONFIG2 - Bit field value definitions
510 */
511 #define FXLS896x_SENS_CONFIG2_WAKE_PM_LOW_POWER ((uint8_t)0x00) /* Low Power mode is selected. */
512 #define FXLS896x_SENS_CONFIG2_WAKE_PM_HIGH_PERF ((uint8_t)0x40) /* High Performance Mode is selected. */
513 #define FXLS896x_SENS_CONFIG2_WAKE_PM_FLEX_PERF ((uint8_t)0x80) /* Flexible Performance Mode is selected. */
514 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_LOW_POWER ((uint8_t)0x00) /* Low Power mode is selected. */
515 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_HIGH_PERF ((uint8_t)0x10) /* High Performance Mode is selected. */
516 #define FXLS896x_SENS_CONFIG2_SLEEP_PM_FLEX_PERF ((uint8_t)0x20) /* Flexible Performance Mode is selected. */
517 #define FXLS896x_SENS_CONFIG2_LE_BE_LE ((uint8_t)0x00) /* Little-endian output mode is selected. */
518 #define FXLS896x_SENS_CONFIG2_LE_BE_BE ((uint8_t)0x08) /* Big-endian output mode is selected. */
519 #define FXLS896x_SENS_CONFIG2_ANIC_TEMP_DIS ((uint8_t)0x00) /* TEMP_OUT register content is not included in */
520  /* auto-increment address range. */
521 #define FXLS896x_SENS_CONFIG2_ANIC_TEMP_EN ((uint8_t)0x02) /* TEMP_OUT register content is included in */
522  /* auto-increment address range. */
523 #define FXLS896x_SENS_CONFIG2_F_READ_NORMAL ((uint8_t)0x00) /* Normal read mode. */
524 #define FXLS896x_SENS_CONFIG2_F_READ_FAST ((uint8_t)0x01) /* Fast read mode. */
525  /*------------------------------*/
526 
527 /*--------------------------------
528 ** Register: SENS_CONFIG3
529 ** Enum: FXLS896x_SENS_CONFIG3
530 ** --
531 ** Offset : 0x17 Configuration register 3.
532 ** ------------------------------*/
533 typedef union
534 {
535  struct
536  {
537  uint8_t sleep_odr : 4; /* Sleep ODR */
538 
539  uint8_t wake_odr : 4; /* Wake ODR */
540 
541  } b;
542  uint8_t w;
543 } FXLS896x_SENS_CONFIG3_t;
544 
545 /*
546 ** SENS_CONFIG3 - Bit field mask definitions
547 */
548 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_MASK ((uint8_t)0x0F)
549 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_SHIFT ((uint8_t)0)
550 
551 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_MASK ((uint8_t)0xF0)
552 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_SHIFT ((uint8_t)4)
553 
554 /*
555 ** SENS_CONFIG3 - Bit field value definitions
556 */
557 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_3200HZ ((uint8_t)0x00)
558 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_1600HZ ((uint8_t)0x10)
559 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_800HZ ((uint8_t)0x20)
560 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_400HZ ((uint8_t)0x30)
561 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_200HZ ((uint8_t)0x40)
562 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_100HZ ((uint8_t)0x50)
563 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_50HZ ((uint8_t)0x60)
564 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_25HZ ((uint8_t)0x70)
565 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_12_5HZ ((uint8_t)0x80)
566 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_6_25HZ ((uint8_t)0x90) /* 6.25 HZ */
567 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_3_125HZ ((uint8_t)0xa0) /* 3.125 HZ */
568 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_1_563HZ ((uint8_t)0xb0) /* 1.563 HZ */
569 #define FXLS896x_SENS_CONFIG3_WAKE_ODR_0_781HZ ((uint8_t)0xc0) /* 0.781 HZ */
570 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_3200HZ ((uint8_t)0x00)
571 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_1600HZ ((uint8_t)0x01)
572 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_800HZ ((uint8_t)0x02)
573 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_400HZ ((uint8_t)0x03)
574 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_200HZ ((uint8_t)0x04)
575 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_100HZ ((uint8_t)0x05)
576 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_50HZ ((uint8_t)0x06)
577 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_25HZ ((uint8_t)0x07)
578 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_12_5HZ ((uint8_t)0x08)
579 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_6_25HZ ((uint8_t)0x09) /* 6.25 HZ */
580 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_3_125HZ ((uint8_t)0x0a) /* 3.125 HZ */
581 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_1_563HZ ((uint8_t)0x0b) /* 1.563 HZ */
582 #define FXLS896x_SENS_CONFIG3_SLEEP_ODR_0_781HZ ((uint8_t)0x0c) /* 0.781 HZ */
583  /*------------------------------*/
584 
585 /*--------------------------------
586 ** Register: SENS_CONFIG4
587 ** Enum: FXLS896x_SENS_CONFIG4
588 ** --
589 ** Offset : 0x18 Configuration register 4.
590 ** ------------------------------*/
591 typedef union
592 {
593  struct
594  {
595  uint8_t int_pol : 1; /* Interrupt logic polarity on INT1 and INT2 pins. */
596 
597  uint8_t int_pp_od : 1; /* INT1 and INT2 pins output driver selection. */
598 
599  uint8_t int2_func : 1; /* INT2 output / EXT_TRIG input pin selection. */
600 
601  uint8_t drdy_pul : 1; /* Pulse generation option for DRDY event. */
602 
603  uint8_t wk_orient : 1; /* Orientation change event Auto-WAKE/SLEEP transition source enable. */
604 
605  uint8_t wk_sdcd_ot : 1; /* SDCD outside of thresholds event Auto-WAKE/SLEEP transition source enable. */
606 
607  uint8_t wk_sdcd_wt : 1; /* SDCD within thresholds event Auto-WAKE/SLEEP transition source enable. */
608 
609  uint8_t ext_trig_m : 1; /* External trigger function acquisition mode. */
610 
611  } b;
612  uint8_t w;
613 } FXLS896x_SENS_CONFIG4_t;
614 
615 /*
616 ** SENS_CONFIG4 - Bit field mask definitions
617 */
618 #define FXLS896x_SENS_CONFIG4_INT_POL_MASK ((uint8_t)0x01)
619 #define FXLS896x_SENS_CONFIG4_INT_POL_SHIFT ((uint8_t)0)
620 
621 #define FXLS896x_SENS_CONFIG4_INT_PP_OD_MASK ((uint8_t)0x02)
622 #define FXLS896x_SENS_CONFIG4_INT_PP_OD_SHIFT ((uint8_t)1)
623 
624 #define FXLS896x_SENS_CONFIG4_INT2_FUNC_MASK ((uint8_t)0x04)
625 #define FXLS896x_SENS_CONFIG4_INT2_FUNC_SHIFT ((uint8_t)2)
626 
627 #define FXLS896x_SENS_CONFIG4_DRDY_PUL_MASK ((uint8_t)0x08)
628 #define FXLS896x_SENS_CONFIG4_DRDY_PUL_SHIFT ((uint8_t)3)
629 
630 #define FXLS896x_SENS_CONFIG4_WK_ORIENT_MASK ((uint8_t)0x10)
631 #define FXLS896x_SENS_CONFIG4_WK_ORIENT_SHIFT ((uint8_t)4)
632 
633 #define FXLS896x_SENS_CONFIG4_WK_SDCD_OT_MASK ((uint8_t)0x20)
634 #define FXLS896x_SENS_CONFIG4_WK_SDCD_OT_SHIFT ((uint8_t)5)
635 
636 #define FXLS896x_SENS_CONFIG4_WK_SDCD_WT_MASK ((uint8_t)0x40)
637 #define FXLS896x_SENS_CONFIG4_WK_SDCD_WT_SHIFT ((uint8_t)6)
638 
639 #define FXLS896x_SENS_CONFIG4_EXT_TRIG_M_MASK ((uint8_t)0x80)
640 #define FXLS896x_SENS_CONFIG4_EXT_TRIG_M_SHIFT ((uint8_t)7)
641 
642 /*
643 ** SENS_CONFIG4 - Bit field value definitions
644 */
645 #define FXLS896x_SENS_CONFIG4_EXT_TRIG_M_SINGLE ((uint8_t)0x00) /* Each positive going trigger edge causes a */
646  /* single ADC acquisition to be made. */
647 #define FXLS896x_SENS_CONFIG4_EXT_TRIG_M_MULTIPLE ((uint8_t)0x80) /* Each positive going trigger edge causes the */
648 /* number of acquisitions. */
649 #define FXLS896x_SENS_CONFIG4_WK_SDCD_WT_DIS ((uint8_t)0x00) /* SDCD within thresholds event is not used to */
650  /* prevent entry into/trigger. */
651 #define FXLS896x_SENS_CONFIG4_WK_SDCD_WT_EN ((uint8_t)0x40) /* SDCD within thresholds event is used to prevent */
652  /* entry into/trigger an exit from SLEEP mode. */
653 #define FXLS896x_SENS_CONFIG4_WK_SDCD_OT_DIS ((uint8_t)0x00) /* SDCD outside thresholds event is not used to */
654  /* prevent entry into/trigger. */
655 #define FXLS896x_SENS_CONFIG4_WK_SDCD_OT_EN ((uint8_t)0x20) /* SDCD outside thresholds event is used to */
656  /* prevent entry into/trigger an exit from SLEEP */
657  /* mode. */
658 #define FXLS896x_SENS_CONFIG4_WK_ORIENT_DIS ((uint8_t)0x00) /* Orientation change condition is not used as an */
659  /* event to prevent entry into /trigger an exit */
660  /* from SLEEP mode. */
661 #define FXLS896x_SENS_CONFIG4_WK_ORIENT_EN ((uint8_t)0x10) /* Orientation change condition is used as an */
662  /* event to prevent entry into/trigger an exit */
663  /* from SLEEP mode. */
664 #define FXLS896x_SENS_CONFIG4_DRDY_PUL_DIS ((uint8_t)0x00) /* A SRC_DRDY event is output on the INTx pin as */
665  /* an active high or active low signal. */
666 #define FXLS896x_SENS_CONFIG4_DRDY_PUL_EN ((uint8_t)0x08) /* A 32 μs (nominal) duration pulse is output on */
667  /* the configured INTx pin once per ODR cycle. */
668 #define FXLS896x_SENS_CONFIG4_INT2_FUNC_INT2 ((uint8_t)0x00) /* INT2/EXT_TRIG pin is configured for the INT2 */
669  /* output function. */
670 #define FXLS896x_SENS_CONFIG4_INT2_FUNC_EXT_TRIG \
671  ((uint8_t)0x04) /* INT2/EXT_TRIG pin is configured as the EXT_TRIG \ \ \
672  */
673 /* input function. */
674 #define FXLS896x_SENS_CONFIG4_INT_PP_OD_PUSH_PULL ((uint8_t)0x00) /* INTx output pin driver is push-pull type. */
675 #define FXLS896x_SENS_CONFIG4_INT_PP_OD_OPEN_DRAIN \
676  ((uint8_t)0x02) /* INTx output pin driver is */
677  /* open-drain/open-source type. */
678 #define FXLS896x_SENS_CONFIG4_INT_POL_ACT_LOW ((uint8_t)0x00) /* Active low:Interrupt events are signaled with a */
679  /* logical 0 level. */
680 #define FXLS896x_SENS_CONFIG4_INT_POL_ACT_HIGH ((uint8_t)0x01) /* Active high: interrupt events are signaled with */
681  /* a logical 1 level. */
682  /*------------------------------*/
683 
684 /*--------------------------------
685 ** Register: SENS_CONFIG5
686 ** Enum: FXLS896x_SENS_CONFIG5
687 ** --
688 ** Offset : 0x19 Configuration register 5.
689 ** ------------------------------*/
690 typedef union
691 {
692  struct
693  {
694  uint8_t hibernate_en : 1; /* Hibernate mode enable. */
695 
696  uint8_t z_dis : 1; /* Z-axis auto-increment disable. */
697 
698  uint8_t y_dis : 1; /* Y-axis auto-increment disable. */
699 
700  uint8_t x_dis : 1; /* X-axis auto-increment disable. */
701 
702  uint8_t vecm_en : 1; /* Vector Magnitude calculation enable. */
703 
704  } b;
705  uint8_t w;
706 } FXLS896x_SENS_CONFIG5_t;
707 
708 /*
709 ** SENS_CONFIG5 - Bit field mask definitions
710 */
711 #define FXLS896x_SENS_CONFIG5_HIBERNATE_EN_MASK ((uint8_t)0x01)
712 #define FXLS896x_SENS_CONFIG5_HIBERNATE_EN_SHIFT ((uint8_t)0)
713 
714 #define FXLS896x_SENS_CONFIG5_Z_DIS_MASK ((uint8_t)0x02)
715 #define FXLS896x_SENS_CONFIG5_Z_DIS_SHIFT ((uint8_t)1)
716 
717 #define FXLS896x_SENS_CONFIG5_Y_DIS_MASK ((uint8_t)0x04)
718 #define FXLS896x_SENS_CONFIG5_Y_DIS_SHIFT ((uint8_t)2)
719 
720 #define FXLS896x_SENS_CONFIG5_X_DIS_MASK ((uint8_t)0x08)
721 #define FXLS896x_SENS_CONFIG5_X_DIS_SHIFT ((uint8_t)3)
722 
723 #define FXLS896x_SENS_CONFIG5_VECM_EN_MASK ((uint8_t)0x10)
724 #define FXLS896x_SENS_CONFIG5_VECM_EN_SHIFT ((uint8_t)4)
725 
726 /*
727 ** SENS_CONFIG5 - Bit field value definitions
728 */
729 #define FXLS896x_SENS_CONFIG5_VECM_EN_DIS ((uint8_t)0x00) /* 12-bit vector magnitude result is not */
730  /* calculated on every ODR cycle. */
731 #define FXLS896x_SENS_CONFIG5_VECM_EN_EN ((uint8_t)0x10) /* 12-bit vector magnitude result is calculated on */
732  /* every ODR cycle. */
733 #define FXLS896x_SENS_CONFIG5_X_DIS_EN ((uint8_t)0x00) /* X-axis measurement is included in the */
734  /* auto-increment address range. */
735 #define FXLS896x_SENS_CONFIG5_X_DIS_DIS ((uint8_t)0x08) /* X-axis measurement is excluded from the */
736  /* auto-increment address range. */
737 #define FXLS896x_SENS_CONFIG5_Y_DIS_EN ((uint8_t)0x00) /* Y-axis measurement is included in the */
738  /* auto-increment address range. */
739 #define FXLS896x_SENS_CONFIG5_Y_DIS_DIS ((uint8_t)0x04) /* Y-axis measurement is excluded from the */
740  /* auto-increment address range. */
741 #define FXLS896x_SENS_CONFIG5_Z_DIS_EN ((uint8_t)0x00) /* Z-axis measurement is included in the */
742  /* auto-increment address range. */
743 #define FXLS896x_SENS_CONFIG5_Z_DIS_DIS ((uint8_t)0x02) /* Z-axis measurement is excluded from the */
744  /* auto-increment address range. */
745 #define FXLS896x_SENS_CONFIG5_HIBERNATE_EN_DIS ((uint8_t)0x00) /* Hibernate mode not enabled. */
746 #define FXLS896x_SENS_CONFIG5_HIBERNATE_EN_EN ((uint8_t)0x01) /* Commands device to enter Hibernate mode. */
747  /*------------------------------*/
748 
749 /*--------------------------------
750 ** Register: WAKE_IDLE_LSB
751 ** Enum: FXLS896x_WAKE_IDLE_LSB
752 ** --
753 ** Offset : 0x1A LSB of 12-bit user programmable wake mode idle.
754 ** ------------------------------*/
755 typedef uint8_t FXLS896x_WAKE_IDLE_LSB_t;
756 
757 /*--------------------------------
758 ** Register: WAKE_IDLE_MSB
759 ** Enum: FXLS896x_WAKE_IDLE_MSB
760 ** --
761 ** Offset : 0x1B MSB of 12-bit user programmable wake mode idle.
762 ** ------------------------------*/
763 typedef uint8_t FXLS896x_WAKE_IDLE_MSB_t;
764 
765 /*--------------------------------
766 ** Register: SLEEP_IDLE_LSB
767 ** Enum: FXLS896x_SLEEP_IDLE_LSB
768 ** --
769 ** Offset : 0x1C LSB of 12-bit user programmable sleep mode idle.
770 ** ------------------------------*/
771 typedef uint8_t FXLS896x_SLEEP_IDLE_LSB_t;
772 
773 /*--------------------------------
774 ** Register: SLEEP_IDLE_MSB
775 ** Enum: FXLS896x_SLEEP_IDLE_MSB
776 ** --
777 ** Offset : 0x1D MSB of 12-bit user programmable sleep mode idle.
778 ** ------------------------------*/
779 typedef uint8_t FXLS896x_SLEEP_IDLE_MSB_t;
780 
781 /*--------------------------------
782 ** Register: ASLP_COUNT_LSB
783 ** Enum: FXLS896x_ASLP_COUNT_LSB
784 ** --
785 ** Offset : 0x1E LSB of inactivity time-out count value used for transitioning into Auto-SLEEP mode.
786 ** ------------------------------*/
787 typedef uint8_t FXLS896x_ASLP_COUNT_LSB_t;
788 
789 /*--------------------------------
790 ** Register: ASLP_COUNT_MSB
791 ** Enum: FXLS896x_ASLP_COUNT_MSB
792 ** --
793 ** Offset : 0x1F MSB of inactivity time-out count value used for transitioning into Auto-SLEEP mode.
794 ** ------------------------------*/
795 typedef uint8_t FXLS896x_ASLP_COUNT_MSB_t;
796 
797 /*--------------------------------
798 ** Register: INT_EN
799 ** Enum: FXLS896x_INT_EN
800 ** --
801 ** Offset : 0x20 Interrupt output enable register.
802 ** ------------------------------*/
803 typedef union
804 {
805  struct
806  {
807  uint8_t wake_out_en : 1; /* WAKE power state output enable. */
808 
809  uint8_t boot_dis : 1; /* Boot interrupt output disable. */
810 
811  uint8_t aslp_en : 1; /* Auto-WAKE/SLEEP interrupt output enable. */
812 
813  uint8_t orient_en : 1; /* Orientation interrupt output enable. */
814 
815  uint8_t sdcd_wt_en : 1; /* SDCD within thresholds interrupt output enable. */
816 
817  uint8_t sdcd_ot_en : 1; /* SDCD outside of thresholds interrupt output enable. */
818 
819  uint8_t buf_en : 1; /* Output data buffer interrupt output enable */
820  uint8_t drdy_en : 1; /* Data Ready interrupt output enable. */
821 
822  } b;
823  uint8_t w;
824 } FXLS896x_INT_EN_t;
825 
826 /*
827 ** INT_EN - Bit field mask definitions
828 */
829 #define FXLS896x_INT_EN_WAKE_OUT_EN_MASK ((uint8_t)0x01)
830 #define FXLS896x_INT_EN_WAKE_OUT_EN_SHIFT ((uint8_t)0)
831 
832 #define FXLS896x_INT_EN_BOOT_DIS_MASK ((uint8_t)0x02)
833 #define FXLS896x_INT_EN_BOOT_DIS_SHIFT ((uint8_t)1)
834 
835 #define FXLS896x_INT_EN_ASLP_EN_MASK ((uint8_t)0x04)
836 #define FXLS896x_INT_EN_ASLP_EN_SHIFT ((uint8_t)2)
837 
838 #define FXLS896x_INT_EN_ORIENT_EN_MASK ((uint8_t)0x08)
839 #define FXLS896x_INT_EN_ORIENT_EN_SHIFT ((uint8_t)3)
840 
841 #define FXLS896x_INT_EN_SDCD_WT_EN_MASK ((uint8_t)0x10)
842 #define FXLS896x_INT_EN_SDCD_WT_EN_SHIFT ((uint8_t)4)
843 
844 #define FXLS896x_INT_EN_SDCD_OT_EN_MASK ((uint8_t)0x20)
845 #define FXLS896x_INT_EN_SDCD_OT_EN_SHIFT ((uint8_t)5)
846 
847 #define FXLS896x_INT_EN_BUF_EN_MASK ((uint8_t)0x40)
848 #define FXLS896x_INT_EN_BUF_EN_SHIFT ((uint8_t)6)
849 
850 #define FXLS896x_INT_EN_DRDY_EN_MASK ((uint8_t)0x80)
851 #define FXLS896x_INT_EN_DRDY_EN_SHIFT ((uint8_t)7)
852 
853 /*
854 ** INT_EN - Bit field value definitions
855 */
856 #define FXLS896x_INT_EN_DRDY_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
857 #define FXLS896x_INT_EN_DRDY_EN_EN ((uint8_t)0x80) /* Interrupt enabled. */
858 #define FXLS896x_INT_EN_BUF_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
859 #define FXLS896x_INT_EN_BUF_EN_EN ((uint8_t)0x40) /* Interrupt enabled. */
860 #define FXLS896x_INT_EN_SDCD_OT_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
861 #define FXLS896x_INT_EN_SDCD_OT_EN_EN ((uint8_t)0x20) /* Interrupt is routed to either the INT1 or INT2. */
862 #define FXLS896x_INT_EN_SDCD_WT_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
863 #define FXLS896x_INT_EN_SDCD_WT_EN_EN ((uint8_t)0x10) /* Interrupt is routed to either the INT1 or INT2. */
864 #define FXLS896x_INT_EN_ORIENT_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
865 #define FXLS896x_INT_EN_ORIENT_EN_EN ((uint8_t)0x08) /* Interrupt is enabled and signaled on either the INT1 */
866  /* or INT2. */
867 #define FXLS896x_INT_EN_ASLP_EN_DIS ((uint8_t)0x00) /* Interrupt is disabled. */
868 #define FXLS896x_INT_EN_ASLP_EN_EN ((uint8_t)0x04) /* Interrupt is enabled and signaled on either the INT1 */
869  /* or INT2. */
870 #define FXLS896x_INT_EN_BOOT_DIS_EN ((uint8_t)0x00) /* Boot interrupt is enabled and routed to either the */
871  /* INT1 or INT2. */
872 #define FXLS896x_INT_EN_BOOT_DIS_DIS ((uint8_t)0x02) /* Interrupt is disabled and not routed to the INTx */
873  /* output pins. */
874 #define FXLS896x_INT_EN_WAKE_OUT_EN_DIS ((uint8_t)0x00) /* The device does not signal the WAKE operating mode on */
875  /* the INTx output pin. */
876 #define FXLS896x_INT_EN_WAKE_OUT_EN_EN ((uint8_t)0x01) /* The device signals that it is currently in WAKE mode */
877  /* via the INT1 or INT2 pin. */
878  /*------------------------------*/
879 
880 /*--------------------------------
881 ** Register: INT_PIN_SEL
882 ** Enum: FXLS896x_INT_PIN_SEL
883 ** --
884 ** Offset : 0x21 Interrupt output pin routing register, INT1 or INT2.
885 ** ------------------------------*/
886 typedef union
887 {
888  struct
889  {
890  uint8_t wk_out_int2 : 1; /* WAKE power state interrupt routing. */
891 
892  uint8_t boot_int2 : 1; /* BOOT event interrupt routing. */
893 
894  uint8_t aslp_int2 : 1; /* Auto-WAKE/SLEEP event interrupt routing. */
895 
896  uint8_t orient_int2 : 1; /* ORIENT event interrupt routing. */
897 
898  uint8_t sdcd_wt_int2 : 1; /* SDCD within thresholds event interrupt routing. */
899 
900  uint8_t sdcd_ot_int2 : 1; /* SDCD outside of thresholds event interrupt routing. */
901 
902  uint8_t buf_int2 : 1; /* Output buffer interrupt routing. */
903 
904  uint8_t drdy_int2 : 1; /* Data Ready interrupt routing. */
905 
906  } b;
907  uint8_t w;
908 } FXLS896x_INT_PIN_SEL_t;
909 
910 /*
911 ** INT_PIN_SEL - Bit field mask definitions
912 */
913 #define FXLS896x_INT_PIN_SEL_WK_OUT_INT2_MASK ((uint8_t)0x01)
914 #define FXLS896x_INT_PIN_SEL_WK_OUT_INT2_SHIFT ((uint8_t)0)
915 
916 #define FXLS896x_INT_PIN_SEL_BOOT_INT2_MASK ((uint8_t)0x02)
917 #define FXLS896x_INT_PIN_SEL_BOOT_INT2_SHIFT ((uint8_t)1)
918 
919 #define FXLS896x_INT_PIN_SEL_ASLP_INT2_MASK ((uint8_t)0x04)
920 #define FXLS896x_INT_PIN_SEL_ASLP_INT2_SHIFT ((uint8_t)2)
921 
922 #define FXLS896x_INT_PIN_SEL_ORIENT_INT2_MASK ((uint8_t)0x08)
923 #define FXLS896x_INT_PIN_SEL_ORIENT_INT2_SHIFT ((uint8_t)3)
924 
925 #define FXLS896x_INT_PIN_SEL_SDCD_WT_INT2_MASK ((uint8_t)0x10)
926 #define FXLS896x_INT_PIN_SEL_SDCD_WT_INT2_SHIFT ((uint8_t)4)
927 
928 #define FXLS896x_INT_PIN_SEL_SDCD_OT_INT2_MASK ((uint8_t)0x20)
929 #define FXLS896x_INT_PIN_SEL_SDCD_OT_INT2_SHIFT ((uint8_t)5)
930 
931 #define FXLS896x_INT_PIN_SEL_BUF_INT2_MASK ((uint8_t)0x40)
932 #define FXLS896x_INT_PIN_SEL_BUF_INT2_SHIFT ((uint8_t)6)
933 
934 #define FXLS896x_INT_PIN_SEL_DRDY_INT2_MASK ((uint8_t)0x80)
935 #define FXLS896x_INT_PIN_SEL_DRDY_INT2_SHIFT ((uint8_t)7)
936 
937 /*
938 ** INT_PIN_SEL - Bit field value definitions
939 */
940 #define FXLS896x_INT_PIN_SEL_DRDY_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
941  /* enabled. */
942 #define FXLS896x_INT_PIN_SEL_DRDY_INT2_EN ((uint8_t)0x80) /* Interrupt signal is routed to INT2 pin if it is */
943  /* enabled. */
944 #define FXLS896x_INT_PIN_SEL_BUF_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
945  /* enabled. */
946 #define FXLS896x_INT_PIN_SEL_BUF_INT2_EN ((uint8_t)0x40) /* Interrupt signal is routed to INT2 pin if it is */
947  /* enabled. */
948 #define FXLS896x_INT_PIN_SEL_SDCD_OT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
949  /* enabled. */
950 #define FXLS896x_INT_PIN_SEL_SDCD_OT_INT2_EN ((uint8_t)0x20) /* Interrupt signal is routed to INT2 pin if it is */
951  /* enabled. */
952 #define FXLS896x_INT_PIN_SEL_SDCD_WT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
953  /* enabled. */
954 #define FXLS896x_INT_PIN_SEL_SDCD_WT_INT2_EN ((uint8_t)0x10) /* Interrupt signal is routed to INT2 pin if it is */
955  /* enabled. */
956 #define FXLS896x_INT_PIN_SEL_ORIENT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
957  /* enabled. */
958 #define FXLS896x_INT_PIN_SEL_ORIENT_INT2_EN ((uint8_t)0x08) /* Interrupt signal is routed to INT2 pin if it is */
959  /* enabled. */
960 #define FXLS896x_INT_PIN_SEL_ASLP_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
961  /* enabled. */
962 #define FXLS896x_INT_PIN_SEL_ASLP_INT2_EN ((uint8_t)0x04) /* Interrupt signal is routed to INT2 pin if it is */
963  /* enabled. */
964 #define FXLS896x_INT_PIN_SEL_BOOT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
965  /* enabled. */
966 #define FXLS896x_INT_PIN_SEL_BOOT_INT2_EN ((uint8_t)0x02) /* Interrupt signal is routed to INT2 pin if it is */
967  /* enabled. */
968 #define FXLS896x_INT_PIN_SEL_WK_OUT_INT2_DIS ((uint8_t)0x00) /* Interrupt signal is routed to INT1 pin if it is */
969  /* enabled. */
970 #define FXLS896x_INT_PIN_SEL_WK_OUT_INT2_EN ((uint8_t)0x01) /* Interrupt signal is routed to INT2 pin if it is */
971  /* enabled. */
972  /*------------------------------*/
973 
974 /*--------------------------------
975 ** Register: OFF_X
976 ** Enum: FXLS896x_OFF_X
977 ** --
978 ** Offset : 0x22 X-Acceleration zero-g offset.
979 ** ------------------------------*/
980 typedef uint8_t FXLS896x_OFF_X_t;
981 
982 /*--------------------------------
983 ** Register: OFF_Y
984 ** Enum: FXLS896x_OFF_Y
985 ** --
986 ** Offset : 0x23 Y-Acceleration zero-g offset.
987 ** ------------------------------*/
988 typedef uint8_t FXLS896x_OFF_Y_t;
989 
990 /*--------------------------------
991 ** Register: OFF_Z
992 ** Enum: FXLS896x_OFF_Z
993 ** --
994 ** Offset : 0x24 Z-Acceleration zero-g offset.
995 ** ------------------------------*/
996 typedef uint8_t FXLS896x_OFF_Z_t;
997 
998 
999 
1000 /*--------------------------------
1001 ** Register: BUF_CONFIG1
1002 ** Enum: FXLS896x_BUF_CONFIG1
1003 ** --
1004 ** Offset : 0x26 Buf configuration1.
1005 ** ------------------------------*/
1006 typedef union {
1007  struct {
1008  uint8_t trg_orient : 1; /* Orientation change event trigger enable */
1009 
1010  uint8_t _reserved_ : 1;
1011  uint8_t trg_sdcd_ot : 1; /* SDCD outside-of-thresholds event buffer trigger enable */
1012 
1013  uint8_t trg_sdcd_wt : 1; /* SDCD within-thresholds event trigger enable */
1014 
1015  uint8_t buf_gate : 1; /* Output data buffer gate enable */
1016 
1017  uint8_t buf_mode : 2; /* Buffer data collection mode */
1018 
1019  uint8_t buf_type : 1; /* Buffer data read out order */
1020 
1021  } b;
1022  uint8_t w;
1023 } FXLS896x_BUF_CONFIG1_t;
1024 
1025 
1026 /*
1027 ** BUF_CONFIG1 - Bit field mask definitions
1028 */
1029 #define FXLS896x_BUF_CONFIG1_TRG_ORIENT_MASK ((uint8_t) 0x01)
1030 #define FXLS896x_BUF_CONFIG1_TRG_ORIENT_SHIFT ((uint8_t) 0)
1031 
1032 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_OT_MASK ((uint8_t) 0x04)
1033 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_OT_SHIFT ((uint8_t) 2)
1034 
1035 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_WT_MASK ((uint8_t) 0x08)
1036 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_WT_SHIFT ((uint8_t) 3)
1037 
1038 #define FXLS896x_BUF_CONFIG1_BUF_GATE_MASK ((uint8_t) 0x10)
1039 #define FXLS896x_BUF_CONFIG1_BUF_GATE_SHIFT ((uint8_t) 4)
1040 
1041 #define FXLS896x_BUF_CONFIG1_BUF_MODE_MASK ((uint8_t) 0x60)
1042 #define FXLS896x_BUF_CONFIG1_BUF_MODE_SHIFT ((uint8_t) 5)
1043 
1044 #define FXLS896x_BUF_CONFIG1_BUF_TYPE_MASK ((uint8_t) 0x80)
1045 #define FXLS896x_BUF_CONFIG1_BUF_TYPE_SHIFT ((uint8_t) 7)
1046 
1047 
1048 /*
1049 ** BUF_CONFIG1 - Bit field value definitions
1050 */
1051 #define FXLS896x_BUF_CONFIG1_BUF_TYPE_FIFO ((uint8_t) 0x00) /* In FIFO mode */
1052 #define FXLS896x_BUF_CONFIG1_BUF_TYPE_FILO ((uint8_t) 0x80) /* First In Last Out (FILO) */
1053 #define FXLS896x_BUF_CONFIG1_BUF_MODE_DIS ((uint8_t) 0x00) /* Buffer is disabled */
1054 #define FXLS896x_BUF_CONFIG1_BUF_MODE_STREAM_MODE ((uint8_t) 0x20) /* Stream Mode */
1055 #define FXLS896x_BUF_CONFIG1_BUF_MODE_STOP_MODE ((uint8_t) 0x40) /* Stop mode */
1056 #define FXLS896x_BUF_CONFIG1_BUF_MODE_TRIGGER_MODE ((uint8_t) 0x60) /* Trigger Mode */
1057 #define FXLS896x_BUF_CONFIG1_BUF_GATE_BY_PASSED ((uint8_t) 0x00) /* Buffer gate is bypassed. */
1058 #define FXLS896x_BUF_CONFIG1_BUF_GATE_ENABLED ((uint8_t) 0x10) /* The Buffer gate input is enabled. */
1059 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_WT_DIS ((uint8_t) 0x00) /* Trigger source is disabled. */
1060 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_WT_EN ((uint8_t) 0x08) /* Trigger source is enabled. */
1061 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_OT_DIS ((uint8_t) 0x00) /* Trigger source is disabled. */
1062 #define FXLS896x_BUF_CONFIG1_TRG_SDCD_OT_EN ((uint8_t) 0x04) /* Trigger source is enabled. */
1063 #define FXLS896x_BUF_CONFIG1_TRG_ORIENT_DIS ((uint8_t) 0x00) /* Trigger source is disabled. */
1064 #define FXLS896x_BUF_CONFIG1_TRG_ORIENT_EN ((uint8_t) 0x01) /* Trigger source is enabled. */
1065 /*------------------------------*/
1066 
1067 
1068 
1069 /*--------------------------------
1070 ** Register: BUF_CONFIG2
1071 ** Enum: FXLS896x_BUF_CONFIG2
1072 ** --
1073 ** Offset : 0x27 buf configuration2.
1074 ** ------------------------------*/
1075 typedef union {
1076  struct {
1077  uint8_t buf_wmrk : 6; /* Buffer sample count watermark */
1078 
1079  uint8_t wake_src_buf : 1; /* Buffer WAKE-to-SLEEP transition source enable */
1080 
1081  uint8_t buf_flush : 1; /* Buffer flush enable */
1082 
1083  } b;
1084  uint8_t w;
1085 } FXLS896x_BUF_CONFIG2_t;
1086 
1087 
1088 /*
1089 ** BUF_CONFIG2 - Bit field mask definitions
1090 */
1091 #define FXLS896x_BUF_CONFIG2_BUF_WMRK_MASK ((uint8_t) 0x3F)
1092 #define FXLS896x_BUF_CONFIG2_BUF_WMRK_SHIFT ((uint8_t) 0)
1093 
1094 #define FXLS896x_BUF_CONFIG2_WAKE_SRC_BUF_MASK ((uint8_t) 0x40)
1095 #define FXLS896x_BUF_CONFIG2_WAKE_SRC_BUF_SHIFT ((uint8_t) 6)
1096 
1097 #define FXLS896x_BUF_CONFIG2_BUF_FLUSH_MASK ((uint8_t) 0x80)
1098 #define FXLS896x_BUF_CONFIG2_BUF_FLUSH_SHIFT ((uint8_t) 7)
1099 
1100 
1101 /*
1102 ** BUF_CONFIG2 - Bit field value definitions
1103 */
1104 #define FXLS896x_BUF_CONFIG2_BUF_FLUSH_COMPLETED ((uint8_t) 0x00) /* Buffer flush operation not pending/completed. */
1105 #define FXLS896x_BUF_CONFIG2_BUF_FLUSH_EN ((uint8_t) 0x80) /* Buffer flush enable. */
1106 #define FXLS896x_BUF_CONFIG2_WAKE_SRC_BUF_IGNORED ((uint8_t) 0x00) /* BUF_WMRK and BUF_OVF and event flags are ignored */
1107  /* by the auto-WAKE/SLEEP function. */
1108 #define FXLS896x_BUF_CONFIG2_WAKE_SRC_BUF_EN ((uint8_t) 0x40) /* BUF_WMRK and BUF_OVF event flags are used by the */
1109  /* auto-WAKE/SLEEP function */
1110 
1111 
1112 /*--------------------------------
1113 ** Register: ORIENT_STATUS
1114 ** Enum: FXLS896x_ORIENT_STATUS
1115 ** --
1116 ** Offset : 0x28 Orientation event status.
1117 ** ------------------------------*/
1118 typedef union
1119 {
1120  struct
1121  {
1122  uint8_t bafro : 1; /* Back or front orientation. */
1123 
1124  uint8_t lapo : 2; /* Landscape/Portrait orientation. */
1125 
1126  uint8_t _reserved_ : 3;
1127  uint8_t lo : 1; /* Z-tilt angle lockout. */
1128 
1129  uint8_t new_orient : 1; /* Orientation status change flag. */
1130 
1131  } b;
1132  uint8_t w;
1133 } FXLS896x_ORIENT_STATUS_t;
1134 
1135 /*
1136 ** ORIENT_STATUS - Bit field mask definitions
1137 */
1138 #define FXLS896x_ORIENT_STATUS_BAFRO_MASK ((uint8_t)0x01)
1139 #define FXLS896x_ORIENT_STATUS_BAFRO_SHIFT ((uint8_t)0)
1140 
1141 #define FXLS896x_ORIENT_STATUS_LAPO_MASK ((uint8_t)0x06)
1142 #define FXLS896x_ORIENT_STATUS_LAPO_SHIFT ((uint8_t)1)
1143 
1144 #define FXLS896x_ORIENT_STATUS_LO_MASK ((uint8_t)0x40)
1145 #define FXLS896x_ORIENT_STATUS_LO_SHIFT ((uint8_t)6)
1146 
1147 #define FXLS896x_ORIENT_STATUS_NEW_ORIENT_MASK ((uint8_t)0x80)
1148 #define FXLS896x_ORIENT_STATUS_NEW_ORIENT_SHIFT ((uint8_t)7)
1149 
1150 /*
1151 ** ORIENT_STATUS - Bit field value definitions
1152 */
1153 #define FXLS896x_ORIENT_STATUS_NEW_ORIENT_NO_CHANGE \
1154  ((uint8_t)0x00) /* No change in orientation detected. */
1155 #define FXLS896x_ORIENT_STATUS_NEW_ORIENT_CHANGED ((uint8_t)0x80) /* BAFRO and/or LAPO and/or Z-tilt lockout value */
1156 /* has changed. */
1157 #define FXLS896x_ORIENT_STATUS_LO_NOT_DETECTED ((uint8_t)0x00) /* Lockout condition has not been detected. */
1158 #define FXLS896x_ORIENT_STATUS_LO_DETECTED ((uint8_t)0x40) /* Z-tilt lockout trip angle has been exceeded. */
1159  /* Lockout condition has been detected. */
1160 #define FXLS896x_ORIENT_STATUS_LAPO_UP ((uint8_t)0x00) /* Portrait up. */
1161 #define FXLS896x_ORIENT_STATUS_LAPO_DOWN ((uint8_t)0x02) /* Portrait down. */
1162 #define FXLS896x_ORIENT_STATUS_LAPO_RIGHT ((uint8_t)0x04) /* Landscape right. */
1163 #define FXLS896x_ORIENT_STATUS_LAPO_LEFT ((uint8_t)0x06) /* Landscape left. */
1164 #define FXLS896x_ORIENT_STATUS_BAFRO_FRONT ((uint8_t)0x00) /* The device is in the front-facing orientation. */
1165 #define FXLS896x_ORIENT_STATUS_BAFRO_BACK ((uint8_t)0x01) /* The device is in the back-facing orientation. */
1166  /*------------------------------*/
1167 
1168 /*--------------------------------
1169 ** Register: ORIENT_CONFIG
1170 ** Enum: FXLS896x_ORIENT_CONFIG
1171 ** --
1172 ** Offset : 0x29 Orientation detection function configuration.
1173 ** ------------------------------*/
1174 typedef union
1175 {
1176  struct
1177  {
1178  uint8_t _reserved_ : 6;
1179  uint8_t orient_enable : 1; /* Orientation detection function enable. */
1180 
1181  uint8_t orient_dbcntm : 1; /* Orientation debounce counter mode selection. */
1182 
1183  } b;
1184  uint8_t w;
1185 } FXLS896x_ORIENT_CONFIG_t;
1186 
1187 /*
1188 ** ORIENT_CONFIG - Bit field mask definitions
1189 */
1190 #define FXLS896x_ORIENT_CONFIG_ORIENT_ENABLE_MASK ((uint8_t)0x40)
1191 #define FXLS896x_ORIENT_CONFIG_ORIENT_ENABLE_SHIFT ((uint8_t)6)
1192 
1193 #define FXLS896x_ORIENT_CONFIG_ORIENT_DBCNTM_MASK ((uint8_t)0x80)
1194 #define FXLS896x_ORIENT_CONFIG_ORIENT_DBCNTM_SHIFT ((uint8_t)7)
1195 
1196 /*
1197 ** ORIENT_CONFIG - Bit field value definitions
1198 */
1199 #define FXLS896x_ORIENT_CONFIG_ORIENT_DBCNTM_DEC ((uint8_t)0x00) /* Orientation debounce counter is decremented */
1200  /* whenever the current orientation is different */
1201  /* thanthe previous one. */
1202 #define FXLS896x_ORIENT_CONFIG_ORIENT_DBCNTM_CLR ((uint8_t)0x80) /* Orientation debounce counter is cleared */
1203  /* whenever the current orientation is different */
1204  /* than the previous one. */
1205 #define FXLS896x_ORIENT_CONFIG_ORIENT_ENABLE_DIS ((uint8_t)0x00) /* Orientation detection function is disabled. */
1206 #define FXLS896x_ORIENT_CONFIG_ORIENT_ENABLE_EN ((uint8_t)0x40) /* Orientation detection function is enabled. */
1207  /*------------------------------*/
1208 
1209 /*--------------------------------
1210 ** Register: ORIENT_DBCOUNT
1211 ** Enum: FXLS896x_ORIENT_DBCOUNT
1212 ** --
1213 ** Offset : 0x2A Orientation detection debounce counter.
1214 ** ------------------------------*/
1215 typedef uint8_t FXLS896x_ORIENT_DBCOUNT_t;
1216 
1217 /*--------------------------------
1218 ** Register: ORIENT_BF_ZCOMP
1219 ** Enum: FXLS896x_ORIENT_BF_ZCOMP
1220 ** --
1221 ** Offset : 0x2B Orientation back/front and Z-tilt angle compensation register.
1222 ** ------------------------------*/
1223 typedef union
1224 {
1225  struct
1226  {
1227  uint8_t orient_zlock : 3; /* Z-lock out angle threshold. */
1228 
1229  uint8_t _reserved_ : 3;
1230  uint8_t orient_bkfr : 2; /* Back-Up / Front-Up trip angle threshold. */
1231 
1232  } b;
1233  uint8_t w;
1234 } FXLS896x_ORIENT_BF_ZCOMP_t;
1235 
1236 /*
1237 ** ORIENT_BF_ZCOMP - Bit field mask definitions
1238 */
1239 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_MASK ((uint8_t)0x07)
1240 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_SHIFT ((uint8_t)0)
1241 
1242 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_MASK ((uint8_t)0xC0)
1243 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_SHIFT ((uint8_t)6)
1244 
1245 /*
1246 ** ORIENT_BF_ZCOMP - Bit field value definitions
1247 */
1248 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_80_280_FB_100_260 \
1249  ((uint8_t)0x00) /* Back to front Z < 80° or Z > 280° */
1250  /* and Front to back Z > 100° and Z */
1251  /* < 260° */
1252 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_75_285_FB_105_255 \
1253  ((uint8_t)0x40) /* Back to front Z < 75° or Z > 285° */
1254  /* and Front to back Z > 105° and Z */
1255  /* < 255° */
1256 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_70_290_FB_110_250 \
1257  ((uint8_t)0x80) /* Back to front Z < 70° or Z > 290° */
1258  /* and Front to back Z > 110° and Z */
1259  /* < 250° */
1260 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_BKFR_BF_65_295_FB_115_245 \
1261  ((uint8_t)0xc0) /* Back to front Z < 65° or Z > 295° */
1262  /* and Front to back Z > 115° and Z */
1263  /* < 250° */
1264 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_13_6 ((uint8_t)0x00) /* Resultant angle 13.6 */
1265 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_17_1 ((uint8_t)0x01) /* Resultant angle 17.1 */
1266 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_20_7 ((uint8_t)0x02) /* Resultant angle 20.7 */
1267 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_24_4 ((uint8_t)0x03) /* Resultant angle 24.4 */
1268 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_28_1 ((uint8_t)0x04) /* Resultant angle 28.1 */
1269 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_32_0 ((uint8_t)0x05) /* Resultant angle 32.0 */
1270 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_36_1 ((uint8_t)0x06) /* Resultant angle 36.1 */
1271 #define FXLS896x_ORIENT_BF_ZCOMP_ORIENT_ZLOCK_40_4 ((uint8_t)0x07) /* Resultant angle 40.4 */
1272  /*------------------------------*/
1273 
1274 /*--------------------------------
1275 ** Register: ORIENT_THS_REG
1276 ** Enum: FXLS896x_ORIENT_THS_REG
1277 ** --
1278 ** Offset : 0x2C Orientation detection state change threshold angle (Portrait/Landscape) and hysteresis settings.
1279 ** ------------------------------*/
1280 typedef union
1281 {
1282  struct
1283  {
1284  uint8_t hys : 3; /* ORIENT_HYS[2:0] */
1285 
1286  uint8_t orient_ths : 5; /* ORIENT_THS[4:0] value */
1287 
1288  } b;
1289  uint8_t w;
1290 } FXLS896x_ORIENT_THS_REG_t;
1291 
1292 /*
1293 ** ORIENT_THS_REG - Bit field mask definitions
1294 */
1295 #define FXLS896x_ORIENT_THS_REG_HYS_MASK ((uint8_t)0x07)
1296 #define FXLS896x_ORIENT_THS_REG_HYS_SHIFT ((uint8_t)0)
1297 
1298 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_MASK ((uint8_t)0xF8)
1299 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_SHIFT ((uint8_t)3)
1300 
1301 /*
1302 ** ORIENT_THS_REG - Bit field value definitions
1303 */
1304 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_0_0 ((uint8_t)0x00) /* 0.0° */
1305 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_1_8 ((uint8_t)0x08) /* 1.8° */
1306 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_3_8 ((uint8_t)0x10) /* 3.8° */
1307 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_5_9 ((uint8_t)0x18) /* 5.9° */
1308 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_8_1 ((uint8_t)0x20) /* 8.1° */
1309 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_10_5 ((uint8_t)0x28) /* 10.5° */
1310 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_13_0 ((uint8_t)0x30) /* 13.0° */
1311 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_15_6 ((uint8_t)0x38) /* 15.6° */
1312 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_18_4 ((uint8_t)0x40) /* 18.4° */
1313 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_21_4 ((uint8_t)0x48) /* 21.4° */
1314 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_24_4 ((uint8_t)0x50) /* 24.4° */
1315 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_27_6 ((uint8_t)0x58) /* 27.6° */
1316 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_31_0 ((uint8_t)0x60) /* 31.0° */
1317 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_34_4 ((uint8_t)0x68) /* 34.4° */
1318 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_37_9 ((uint8_t)0x70) /* 37.9° */
1319 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_41_4 ((uint8_t)0x78) /* 41.4° */
1320 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_45_0 ((uint8_t)0x80) /* 45.0° */
1321 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_48_6 ((uint8_t)0x88) /* 48.6° */
1322 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_52_1 ((uint8_t)0x90) /* 52.1° */
1323 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_55_6 ((uint8_t)0x98) /* 55.6° */
1324 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_59_0 ((uint8_t)0xa0) /* 59.0° */
1325 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_62_4 ((uint8_t)0xa8) /* 62.4° */
1326 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_65_6 ((uint8_t)0xb0) /* 65.6° */
1327 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_68_6 ((uint8_t)0xb8) /* 68.6° */
1328 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_71_6 ((uint8_t)0xc0) /* 71.6° */
1329 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_74_4 ((uint8_t)0xc8) /* 74.4° */
1330 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_77_0 ((uint8_t)0xd0) /* 77.0° */
1331 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_79_5 ((uint8_t)0xd8) /* 79.5° */
1332 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_81_9 ((uint8_t)0xe0) /* 81.9° */
1333 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_84_1 ((uint8_t)0xe8) /* 84.1° */
1334 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_86_2 ((uint8_t)0xf0) /* 86.2° */
1335 #define FXLS896x_ORIENT_THS_REG_ORIENT_THS_88_2 ((uint8_t)0xf8) /* 88.2° */
1336 #define FXLS896x_ORIENT_THS_REG_HYS_45_45 ((uint8_t)0x00) /* L-to-P 45° P-to-L 45° */
1337 #define FXLS896x_ORIENT_THS_REG_HYS_49_41 ((uint8_t)0x01) /* L-to-P 49° P-to-L 41° */
1338 #define FXLS896x_ORIENT_THS_REG_HYS_52_38 ((uint8_t)0x02) /* L-to-P 52° P-to-L 38° */
1339 #define FXLS896x_ORIENT_THS_REG_HYS_56_34 ((uint8_t)0x03) /* L-to-P 56° P-to-L 34° */
1340 #define FXLS896x_ORIENT_THS_REG_HYS_59_31 ((uint8_t)0x04) /* L-to-P 59° P-to-L 31° */
1341 #define FXLS896x_ORIENT_THS_REG_HYS_62_28 ((uint8_t)0x05) /* L-to-P 62° P-to-L 28° */
1342 #define FXLS896x_ORIENT_THS_REG_HYS_66_24 ((uint8_t)0x06) /* L-to-P 66° P-to-L 24° */
1343 #define FXLS896x_ORIENT_THS_REG_HYS_69_21 ((uint8_t)0x07) /* L-to-P 69° P-to-L 21° */
1344  /*------------------------------*/
1345 
1346 /*--------------------------------
1347 ** Register: SDCD_INT_SRC1
1348 ** Enum: FXLS896x_SDCD_INT_SRC1
1349 ** --
1350 ** Offset : 0x2D Sensor data change detection function 1.
1351 ** ------------------------------*/
1352 typedef union
1353 {
1354  struct
1355  {
1356  uint8_t z_ot_pol : 1; /* Z-axis outside of thresholds polarity flag. */
1357 
1358  uint8_t z_ot_ef : 1; /* Z-axis data or delta outside of upper and lower thresholds event flag. */
1359 
1360  uint8_t y_ot_pol : 1; /* Y-axis outside of thresholds polarity flag. */
1361 
1362  uint8_t y_ot_ef : 1; /* Y-axis data or delta outside of upper and lower thresholds event flag. */
1363 
1364  uint8_t x_ot_pol : 1; /* X-axis outside of thresholds polarity flag. */
1365 
1366  uint8_t x_ot_ef : 1; /* X-axis data or delta outside of upper and lower thresholds event flag. */
1367 
1368  uint8_t _reserved_ : 1;
1369  uint8_t ot_ea : 1; /* SDCD outside of thresholds event active flag. */
1370 
1371  } b;
1372  uint8_t w;
1373 } FXLS896x_SDCD_INT_SRC1_t;
1374 
1375 /*
1376 ** SDCD_INT_SRC1 - Bit field mask definitions
1377 */
1378 #define FXLS896x_SDCD_INT_SRC1_Z_OT_POL_MASK ((uint8_t)0x01)
1379 #define FXLS896x_SDCD_INT_SRC1_Z_OT_POL_SHIFT ((uint8_t)0)
1380 
1381 #define FXLS896x_SDCD_INT_SRC1_Z_OT_EF_MASK ((uint8_t)0x02)
1382 #define FXLS896x_SDCD_INT_SRC1_Z_OT_EF_SHIFT ((uint8_t)1)
1383 
1384 #define FXLS896x_SDCD_INT_SRC1_Y_OT_POL_MASK ((uint8_t)0x04)
1385 #define FXLS896x_SDCD_INT_SRC1_Y_OT_POL_SHIFT ((uint8_t)2)
1386 
1387 #define FXLS896x_SDCD_INT_SRC1_Y_OT_EF_MASK ((uint8_t)0x08)
1388 #define FXLS896x_SDCD_INT_SRC1_Y_OT_EF_SHIFT ((uint8_t)3)
1389 
1390 #define FXLS896x_SDCD_INT_SRC1_X_OT_POL_MASK ((uint8_t)0x10)
1391 #define FXLS896x_SDCD_INT_SRC1_X_OT_POL_SHIFT ((uint8_t)4)
1392 
1393 #define FXLS896x_SDCD_INT_SRC1_X_OT_EF_MASK ((uint8_t)0x20)
1394 #define FXLS896x_SDCD_INT_SRC1_X_OT_EF_SHIFT ((uint8_t)5)
1395 
1396 #define FXLS896x_SDCD_INT_SRC1_OT_EA_MASK ((uint8_t)0x80)
1397 #define FXLS896x_SDCD_INT_SRC1_OT_EA_SHIFT ((uint8_t)7)
1398 
1399 /*
1400 ** SDCD_INT_SRC1 - Bit field value definitions
1401 */
1402 #define FXLS896x_SDCD_INT_SRC1_OT_EA_INSIDE ((uint8_t)0x00) /* Event flag has not been asserted. */
1403 #define FXLS896x_SDCD_INT_SRC1_OT_EA_OUTSIDE ((uint8_t)0x80) /* Event flag has been asserted. */
1404 #define FXLS896x_SDCD_INT_SRC1_X_OT_EF_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */
1405 #define FXLS896x_SDCD_INT_SRC1_X_OT_EF_EVENT_YES ((uint8_t)0x20) /* Event has occured. */
1406 #define FXLS896x_SDCD_INT_SRC1_X_OT_POL_LT_THS ((uint8_t)0x00) /* Less than lower Threshold. */
1407 #define FXLS896x_SDCD_INT_SRC1_X_OT_POL_GT_THS ((uint8_t)0x10) /* Greater than upper threshold. */
1408 #define FXLS896x_SDCD_INT_SRC1_Y_OT_EF_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */
1409 #define FXLS896x_SDCD_INT_SRC1_Y_OT_EF_EVENT_YES ((uint8_t)0x08) /* Event has occured. */
1410 #define FXLS896x_SDCD_INT_SRC1_Y_OT_POL_LT_THS ((uint8_t)0x00) /* Less than lower Threshold. */
1411 #define FXLS896x_SDCD_INT_SRC1_Y_OT_POL_GT_THS ((uint8_t)0x04) /* Greater than upper threshold. */
1412 #define FXLS896x_SDCD_INT_SRC1_Z_OT_EF_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */
1413 #define FXLS896x_SDCD_INT_SRC1_Z_OT_EF_EVENT_YES ((uint8_t)0x02) /* Event has occured. */
1414 #define FXLS896x_SDCD_INT_SRC1_Z_OT_POL_LT_THS ((uint8_t)0x00) /* Less than lower Threshold. */
1415 #define FXLS896x_SDCD_INT_SRC1_Z_OT_POL_GT_THS ((uint8_t)0x01) /* Greater than upper threshold. */
1416  /*------------------------------*/
1417 
1418 /*--------------------------------
1419 ** Register: SDCD_INT_SRC2
1420 ** Enum: FXLS896x_SDCD_INT_SRC2
1421 ** --
1422 ** Offset : 0x2E Sensor data change detection function 2.
1423 ** ------------------------------*/
1424 typedef union
1425 {
1426  struct
1427  {
1428  uint8_t _reserved_ : 1;
1429  uint8_t z_wt_ef : 1; /* Z-axis data or delta inside of upper and lower thresholds event flag. */
1430 
1431  uint8_t _reserved_1 : 1;
1432  uint8_t y_wt_ef : 1; /* Y-axis data or delta inside of upper and lower thresholds event flag. */
1433 
1434  uint8_t _reserved_2 : 1;
1435  uint8_t x_wt_ef : 1; /* X-axis data or delta inside of upper and lower thresholds event flag. */
1436 
1437  uint8_t _reserved_3 : 1;
1438  uint8_t wt_ea : 1; /* SDCD within-thresholds event active flag. */
1439 
1440  } b;
1441  uint8_t w;
1442 } FXLS896x_SDCD_INT_SRC2_t;
1443 
1444 /*
1445 ** SDCD_INT_SRC2 - Bit field mask definitions
1446 */
1447 #define FXLS896x_SDCD_INT_SRC2_Z_WT_EF_MASK ((uint8_t)0x02)
1448 #define FXLS896x_SDCD_INT_SRC2_Z_WT_EF_SHIFT ((uint8_t)1)
1449 
1450 #define FXLS896x_SDCD_INT_SRC2_Y_WT_EF_MASK ((uint8_t)0x08)
1451 #define FXLS896x_SDCD_INT_SRC2_Y_WT_EF_SHIFT ((uint8_t)3)
1452 
1453 #define FXLS896x_SDCD_INT_SRC2_X_WT_EF_MASK ((uint8_t)0x20)
1454 #define FXLS896x_SDCD_INT_SRC2_X_WT_EF_SHIFT ((uint8_t)5)
1455 
1456 #define FXLS896x_SDCD_INT_SRC2_WT_EA_MASK ((uint8_t)0x80)
1457 #define FXLS896x_SDCD_INT_SRC2_WT_EA_SHIFT ((uint8_t)7)
1458 
1459 /*
1460 ** SDCD_INT_SRC2 - Bit field value definitions
1461 */
1462 #define FXLS896x_SDCD_INT_SRC2_WT_EA_EVENT_NO ((uint8_t)0x00) /* Event has not occured. */
1463 #define FXLS896x_SDCD_INT_SRC2_WT_EA_EVENT_YES ((uint8_t)0x80) /* Event has occured. */
1464 #define FXLS896x_SDCD_INT_SRC2_X_WT_EF_IN_RANGE ((uint8_t)0x00) /* X-axis data or delta is >= SDCD_UTHS or =< */
1465  /* SDCD_LTHS values. */
1466 #define FXLS896x_SDCD_INT_SRC2_X_WT_EF_OUT_RANGE ((uint8_t)0x20) /* X-axis data or delta is < SDCD_UTHS and > */
1467  /* SDCD_LTHS value. */
1468 #define FXLS896x_SDCD_INT_SRC2_Y_WT_EF_IN_RANGE ((uint8_t)0x00) /* Y-axis data or delta is >= SDCD_UTHS or =< */
1469  /* SDCD_LTHS values. */
1470 #define FXLS896x_SDCD_INT_SRC2_Y_WT_EF_OUT_RANGE ((uint8_t)0x08) /* Y-axis data or delta is < SDCD_UTHS and > */
1471  /* SDCD_LTHS value. */
1472 #define FXLS896x_SDCD_INT_SRC2_Z_WT_EF_IN_RANGE ((uint8_t)0x00) /* Z-axis data or delta is >= SDCD_UTHS or =< */
1473  /* SDCD_LTHS values. */
1474 #define FXLS896x_SDCD_INT_SRC2_Z_WT_EF_OUT_RANGE ((uint8_t)0x02) /* Z-axis data or delta is < SDCD_UTHS and > */
1475  /* SDCD_LTHS value. */
1476  /*------------------------------*/
1477 
1478 /*--------------------------------
1479 ** Register: SDCD_CONFIG1
1480 ** Enum: FXLS896x_SDCD_CONFIG1
1481 ** --
1482 ** Offset : 0x2F Sensor data change detection function 1 register.
1483 ** ------------------------------*/
1484 typedef union
1485 {
1486  struct
1487  {
1488  uint8_t z_wt_en : 1; /* SDCD function Z-axis within thresholds condition enable. */
1489 
1490  uint8_t y_wt_en : 1; /* SDCD function Y-axis within thresholds condition enable. */
1491 
1492  uint8_t x_wt_en : 1; /* SDCD function X-axis within thresholds condition enable. */
1493 
1494  uint8_t z_ot_en : 1; /* SDCD function Z-axis outside of thresholds condition enable. */
1495 
1496  uint8_t y_ot_en : 1; /* SDCD function Y-axis outside of thresholds condition enable. */
1497 
1498  uint8_t x_ot_en : 1; /* SDCD function X-axis outside of thresholds condition enable. */
1499 
1500  uint8_t wt_ele : 1; /* SDCD within thresholds event latch enable. */
1501 
1502  uint8_t ot_ele : 1; /* SDCD outside of thresholds event latch enable. */
1503 
1504  } b;
1505  uint8_t w;
1506 } FXLS896x_SDCD_CONFIG1_t;
1507 
1508 /*
1509 ** SDCD_CONFIG1 - Bit field mask definitions
1510 */
1511 #define FXLS896x_SDCD_CONFIG1_Z_WT_EN_MASK ((uint8_t)0x01)
1512 #define FXLS896x_SDCD_CONFIG1_Z_WT_EN_SHIFT ((uint8_t)0)
1513 
1514 #define FXLS896x_SDCD_CONFIG1_Y_WT_EN_MASK ((uint8_t)0x02)
1515 #define FXLS896x_SDCD_CONFIG1_Y_WT_EN_SHIFT ((uint8_t)1)
1516 
1517 #define FXLS896x_SDCD_CONFIG1_X_WT_EN_MASK ((uint8_t)0x04)
1518 #define FXLS896x_SDCD_CONFIG1_X_WT_EN_SHIFT ((uint8_t)2)
1519 
1520 #define FXLS896x_SDCD_CONFIG1_Z_OT_EN_MASK ((uint8_t)0x08)
1521 #define FXLS896x_SDCD_CONFIG1_Z_OT_EN_SHIFT ((uint8_t)3)
1522 
1523 #define FXLS896x_SDCD_CONFIG1_Y_OT_EN_MASK ((uint8_t)0x10)
1524 #define FXLS896x_SDCD_CONFIG1_Y_OT_EN_SHIFT ((uint8_t)4)
1525 
1526 #define FXLS896x_SDCD_CONFIG1_X_OT_EN_MASK ((uint8_t)0x20)
1527 #define FXLS896x_SDCD_CONFIG1_X_OT_EN_SHIFT ((uint8_t)5)
1528 
1529 #define FXLS896x_SDCD_CONFIG1_WT_ELE_MASK ((uint8_t)0x40)
1530 #define FXLS896x_SDCD_CONFIG1_WT_ELE_SHIFT ((uint8_t)6)
1531 
1532 #define FXLS896x_SDCD_CONFIG1_OT_ELE_MASK ((uint8_t)0x80)
1533 #define FXLS896x_SDCD_CONFIG1_OT_ELE_SHIFT ((uint8_t)7)
1534 
1535 /*
1536 ** SDCD_CONFIG1 - Bit field value definitions
1537 */
1538 #define FXLS896x_SDCD_CONFIG1_OT_ELE_DIS ((uint8_t)0x00) /* Outside of thresholds event flag latching is */
1539  /* disabled. */
1540 #define FXLS896x_SDCD_CONFIG1_OT_ELE_EN ((uint8_t)0x80) /* Outside of thresholds event flag latching is */
1541  /* enabled. */
1542 #define FXLS896x_SDCD_CONFIG1_WT_ELE_DIS ((uint8_t)0x00) /* Within thresholds event flag latching is */
1543  /* disabled. */
1544 #define FXLS896x_SDCD_CONFIG1_WT_ELE_EN ((uint8_t)0x40) /* Within thresholds event flag latching is */
1545  /* enabled. */
1546 #define FXLS896x_SDCD_CONFIG1_X_OT_EN_DIS ((uint8_t)0x00) /* X-axis data or delta is not used in the outside */
1547  /* of thresholds condition evaluation. */
1548 #define FXLS896x_SDCD_CONFIG1_X_OT_EN_EN ((uint8_t)0x20) /* X-axis data or delta is used in the outside of */
1549  /* thresholds condition evaluation. */
1550 #define FXLS896x_SDCD_CONFIG1_Y_OT_EN_DIS ((uint8_t)0x00) /* Y-axis data or delta is not used in the outside */
1551  /* of thresholds condition evaluation. */
1552 #define FXLS896x_SDCD_CONFIG1_Y_OT_EN_EN ((uint8_t)0x10) /* Y-axis data or delta is used in the outside of */
1553  /* thresholds condition evaluation. */
1554 #define FXLS896x_SDCD_CONFIG1_Z_OT_EN_DIS ((uint8_t)0x00) /* Z-axis data or delta is not used in the outside */
1555  /* of thresholds condition evaluation. */
1556 #define FXLS896x_SDCD_CONFIG1_Z_OT_EN_EN ((uint8_t)0x08) /* Z-axis data or delta is used in the outside of */
1557  /* thresholds condition evaluation. */
1558 #define FXLS896x_SDCD_CONFIG1_X_WT_EN_DIS ((uint8_t)0x00) /* X-axis data or delta is not used in the outside */
1559  /* of thresholds condition evaluation. */
1560 #define FXLS896x_SDCD_CONFIG1_X_WT_EN_EN ((uint8_t)0x04) /* X-axis data or delta is used in the outside of */
1561  /* thresholds condition evaluation. */
1562 #define FXLS896x_SDCD_CONFIG1_Y_WT_EN_DIS ((uint8_t)0x00) /* Y-axis data or delta is not used in the outside */
1563  /* of thresholds condition evaluation. */
1564 #define FXLS896x_SDCD_CONFIG1_Y_WT_EN_EN ((uint8_t)0x02) /* Y-axis data or delta is used in the outside of */
1565  /* thresholds condition evaluation. */
1566 #define FXLS896x_SDCD_CONFIG1_Z_WT_EN_DIS ((uint8_t)0x00) /* Z-axis data or delta is not used in the outside */
1567  /* of thresholds condition evaluation. */
1568 #define FXLS896x_SDCD_CONFIG1_Z_WT_EN_EN ((uint8_t)0x01) /* Z-axis data or delta is used in the outside of */
1569  /* thresholds condition evaluation. */
1570  /*------------------------------*/
1571 
1572 /*--------------------------------
1573 ** Register: SDCD_CONFIG2
1574 ** Enum: FXLS896x_SDCD_CONFIG2
1575 ** --
1576 ** Offset : 0x30 Sensor data change detection function 2 register.
1577 ** ------------------------------*/
1578 typedef union
1579 {
1580  struct
1581  {
1582  uint8_t ref_upd : 1; /* SDCD synchronous X/Y/Z reference values update bit. */
1583 
1584  uint8_t mode : 1; /* SDCD input data mode. */
1585 
1586  uint8_t wt_log_sel : 1; /* SDCD within thresholds event logic selection. */
1587 
1588  uint8_t wt_dbctm : 1; /* SDCD within thresholds event debounce counter behavior. */
1589 
1590  uint8_t ot_dbctm : 1; /* SDCD outside of threshold event debounce counter behavior. */
1591 
1592  uint8_t ref_updm : 2; /* SDCD internal reference values update mode. */
1593 
1594  uint8_t sdcd_en : 1; /* SDCD function. */
1595 
1596  } b;
1597  uint8_t w;
1598 } FXLS896x_SDCD_CONFIG2_t;
1599 
1600 /*
1601 ** SDCD_CONFIG2 - Bit field mask definitions
1602 */
1603 #define FXLS896x_SDCD_CONFIG2_REF_UPD_MASK ((uint8_t)0x01)
1604 #define FXLS896x_SDCD_CONFIG2_REF_UPD_SHIFT ((uint8_t)0)
1605 
1606 #define FXLS896x_SDCD_CONFIG2_MODE_MASK ((uint8_t)0x02)
1607 #define FXLS896x_SDCD_CONFIG2_MODE_SHIFT ((uint8_t)1)
1608 
1609 #define FXLS896x_SDCD_CONFIG2_WT_LOG_SEL_MASK ((uint8_t)0x04)
1610 #define FXLS896x_SDCD_CONFIG2_WT_LOG_SEL_SHIFT ((uint8_t)2)
1611 
1612 #define FXLS896x_SDCD_CONFIG2_WT_DBCTM_MASK ((uint8_t)0x08)
1613 #define FXLS896x_SDCD_CONFIG2_WT_DBCTM_SHIFT ((uint8_t)3)
1614 
1615 #define FXLS896x_SDCD_CONFIG2_OT_DBCTM_MASK ((uint8_t)0x10)
1616 #define FXLS896x_SDCD_CONFIG2_OT_DBCTM_SHIFT ((uint8_t)4)
1617 
1618 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_MASK ((uint8_t)0x60)
1619 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_SHIFT ((uint8_t)5)
1620 
1621 #define FXLS896x_SDCD_CONFIG2_SDCD_EN_MASK ((uint8_t)0x80)
1622 #define FXLS896x_SDCD_CONFIG2_SDCD_EN_SHIFT ((uint8_t)7)
1623 
1624 /*
1625 ** SDCD_CONFIG2 - Bit field value definitions
1626 */
1627 #define FXLS896x_SDCD_CONFIG2_SDCD_EN_DIS ((uint8_t)0x00) /* SDCD function is disabled. */
1628 #define FXLS896x_SDCD_CONFIG2_SDCD_EN_EN ((uint8_t)0x80) /* SDCD function is Enabled. */
1629 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_12_BIT ((uint8_t)0x00) /* The function stores the first 12-bit X/Y/Z */
1630  /* decimated and trimmed input data. */
1631 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_FIRST ((uint8_t)0x20) /* The function stores the first decimated and */
1632  /* trimmed X/Y/Z acceleration input data. */
1633 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_SDCD_REF ((uint8_t)0x40) /* The function updates the SDCD_REF_X/Y/Z values */
1634  /* with the current decimated and trimmed X/Y/Z */
1635  /* acceleration input data after the function */
1636  /* evaluation. */
1637 #define FXLS896x_SDCD_CONFIG2_REF_UPDM_FIXED_VAL ((uint8_t)0x60) /* The function uses a fixed value of 0 for each */
1638 /* of the SDCD_REF_X/Y/Z registers. */
1639 #define FXLS896x_SDCD_CONFIG2_OT_DBCTM_DECREMENT ((uint8_t)0x00) /* Debounce counter is decremented by 1 when the */
1640 /* current outside of thresholds result for the */
1641 /* enabled axes is false. */
1642 #define FXLS896x_SDCD_CONFIG2_OT_DBCTM_CLEARED ((uint8_t)0x10) /* Debounce counter is cleared whenever the */
1643  /* current outside of thresholds result for the */
1644  /* enabled axes is false. */
1645 #define FXLS896x_SDCD_CONFIG2_WT_DBCTM_DECREMENT ((uint8_t)0x00) /* Debounce counter is decremented by 1 when the */
1646 /* current outside of thresholds result for the */
1647 /* enabled axes is false. */
1648 #define FXLS896x_SDCD_CONFIG2_WT_DBCTM_CLEARED ((uint8_t)0x08) /* Debounce counter is cleared whenever the */
1649  /* current outside of thresholds result for the */
1650  /* enabled axes is false. */
1651 #define FXLS896x_SDCD_CONFIG2_WT_LOG_SEL_AND ((uint8_t)0x00) /* Function uses the logical AND of the enabled */
1652  /* axes. */
1653 #define FXLS896x_SDCD_CONFIG2_WT_LOG_SEL_OR ((uint8_t)0x04) /* Function uses the logical OR of the enabled */
1654  /* axes. */
1655 #define FXLS896x_SDCD_CONFIG2_MODE_XYZ ((uint8_t)0x00) /* Function uses X, Y, Z acceleration data for the */
1656  /* window comparison. */
1657 #define FXLS896x_SDCD_CONFIG2_MODE_VECM ((uint8_t)0x02) /* Function uses Vector magnitude data for the */
1658  /* window comparison on the X-axis channel only. */
1659 #define FXLS896x_SDCD_CONFIG2_REF_UPD_NO_PENDING \
1660  ((uint8_t)0x00) /* No reference update pending or reference update \ \ \
1661  */
1662 /* has completed. */
1663 #define FXLS896x_SDCD_CONFIG2_REF_UPD_SYNC_UPDATE ((uint8_t)0x01) /* Triggers a synchronous update of the internal */
1664  /* X/Y/Z reference registers. */
1665  /*------------------------------*/
1666 
1667 /*--------------------------------
1668 ** Register: SDCD_OT_DBCNT
1669 ** Enum: FXLS896x_SDCD_OT_DBCNT
1670 ** --
1671 ** Offset : 0x31 Sensor Data Change Detection outside of thresholds condition debounce count value.
1672 ** ------------------------------*/
1673 typedef uint8_t FXLS896x_SDCD_OT_DBCNT_t;
1674 
1675 /*--------------------------------
1676 ** Register: SDCD_WT_DBCNT
1677 ** Enum: FXLS896x_SDCD_WT_DBCNT
1678 ** --
1679 ** Offset : 0x32 Sensor Data Change Detection within thresholds condition debounce count value.
1680 ** ------------------------------*/
1681 typedef uint8_t FXLS896x_SDCD_WT_DBCNT_t;
1682 
1683 /*--------------------------------
1684 ** Register: SDCD_LTHS_LSB
1685 ** Enum: FXLS896x_SDCD_LTHS_LSB
1686 ** --
1687 ** Offset : 0x33 Sensor Data Change Detection lower threshold value LSB.
1688 ** ------------------------------*/
1689 typedef uint8_t FXLS896x_SDCD_LTHS_LSB_t;
1690 
1691 /*--------------------------------
1692 ** Register: SDCD_LTHS_MSB
1693 ** Enum: FXLS896x_SDCD_LTHS_MSB
1694 ** --
1695 ** Offset : 0x34 Sensor Data change Detection lower threshold value MSB.
1696 ** ------------------------------*/
1697 typedef uint8_t FXLS896x_SDCD_LTHS_MSB_t;
1698 
1699 /*--------------------------------
1700 ** Register: SDCD_UTHS_LSB
1701 ** Enum: FXLS896x_SDCD_UTHS_LSB
1702 ** --
1703 ** Offset : 0x35 Sensor Data change detection upper threshold value LSB.
1704 ** ------------------------------*/
1705 typedef uint8_t FXLS896x_SDCD_UTHS_LSB_t;
1706 
1707 /*--------------------------------
1708 ** Register: SDCD_UTHS_MSB
1709 ** Enum: FXLS896x_SDCD_UTHS_MSB
1710 ** --
1711 ** Offset : 0x36 Sensor Data change detection upper threshold value MSB.
1712 ** ------------------------------*/
1713 typedef uint8_t FXLS896x_SDCD_UTHS_MSB_t;
1714 
1715 
1716 /*--------------------------------
1717 ** Register: SELF_TEST_CONFIG1
1718 ** Enum: FXLS896x_SELF_TEST_CONFIG1
1719 ** --
1720 ** Offset : 0x37 Self Test Configuration function 1 register.
1721 ** ------------------------------*/
1722 typedef union
1723 {
1724  struct
1725  {
1726  uint8_t st_idle : 5; /* Self-Test Idle phase duration. */
1727 
1728  } b;
1729  uint8_t w;
1730 } FXLS896x_SELF_TEST_CONFIG1_t;
1731 
1732 /*
1733 ** SELF_TEST_CONFIG1 - Bit field mask definitions
1734 */
1735 #define FXLS896x_SELF_TEST_CONFIG1_ST_IDLE_MASK ((uint8_t)0x1f)
1736 #define FXLS896x_SELF_TEST_CONFIG1_ST_IDLE_SHIFT ((uint8_t)0)
1737 
1738 
1739 /*--------------------------------
1740 ** Register: SELF_TEST_CONFIG2
1741 ** Enum: FXLS896x_SELF_TEST_CONFIG2
1742 ** --
1743 ** Offset : 0x38 Self Test Configuration function 2 register.
1744 ** ------------------------------*/
1745 typedef union
1746 {
1747  struct
1748  {
1749  uint8_t st_dec : 4; /* Self-Test measurement phase decimation factor. */
1750 
1751  } b;
1752  uint8_t w;
1753 } FXLS896x_SELF_TEST_CONFIG2_t;
1754 
1755 /*
1756 ** SELF_TEST_CONFIG2 - Bit field mask definitions
1757 */
1758 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_MASK ((uint8_t)0x0f)
1759 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_SHIFT ((uint8_t)0)
1760 
1761 /*
1762 ** SELF_TEST_CONFIG2 - Bit field value definitions
1763 */
1764 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_1 ((uint8_t)0x00)
1765 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_2 ((uint8_t)0x01)
1766 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_4 ((uint8_t)0x02)
1767 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_8 ((uint8_t)0x03)
1768 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_16 ((uint8_t)0x04)
1769 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_32 ((uint8_t)0x05)
1770 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_64 ((uint8_t)0x06)
1771 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_128 ((uint8_t)0x07)
1772 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_256 ((uint8_t)0x08)
1773 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_512 ((uint8_t)0x09)
1774 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_1024 ((uint8_t)0x0a)
1775 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_2048 ((uint8_t)0x0b)
1776 #define FXLS896x_SELF_TEST_CONFIG2_ST_DEC_4096 ((uint8_t)0x0c)
1777 
1778 
1779 #endif /* FXLS896X_H_ */
FXLS896x_TEMP_OUT_t
uint8_t FXLS896x_TEMP_OUT_t
Definition: fxls896x.h:158
FXLS896x_OFF_Y_t
uint8_t FXLS896x_OFF_Y_t
Definition: fxls896x.h:988
FXLS896x_SDCD_OT_DBCNT_t
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Definition: fxls896x.h:1673
FXLS896x_INT_EN_t::sdcd_ot_en
uint8_t sdcd_ot_en
Definition: fxls896x.h:817
FXLS896x_BUF_Y_MSB_t
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Definition: fxls896x.h:290
FXLS896x_OUT_Y_LSB_t
uint8_t FXLS896x_OUT_Y_LSB_t
Definition: fxls896x.h:198
FXLS896x_INT_EN_t::sdcd_wt_en
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Definition: fxls896x.h:815
FXLS896x_BUF_X_MSB_t
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Definition: fxls896x.h:272
FXLS896x_INT_EN_t::drdy_en
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Definition: fxls896x.h:820
FXLS896x_ORIENT_DBCOUNT_t
uint8_t FXLS896x_ORIENT_DBCOUNT_t
Definition: fxls896x.h:1215
FXLS896x_WAKE_IDLE_LSB_t
uint8_t FXLS896x_WAKE_IDLE_LSB_t
Definition: fxls896x.h:755
FXLS896x_INT_EN_t::orient_en
uint8_t orient_en
Definition: fxls896x.h:813
FXLS896x_OUT_X_MSB_t
uint8_t FXLS896x_OUT_X_MSB_t
Definition: fxls896x.h:190
FXLS896x_OFF_Z_t
uint8_t FXLS896x_OFF_Z_t
Definition: fxls896x.h:996
FXLS896x_SLEEP_IDLE_LSB_t
uint8_t FXLS896x_SLEEP_IDLE_LSB_t
Definition: fxls896x.h:771
FXLS896x_OFF_X_t
uint8_t FXLS896x_OFF_X_t
Definition: fxls896x.h:980
FXLS896x_ASLP_COUNT_MSB_t
uint8_t FXLS896x_ASLP_COUNT_MSB_t
Definition: fxls896x.h:795
FXLS896x_BUF_Z_LSB_t
uint8_t FXLS896x_BUF_Z_LSB_t
Definition: fxls896x.h:299
FXLS896x_SLEEP_IDLE_MSB_t
uint8_t FXLS896x_SLEEP_IDLE_MSB_t
Definition: fxls896x.h:779
FXLS896x_VECM_LSB_t
uint8_t FXLS896x_VECM_LSB_t
Definition: fxls896x.h:166
FXLS896x_OUT_Y_MSB_t
uint8_t FXLS896x_OUT_Y_MSB_t
Definition: fxls896x.h:206
FXLS896x_INT_EN_t::boot_dis
uint8_t boot_dis
Definition: fxls896x.h:809
FXLS896x_VECM_MSB_t
uint8_t FXLS896x_VECM_MSB_t
Definition: fxls896x.h:174
FXLS896x_SYS_MODE_t::buf_gate_cnt
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Definition: fxls896x.h:359
FXLS896x_INT_EN_t::buf_en
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Definition: fxls896x.h:819
FXLS896x_SDCD_LTHS_MSB_t
uint8_t FXLS896x_SDCD_LTHS_MSB_t
Definition: fxls896x.h:1697
FXLS896x_INT_EN_t::wake_out_en
uint8_t wake_out_en
Definition: fxls896x.h:807
FXLS896x_BUF_Z_MSB_t
uint8_t FXLS896x_BUF_Z_MSB_t
Definition: fxls896x.h:308
FXLS896x_OUT_Z_MSB_t
uint8_t FXLS896x_OUT_Z_MSB_t
Definition: fxls896x.h:222
FXLS896x_PROD_REV_t::prod_rev_min
uint8_t prod_rev_min
Definition: fxls896x.h:320
FXLS896x_OUT_Z_LSB_t
uint8_t FXLS896x_OUT_Z_LSB_t
Definition: fxls896x.h:214
FXLS896x_ASLP_COUNT_LSB_t
uint8_t FXLS896x_ASLP_COUNT_LSB_t
Definition: fxls896x.h:787
FXLS896x_WHO_AM_I_t
uint8_t FXLS896x_WHO_AM_I_t
Definition: fxls896x.h:345
FXLS896x_INT_EN_t::aslp_en
uint8_t aslp_en
Definition: fxls896x.h:811
FXLS896x_SDCD_WT_DBCNT_t
uint8_t FXLS896x_SDCD_WT_DBCNT_t
Definition: fxls896x.h:1681
FXLS896x_SYS_MODE_t::buf_gate_error
uint8_t buf_gate_error
Definition: fxls896x.h:361
FXLS896x_SDCD_UTHS_MSB_t
uint8_t FXLS896x_SDCD_UTHS_MSB_t
Definition: fxls896x.h:1713
FXLS896x_BUF_Y_LSB_t
uint8_t FXLS896x_BUF_Y_LSB_t
Definition: fxls896x.h:281
FXLS896x_OUT_X_LSB_t
uint8_t FXLS896x_OUT_X_LSB_t
Definition: fxls896x.h:182
FXLS896x_BUF_X_LSB_t
uint8_t FXLS896x_BUF_X_LSB_t
Definition: fxls896x.h:263
FXLS896x_SDCD_UTHS_LSB_t
uint8_t FXLS896x_SDCD_UTHS_LSB_t
Definition: fxls896x.h:1705
FXLS896x_WAKE_IDLE_MSB_t
uint8_t FXLS896x_WAKE_IDLE_MSB_t
Definition: fxls896x.h:763
FXLS896x_PROD_REV_t::prod_rev_maj
uint8_t prod_rev_maj
Definition: fxls896x.h:323
FXLS896x_SDCD_LTHS_LSB_t
uint8_t FXLS896x_SDCD_LTHS_LSB_t
Definition: fxls896x.h:1689
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