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ISSDK
1.8
IoT Sensing Software Development Kit
|
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ISSDK
1.8
IoT Sensing Software Development Kit
|
Go to the source code of this file.
Data Structures | |
| union | MPL3115_OUT_P_LSB_t |
| union | MPL3115_OUT_T_LSB_t |
| union | MPL3115_DR_STATUS_t |
| union | MPL3115_OUT_P_DELTA_LSB_t |
| union | MPL3115_OUT_T_DELTA_LSB_t |
| union | MPL3115_F_STATUS_t |
| union | MPL3115_F_SETUP_t |
| union | MPL3115_SYSMOD_t |
| union | MPL3115_INT_SOURCE_t |
| union | MPL3115_PT_DATA_CFG_t |
| union | MPL3115_P_MIN_LSB_t |
| union | MPL3115_T_MIN_LSB_t |
| union | MPL3115_P_MAX_LSB_t |
| union | MPL3115_T_MAX_LSB_t |
| union | MPL3115_CTRL_REG1_t |
| union | MPL3115_CTRL_REG2_t |
| union | MPL3115_CTRL_REG3_t |
| union | MPL3115_CTRL_REG4_t |
| union | MPL3115_CTRL_REG5_t |
Macros | |
| #define | MPL3115_I2C_ADDRESS (0x60) /*MPL3115A2 Address*/ |
| #define | MPL3115_WHOAMI_VALUE (0xC4) |
| #define | MPL3115_OUT_P_LSB_PD_MASK ((uint8_t) 0xF0) |
| #define | MPL3115_OUT_P_LSB_PD_SHIFT ((uint8_t) 4) |
| #define | MPL3115_OUT_T_LSB_PD_MASK ((uint8_t) 0xF0) |
| #define | MPL3115_OUT_T_LSB_PD_SHIFT ((uint8_t) 4) |
| #define | MPL3115_DR_STATUS_TDR_MASK ((uint8_t) 0x02) |
| #define | MPL3115_DR_STATUS_TDR_SHIFT ((uint8_t) 1) |
| #define | MPL3115_DR_STATUS_PDR_MASK ((uint8_t) 0x04) |
| #define | MPL3115_DR_STATUS_PDR_SHIFT ((uint8_t) 2) |
| #define | MPL3115_DR_STATUS_PTDR_MASK ((uint8_t) 0x08) |
| #define | MPL3115_DR_STATUS_PTDR_SHIFT ((uint8_t) 3) |
| #define | MPL3115_DR_STATUS_TOW_MASK ((uint8_t) 0x20) |
| #define | MPL3115_DR_STATUS_TOW_SHIFT ((uint8_t) 5) |
| #define | MPL3115_DR_STATUS_POW_MASK ((uint8_t) 0x40) |
| #define | MPL3115_DR_STATUS_POW_SHIFT ((uint8_t) 6) |
| #define | MPL3115_DR_STATUS_PTOW_MASK ((uint8_t) 0x80) |
| #define | MPL3115_DR_STATUS_PTOW_SHIFT ((uint8_t) 7) |
| #define | MPL3115_DR_STATUS_TDR_DRDY ((uint8_t) 0x02) /* Set to 1 whenever a Temperature data acquisition is */ |
| #define | MPL3115_DR_STATUS_PDR_DRDY ((uint8_t) 0x04) /* Set to 1 whenever a new Pressure/Altitude data */ |
| #define | MPL3115_DR_STATUS_PTDR_DRDY ((uint8_t) 0x08) /* Signals that a new acquisition for either */ |
| #define | MPL3115_DR_STATUS_TOW_OWR ((uint8_t) 0x20) /* Set to 1 whenever a new Temperature acquisition is */ |
| #define | MPL3115_DR_STATUS_POW_OWR ((uint8_t) 0x40) /* Set to 1 whenever a new Pressure/Altitude */ |
| #define | MPL3115_DR_STATUS_PTOW_OWR ((uint8_t) 0x80) /* Set to 1 whenever new data is acquired before */ |
| #define | MPL3115_OUT_P_DELTA_LSB_PCD_MASK ((uint8_t) 0xF0) |
| #define | MPL3115_OUT_P_DELTA_LSB_PCD_SHIFT ((uint8_t) 4) |
| #define | MPL3115_OUT_T_DELTA_LSB_TCD_MASK ((uint8_t) 0xF0) |
| #define | MPL3115_OUT_T_DELTA_LSB_TCD_SHIFT ((uint8_t) 4) |
| #define | MPL3115_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F) |
| #define | MPL3115_F_STATUS_F_CNT_SHIFT ((uint8_t) 0) |
| #define | MPL3115_F_STATUS_F_WMKF_FLAG_MASK ((uint8_t) 0x40) |
| #define | MPL3115_F_STATUS_F_WMKF_FLAG_SHIFT ((uint8_t) 6) |
| #define | MPL3115_F_STATUS_F_OVF_MASK ((uint8_t) 0x80) |
| #define | MPL3115_F_STATUS_F_OVF_SHIFT ((uint8_t) 7) |
| #define | MPL3115_F_STATUS_F_WMKF_FLAG_NOEVT ((uint8_t) 0x00) /* No FIFO watermark event detected. */ |
| #define | MPL3115_F_STATUS_F_WMKF_FLAG_EVTDET ((uint8_t) 0x40) /* FIFO Watermark event has been detected. */ |
| #define | MPL3115_F_STATUS_F_OVF_NOOVFL ((uint8_t) 0x00) /* No FIFO overflow events detected. */ |
| #define | MPL3115_F_STATUS_F_OVF_OVFLDET ((uint8_t) 0x80) /* FIFO Overflow event has been detected. */ |
| #define | MPL3115_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F) |
| #define | MPL3115_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0) |
| #define | MPL3115_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0) |
| #define | MPL3115_F_SETUP_F_MODE_SHIFT ((uint8_t) 6) |
| #define | MPL3115_F_SETUP_F_MODE_FIFO_OFF ((uint8_t) 0x00) /* FIFO is disabled. */ |
| #define | MPL3115_F_SETUP_F_MODE_CIR_MODE ((uint8_t) 0x40) /* FIFO contains the most recent samples when overflowed */ |
| #define | MPL3115_F_SETUP_F_MODE_STOP_MODE ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed. */ |
| #define | MPL3115_SYSMOD_SYSMOD_MASK ((uint8_t) 0x01) |
| #define | MPL3115_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0) |
| #define | MPL3115_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* STANDBY Mode. */ |
| #define | MPL3115_SYSMOD_SYSMOD_ACTIVE ((uint8_t) 0x01) /* ACTIVE Mode. */ |
| #define | MPL3115_INT_SOURCE_SRC_TCHG_MASK ((uint8_t) 0x01) |
| #define | MPL3115_INT_SOURCE_SRC_TCHG_SHIFT ((uint8_t) 0) |
| #define | MPL3115_INT_SOURCE_SRC_PCHG_MASK ((uint8_t) 0x02) |
| #define | MPL3115_INT_SOURCE_SRC_PCHG_SHIFT ((uint8_t) 1) |
| #define | MPL3115_INT_SOURCE_SRC_TTH_MASK ((uint8_t) 0x04) |
| #define | MPL3115_INT_SOURCE_SRC_TTH_SHIFT ((uint8_t) 2) |
| #define | MPL3115_INT_SOURCE_SRC_PTH_MASK ((uint8_t) 0x08) |
| #define | MPL3115_INT_SOURCE_SRC_PTH_SHIFT ((uint8_t) 3) |
| #define | MPL3115_INT_SOURCE_SRC_TW_MASK ((uint8_t) 0x10) |
| #define | MPL3115_INT_SOURCE_SRC_TW_SHIFT ((uint8_t) 4) |
| #define | MPL3115_INT_SOURCE_SRC_PW_MASK ((uint8_t) 0x20) |
| #define | MPL3115_INT_SOURCE_SRC_PW_SHIFT ((uint8_t) 5) |
| #define | MPL3115_INT_SOURCE_SRC_FIFO_MASK ((uint8_t) 0x40) |
| #define | MPL3115_INT_SOURCE_SRC_FIFO_SHIFT ((uint8_t) 6) |
| #define | MPL3115_INT_SOURCE_SRC_DRDY_MASK ((uint8_t) 0x80) |
| #define | MPL3115_INT_SOURCE_SRC_DRDY_SHIFT ((uint8_t) 7) |
| #define | MPL3115_PT_DATA_CFG_TDEFE_MASK ((uint8_t) 0x01) |
| #define | MPL3115_PT_DATA_CFG_TDEFE_SHIFT ((uint8_t) 0) |
| #define | MPL3115_PT_DATA_CFG_PDEFE_MASK ((uint8_t) 0x02) |
| #define | MPL3115_PT_DATA_CFG_PDEFE_SHIFT ((uint8_t) 1) |
| #define | MPL3115_PT_DATA_CFG_DREM_MASK ((uint8_t) 0x04) |
| #define | MPL3115_PT_DATA_CFG_DREM_SHIFT ((uint8_t) 2) |
| #define | MPL3115_PT_DATA_CFG_TDEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
| #define | MPL3115_PT_DATA_CFG_TDEFE_ENABLED ((uint8_t) 0x01) /* Event detection enabled. Raise event flag on new */ |
| #define | MPL3115_PT_DATA_CFG_PDEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
| #define | MPL3115_PT_DATA_CFG_PDEFE_ENABLED ((uint8_t) 0x02) /* Event detection enabled. Raise event flag on new */ |
| #define | MPL3115_PT_DATA_CFG_DREM_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
| #define | MPL3115_PT_DATA_CFG_DREM_ENABLED ((uint8_t) 0x04) /* Event detection enabled. Generate data ready */ |
| #define | MPL3115_P_MIN_LSB_MINPAD_MASK ((uint8_t) 0xF0) |
| #define | MPL3115_P_MIN_LSB_MINPAD_SHIFT ((uint8_t) 4) |
| #define | MPL3115_T_MIN_LSB_MINTD_MASK ((uint8_t) 0xF0) |
| #define | MPL3115_T_MIN_LSB_MINTD_SHIFT ((uint8_t) 4) |
| #define | MPL3115_P_MAX_LSB_MAXPAD_MASK ((uint8_t) 0xF0) |
| #define | MPL3115_P_MAX_LSB_MAXPAD_SHIFT ((uint8_t) 4) |
| #define | MPL3115_T_MAX_LSB_MAXTD_MASK ((uint8_t) 0xF0) |
| #define | MPL3115_T_MAX_LSB_MAXTD_SHIFT ((uint8_t) 4) |
| #define | MPL3115_CTRL_REG1_SBYB_MASK ((uint8_t) 0x01) |
| #define | MPL3115_CTRL_REG1_SBYB_SHIFT ((uint8_t) 0) |
| #define | MPL3115_CTRL_REG1_OST_MASK ((uint8_t) 0x02) |
| #define | MPL3115_CTRL_REG1_OST_SHIFT ((uint8_t) 1) |
| #define | MPL3115_CTRL_REG1_RST_MASK ((uint8_t) 0x04) |
| #define | MPL3115_CTRL_REG1_RST_SHIFT ((uint8_t) 2) |
| #define | MPL3115_CTRL_REG1_OS_MASK ((uint8_t) 0x38) |
| #define | MPL3115_CTRL_REG1_OS_SHIFT ((uint8_t) 3) |
| #define | MPL3115_CTRL_REG1_RAW_MASK ((uint8_t) 0x40) |
| #define | MPL3115_CTRL_REG1_RAW_SHIFT ((uint8_t) 6) |
| #define | MPL3115_CTRL_REG1_ALT_MASK ((uint8_t) 0x80) |
| #define | MPL3115_CTRL_REG1_ALT_SHIFT ((uint8_t) 7) |
| #define | MPL3115_CTRL_REG1_SBYB_STANDBY ((uint8_t) 0x00) /* Standby Mode. */ |
| #define | MPL3115_CTRL_REG1_SBYB_ACTIVE ((uint8_t) 0x01) /* Active Mode. */ |
| #define | MPL3115_CTRL_REG1_OST_RESET ((uint8_t) 0x00) /* Reset OST Bit. */ |
| #define | MPL3115_CTRL_REG1_OST_SET ((uint8_t) 0x02) /* SET OST Bit. */ |
| #define | MPL3115_CTRL_REG1_RST_DIS ((uint8_t) 0x00) /* Device reset disabled. */ |
| #define | MPL3115_CTRL_REG1_RST_EN ((uint8_t) 0x04) /* Device reset enabled. */ |
| #define | MPL3115_CTRL_REG1_OS_OSR_1 ((uint8_t) 0x00) /* OSR = 1 and Minimum Time Between Data Samples 6 ms */ |
| #define | MPL3115_CTRL_REG1_OS_OSR_2 ((uint8_t) 0x08) /* OSR = 2 and Minimum Time Between Data Samples 10 ms */ |
| #define | MPL3115_CTRL_REG1_OS_OSR_4 ((uint8_t) 0x10) /* OSR = 4 and Minimum Time Between Data Samples 18 ms */ |
| #define | MPL3115_CTRL_REG1_OS_OSR_8 ((uint8_t) 0x18) /* OSR = 8 and Minimum Time Between Data Samples 34 ms */ |
| #define | MPL3115_CTRL_REG1_OS_OSR_16 ((uint8_t) 0x20) /* OSR = 16 and Minimum Time Between Data Samples 66 */ |
| #define | MPL3115_CTRL_REG1_OS_OSR_32 ((uint8_t) 0x28) /* OSR = 32 and Minimum Time Between Data Samples 130 */ |
| #define | MPL3115_CTRL_REG1_OS_OSR_64 ((uint8_t) 0x30) /* OSR = 64 and Minimum Time Between Data Samples 258 */ |
| #define | MPL3115_CTRL_REG1_OS_OSR_128 ((uint8_t) 0x38) /* OSR = 128 and Minimum Time Between Data Samples 512 */ |
| #define | MPL3115_CTRL_REG1_RAW_DIS ((uint8_t) 0x00) /* Raw output disabled. */ |
| #define | MPL3115_CTRL_REG1_RAW_EN ((uint8_t) 0x40) /* Raw output enabled. */ |
| #define | MPL3115_CTRL_REG1_ALT_ALT ((uint8_t) 0x80) /* Altimeter Mode. */ |
| #define | MPL3115_CTRL_REG1_ALT_BAR ((uint8_t) 0x00) /* Barometer Mode. */ |
| #define | MPL3115_CTRL_REG2_ST_MASK ((uint8_t) 0x0F) |
| #define | MPL3115_CTRL_REG2_ST_SHIFT ((uint8_t) 0) |
| #define | MPL3115_CTRL_REG2_ALARM_SEL_MASK ((uint8_t) 0x10) |
| #define | MPL3115_CTRL_REG2_ALARM_SEL_SHIFT ((uint8_t) 4) |
| #define | MPL3115_CTRL_REG2_LOAD_OUTPUT_MASK ((uint8_t) 0x20) |
| #define | MPL3115_CTRL_REG2_LOAD_OUTPUT_SHIFT ((uint8_t) 5) |
| #define | MPL3115_CTRL_REG2_ALARM_SEL_USE_TGT ((uint8_t) 0x00) /* The values in P_TGT_MSB, P_TGT_LSB and T_TGT are */ |
| #define | MPL3115_CTRL_REG2_ALARM_SEL_USE_OUT ((uint8_t) 0x10) /* The values in OUT_P/OUT_T are used for calculating */ |
| #define | MPL3115_CTRL_REG2_LOAD_OUTPUT_DNL ((uint8_t) 0x00) /* Do not load OUT_P/OUT_T as target values. */ |
| #define | MPL3115_CTRL_REG2_LOAD_OUTPUT_NXT_VAL ((uint8_t) 0x20) /* The next values of OUT_P/OUT_T are used to set the */ |
| #define | MPL3115_CTRL_REG3_PP_OD2_MASK ((uint8_t) 0x01) |
| #define | MPL3115_CTRL_REG3_PP_OD2_SHIFT ((uint8_t) 0) |
| #define | MPL3115_CTRL_REG3_IPOL2_MASK ((uint8_t) 0x02) |
| #define | MPL3115_CTRL_REG3_IPOL2_SHIFT ((uint8_t) 1) |
| #define | MPL3115_CTRL_REG3_PP_OD1_MASK ((uint8_t) 0x10) |
| #define | MPL3115_CTRL_REG3_PP_OD1_SHIFT ((uint8_t) 4) |
| #define | MPL3115_CTRL_REG3_IPOL1_MASK ((uint8_t) 0x20) |
| #define | MPL3115_CTRL_REG3_IPOL1_SHIFT ((uint8_t) 5) |
| #define | MPL3115_CTRL_REG3_PP_OD2_INTPULLUP ((uint8_t) 0x00) /* Internal Pull-up. */ |
| #define | MPL3115_CTRL_REG3_PP_OD2_OPENDRAIN ((uint8_t) 0x01) /* Open drain. */ |
| #define | MPL3115_CTRL_REG3_IPOL2_LOW ((uint8_t) 0x00) /* Active low. */ |
| #define | MPL3115_CTRL_REG3_IPOL2_HIGH ((uint8_t) 0x02) /* Active high. */ |
| #define | MPL3115_CTRL_REG3_PP_OD1_INTPULLUP ((uint8_t) 0x00) /* Internal Pull-up. */ |
| #define | MPL3115_CTRL_REG3_PP_OD1_OPENDRAIN ((uint8_t) 0x10) /* Open drain. */ |
| #define | MPL3115_CTRL_REG3_IPOL1_LOW ((uint8_t) 0x00) /* Active low. */ |
| #define | MPL3115_CTRL_REG3_IPOL1_HIGH ((uint8_t) 0x20) /* Active high. */ |
| #define | MPL3115_CTRL_REG4_INT_EN_TCHG_MASK ((uint8_t) 0x01) |
| #define | MPL3115_CTRL_REG4_INT_EN_TCHG_SHIFT ((uint8_t) 0) |
| #define | MPL3115_CTRL_REG4_INT_EN_PCHG_MASK ((uint8_t) 0x02) |
| #define | MPL3115_CTRL_REG4_INT_EN_PCHG_SHIFT ((uint8_t) 1) |
| #define | MPL3115_CTRL_REG4_INT_EN_TTH_MASK ((uint8_t) 0x04) |
| #define | MPL3115_CTRL_REG4_INT_EN_TTH_SHIFT ((uint8_t) 2) |
| #define | MPL3115_CTRL_REG4_INT_EN_PTH_MASK ((uint8_t) 0x08) |
| #define | MPL3115_CTRL_REG4_INT_EN_PTH_SHIFT ((uint8_t) 3) |
| #define | MPL3115_CTRL_REG4_INT_EN_TW_MASK ((uint8_t) 0x10) |
| #define | MPL3115_CTRL_REG4_INT_EN_TW_SHIFT ((uint8_t) 4) |
| #define | MPL3115_CTRL_REG4_INT_EN_PW_MASK ((uint8_t) 0x20) |
| #define | MPL3115_CTRL_REG4_INT_EN_PW_SHIFT ((uint8_t) 5) |
| #define | MPL3115_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40) |
| #define | MPL3115_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6) |
| #define | MPL3115_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x80) |
| #define | MPL3115_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 7) |
| #define | MPL3115_CTRL_REG4_INT_EN_TCHG_INTDISABLED ((uint8_t) 0x00) /* Temperature Change interrupt disabled. */ |
| #define | MPL3115_CTRL_REG4_INT_EN_TCHG_INTENABLED ((uint8_t) 0x01) /* Temperature Change interrupt enabled */ |
| #define | MPL3115_CTRL_REG4_INT_EN_PCHG_INTDISABLED ((uint8_t) 0x00) /* Pressure Change interrupt disabled. */ |
| #define | MPL3115_CTRL_REG4_INT_EN_PCHG_INTENABLED ((uint8_t) 0x02) /* Pressure Change interrupt enabled */ |
| #define | MPL3115_CTRL_REG4_INT_EN_TTH_INTDISABLED ((uint8_t) 0x00) /* Temperature Threshold interrupt disabled. */ |
| #define | MPL3115_CTRL_REG4_INT_EN_TTH_INTENABLED ((uint8_t) 0x04) /* Temperature Threshold interrupt enabled */ |
| #define | MPL3115_CTRL_REG4_INT_EN_PTH_INTDISABLED ((uint8_t) 0x00) /* Pressure Threshold interrupt disabled. */ |
| #define | MPL3115_CTRL_REG4_INT_EN_PTH_INTENABLED ((uint8_t) 0x08) /* Pressure Threshold interrupt enabled */ |
| #define | MPL3115_CTRL_REG4_INT_EN_TW_INTDISABLED ((uint8_t) 0x00) /* Temperature window interrupt disabled. */ |
| #define | MPL3115_CTRL_REG4_INT_EN_TW_INTENABLED ((uint8_t) 0x10) /* Temperature window interrupt enabled */ |
| #define | MPL3115_CTRL_REG4_INT_EN_PW_INTDISABLED ((uint8_t) 0x00) /* Pressure window interrupt disabled. */ |
| #define | MPL3115_CTRL_REG4_INT_EN_PW_INTENABLED ((uint8_t) 0x20) /* Pressure window interrupt enabled */ |
| #define | MPL3115_CTRL_REG4_INT_EN_FIFO_INTDISABLED ((uint8_t) 0x00) /* FIFO interrupt disabled. */ |
| #define | MPL3115_CTRL_REG4_INT_EN_FIFO_INTENABLED ((uint8_t) 0x40) /* FIFO interrupt enabled */ |
| #define | MPL3115_CTRL_REG4_INT_EN_DRDY_INTDISABLED ((uint8_t) 0x00) /* Data Ready interrupt disabled. */ |
| #define | MPL3115_CTRL_REG4_INT_EN_DRDY_INTENABLED ((uint8_t) 0x80) /* Data Ready interrupt enabled. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_TCHG_MASK ((uint8_t) 0x01) |
| #define | MPL3115_CTRL_REG5_INT_CFG_TCHG_SHIFT ((uint8_t) 0) |
| #define | MPL3115_CTRL_REG5_INT_CFG_PCHG_MASK ((uint8_t) 0x02) |
| #define | MPL3115_CTRL_REG5_INT_CFG_PCHG_SHIFT ((uint8_t) 1) |
| #define | MPL3115_CTRL_REG5_INT_CFG_TTH_MASK ((uint8_t) 0x04) |
| #define | MPL3115_CTRL_REG5_INT_CFG_TTH_SHIFT ((uint8_t) 2) |
| #define | MPL3115_CTRL_REG5_INT_CFG_PTH_MASK ((uint8_t) 0x08) |
| #define | MPL3115_CTRL_REG5_INT_CFG_PTH_SHIFT ((uint8_t) 3) |
| #define | MPL3115_CTRL_REG5_INT_CFG_TW_MASK ((uint8_t) 0x10) |
| #define | MPL3115_CTRL_REG5_INT_CFG_TW_SHIFT ((uint8_t) 4) |
| #define | MPL3115_CTRL_REG5_INT_CFG_PW_MASK ((uint8_t) 0x20) |
| #define | MPL3115_CTRL_REG5_INT_CFG_PW_SHIFT ((uint8_t) 5) |
| #define | MPL3115_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40) |
| #define | MPL3115_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6) |
| #define | MPL3115_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x80) |
| #define | MPL3115_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 7) |
| #define | MPL3115_CTRL_REG5_INT_CFG_TCHG_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_TCHG_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 Pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_PCHG_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_PCHG_INT1 ((uint8_t) 0x02) /* Interrupt is routed to INT1 Pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_TTH_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_TTH_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 Pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_PTH_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_PTH_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 Pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_TW_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_TW_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 Pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_PW_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_PW_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 Pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 Pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define | MPL3115_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 Pin. */ |
Typedefs | |
| typedef uint8_t | MPL3115_STATUS_t |
| typedef uint8_t | MPL3115_OUT_P_MSB_t |
| typedef uint8_t | MPL3115_OUT_P_CSB_t |
| typedef uint8_t | MPL3115_OUT_T_MSB_t |
| typedef uint8_t | MPL3115_OUT_P_DELTA_MSB_t |
| typedef uint8_t | MPL3115_OUT_P_DELTA_CSB_t |
| typedef uint8_t | MPL3115_OUT_T_DELTA_MSB_t |
| typedef uint8_t | MPL3115_WHO_AM_I_t |
| typedef uint8_t | MPL3115_F_DATA_t |
| typedef uint8_t | MPL3115_TIME_DLY_t |
| typedef uint8_t | MPL3115_BAR_IN_MSB_t |
| typedef uint8_t | MPL3115_BAR_IN_LSB_t |
| typedef uint8_t | MPL3115_P_TGT_MSB_t |
| typedef uint8_t | MPL3115_P_TGT_LSB_t |
| typedef uint8_t | MPL3115_T_TGT_t |
| typedef uint8_t | MPL3115_P_WND_MSB_t |
| typedef uint8_t | MPL3115_P_WND_LSB_t |
| typedef uint8_t | MPL3115_T_WND_t |
| typedef uint8_t | MPL3115_P_MIN_MSB_t |
| typedef uint8_t | MPL3115_P_MIN_CSB_t |
| typedef uint8_t | MPL3115_T_MIN_MSB_t |
| typedef uint8_t | MPL3115_P_MAX_MSB_t |
| typedef uint8_t | MPL3115_P_MAX_CSB_t |
| typedef uint8_t | MPL3115_T_MAX_MSB_t |
| typedef uint8_t | MPL3115_OFF_P_t |
| typedef uint8_t | MPL3115_OFF_T_t |
| typedef uint8_t | MPL3115_OFF_H_t |
| #define MPL3115_CTRL_REG1_ALT_ALT ((uint8_t) 0x80) /* Altimeter Mode. */ |
| #define MPL3115_CTRL_REG1_ALT_BAR ((uint8_t) 0x00) /* Barometer Mode. */ |
| #define MPL3115_CTRL_REG1_OS_OSR_1 ((uint8_t) 0x00) /* OSR = 1 and Minimum Time Between Data Samples 6 ms */ |
| #define MPL3115_CTRL_REG1_OS_OSR_128 ((uint8_t) 0x38) /* OSR = 128 and Minimum Time Between Data Samples 512 */ |
| #define MPL3115_CTRL_REG1_OS_OSR_16 ((uint8_t) 0x20) /* OSR = 16 and Minimum Time Between Data Samples 66 */ |
| #define MPL3115_CTRL_REG1_OS_OSR_2 ((uint8_t) 0x08) /* OSR = 2 and Minimum Time Between Data Samples 10 ms */ |
| #define MPL3115_CTRL_REG1_OS_OSR_32 ((uint8_t) 0x28) /* OSR = 32 and Minimum Time Between Data Samples 130 */ |
| #define MPL3115_CTRL_REG1_OS_OSR_4 ((uint8_t) 0x10) /* OSR = 4 and Minimum Time Between Data Samples 18 ms */ |
| #define MPL3115_CTRL_REG1_OS_OSR_64 ((uint8_t) 0x30) /* OSR = 64 and Minimum Time Between Data Samples 258 */ |
| #define MPL3115_CTRL_REG1_OS_OSR_8 ((uint8_t) 0x18) /* OSR = 8 and Minimum Time Between Data Samples 34 ms */ |
| #define MPL3115_CTRL_REG1_OST_MASK ((uint8_t) 0x02) |
| #define MPL3115_CTRL_REG1_OST_RESET ((uint8_t) 0x00) /* Reset OST Bit. */ |
| #define MPL3115_CTRL_REG1_OST_SET ((uint8_t) 0x02) /* SET OST Bit. */ |
| #define MPL3115_CTRL_REG1_RAW_DIS ((uint8_t) 0x00) /* Raw output disabled. */ |
| #define MPL3115_CTRL_REG1_RAW_EN ((uint8_t) 0x40) /* Raw output enabled. */ |
| #define MPL3115_CTRL_REG1_RST_DIS ((uint8_t) 0x00) /* Device reset disabled. */ |
| #define MPL3115_CTRL_REG1_RST_EN ((uint8_t) 0x04) /* Device reset enabled. */ |
Definition at line 873 of file mpl3115.h.
Referenced by MPL3115_I2C_DeInit().
| #define MPL3115_CTRL_REG1_RST_MASK ((uint8_t) 0x04) |
Definition at line 852 of file mpl3115.h.
Referenced by MPL3115_I2C_DeInit().
| #define MPL3115_CTRL_REG1_SBYB_ACTIVE ((uint8_t) 0x01) /* Active Mode. */ |
Definition at line 869 of file mpl3115.h.
Referenced by MPL3115_I2C_Configure().
| #define MPL3115_CTRL_REG1_SBYB_MASK ((uint8_t) 0x01) |
Definition at line 846 of file mpl3115.h.
Referenced by MPL3115_I2C_Configure().
| #define MPL3115_CTRL_REG1_SBYB_STANDBY ((uint8_t) 0x00) /* Standby Mode. */ |
Definition at line 868 of file mpl3115.h.
Referenced by MPL3115_I2C_Configure().
| #define MPL3115_CTRL_REG2_ALARM_SEL_USE_OUT ((uint8_t) 0x10) /* The values in OUT_P/OUT_T are used for calculating */ |
| #define MPL3115_CTRL_REG2_ALARM_SEL_USE_TGT ((uint8_t) 0x00) /* The values in P_TGT_MSB, P_TGT_LSB and T_TGT are */ |
| #define MPL3115_CTRL_REG2_LOAD_OUTPUT_DNL ((uint8_t) 0x00) /* Do not load OUT_P/OUT_T as target values. */ |
| #define MPL3115_CTRL_REG2_LOAD_OUTPUT_MASK ((uint8_t) 0x20) |
| #define MPL3115_CTRL_REG2_LOAD_OUTPUT_NXT_VAL ((uint8_t) 0x20) /* The next values of OUT_P/OUT_T are used to set the */ |
| #define MPL3115_CTRL_REG3_IPOL1_HIGH ((uint8_t) 0x20) /* Active high. */ |
| #define MPL3115_CTRL_REG3_IPOL1_LOW ((uint8_t) 0x00) /* Active low. */ |
| #define MPL3115_CTRL_REG3_IPOL2_HIGH ((uint8_t) 0x02) /* Active high. */ |
| #define MPL3115_CTRL_REG3_IPOL2_LOW ((uint8_t) 0x00) /* Active low. */ |
| #define MPL3115_CTRL_REG3_PP_OD1_INTPULLUP ((uint8_t) 0x00) /* Internal Pull-up. */ |
| #define MPL3115_CTRL_REG3_PP_OD1_OPENDRAIN ((uint8_t) 0x10) /* Open drain. */ |
| #define MPL3115_CTRL_REG3_PP_OD2_INTPULLUP ((uint8_t) 0x00) /* Internal Pull-up. */ |
| #define MPL3115_CTRL_REG3_PP_OD2_OPENDRAIN ((uint8_t) 0x01) /* Open drain. */ |
| #define MPL3115_CTRL_REG4_INT_EN_DRDY_INTDISABLED ((uint8_t) 0x00) /* Data Ready interrupt disabled. */ |
| #define MPL3115_CTRL_REG4_INT_EN_DRDY_INTENABLED ((uint8_t) 0x80) /* Data Ready interrupt enabled. */ |
| #define MPL3115_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x80) |
| #define MPL3115_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 7) |
| #define MPL3115_CTRL_REG4_INT_EN_FIFO_INTDISABLED ((uint8_t) 0x00) /* FIFO interrupt disabled. */ |
| #define MPL3115_CTRL_REG4_INT_EN_FIFO_INTENABLED ((uint8_t) 0x40) /* FIFO interrupt enabled */ |
| #define MPL3115_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40) |
| #define MPL3115_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6) |
| #define MPL3115_CTRL_REG4_INT_EN_PCHG_INTDISABLED ((uint8_t) 0x00) /* Pressure Change interrupt disabled. */ |
| #define MPL3115_CTRL_REG4_INT_EN_PCHG_INTENABLED ((uint8_t) 0x02) /* Pressure Change interrupt enabled */ |
| #define MPL3115_CTRL_REG4_INT_EN_PCHG_MASK ((uint8_t) 0x02) |
| #define MPL3115_CTRL_REG4_INT_EN_PCHG_SHIFT ((uint8_t) 1) |
| #define MPL3115_CTRL_REG4_INT_EN_PTH_INTDISABLED ((uint8_t) 0x00) /* Pressure Threshold interrupt disabled. */ |
| #define MPL3115_CTRL_REG4_INT_EN_PTH_INTENABLED ((uint8_t) 0x08) /* Pressure Threshold interrupt enabled */ |
| #define MPL3115_CTRL_REG4_INT_EN_PTH_MASK ((uint8_t) 0x08) |
| #define MPL3115_CTRL_REG4_INT_EN_PW_INTDISABLED ((uint8_t) 0x00) /* Pressure window interrupt disabled. */ |
| #define MPL3115_CTRL_REG4_INT_EN_PW_INTENABLED ((uint8_t) 0x20) /* Pressure window interrupt enabled */ |
| #define MPL3115_CTRL_REG4_INT_EN_PW_MASK ((uint8_t) 0x20) |
| #define MPL3115_CTRL_REG4_INT_EN_TCHG_INTDISABLED ((uint8_t) 0x00) /* Temperature Change interrupt disabled. */ |
| #define MPL3115_CTRL_REG4_INT_EN_TCHG_INTENABLED ((uint8_t) 0x01) /* Temperature Change interrupt enabled */ |
| #define MPL3115_CTRL_REG4_INT_EN_TCHG_MASK ((uint8_t) 0x01) |
| #define MPL3115_CTRL_REG4_INT_EN_TCHG_SHIFT ((uint8_t) 0) |
| #define MPL3115_CTRL_REG4_INT_EN_TTH_INTDISABLED ((uint8_t) 0x00) /* Temperature Threshold interrupt disabled. */ |
| #define MPL3115_CTRL_REG4_INT_EN_TTH_INTENABLED ((uint8_t) 0x04) /* Temperature Threshold interrupt enabled */ |
| #define MPL3115_CTRL_REG4_INT_EN_TTH_MASK ((uint8_t) 0x04) |
| #define MPL3115_CTRL_REG4_INT_EN_TW_INTDISABLED ((uint8_t) 0x00) /* Temperature window interrupt disabled. */ |
| #define MPL3115_CTRL_REG4_INT_EN_TW_INTENABLED ((uint8_t) 0x10) /* Temperature window interrupt enabled */ |
| #define MPL3115_CTRL_REG4_INT_EN_TW_MASK ((uint8_t) 0x10) |
| #define MPL3115_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 Pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x80) |
| #define MPL3115_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 7) |
| #define MPL3115_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 Pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40) |
| #define MPL3115_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6) |
| #define MPL3115_CTRL_REG5_INT_CFG_PCHG_INT1 ((uint8_t) 0x02) /* Interrupt is routed to INT1 Pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_PCHG_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_PCHG_MASK ((uint8_t) 0x02) |
| #define MPL3115_CTRL_REG5_INT_CFG_PCHG_SHIFT ((uint8_t) 1) |
| #define MPL3115_CTRL_REG5_INT_CFG_PTH_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 Pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_PTH_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_PTH_MASK ((uint8_t) 0x08) |
| #define MPL3115_CTRL_REG5_INT_CFG_PTH_SHIFT ((uint8_t) 3) |
| #define MPL3115_CTRL_REG5_INT_CFG_PW_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 Pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_PW_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_PW_MASK ((uint8_t) 0x20) |
| #define MPL3115_CTRL_REG5_INT_CFG_TCHG_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 Pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_TCHG_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_TCHG_MASK ((uint8_t) 0x01) |
| #define MPL3115_CTRL_REG5_INT_CFG_TCHG_SHIFT ((uint8_t) 0) |
| #define MPL3115_CTRL_REG5_INT_CFG_TTH_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 Pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_TTH_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_TTH_MASK ((uint8_t) 0x04) |
| #define MPL3115_CTRL_REG5_INT_CFG_TTH_SHIFT ((uint8_t) 2) |
| #define MPL3115_CTRL_REG5_INT_CFG_TW_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 Pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_TW_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */ |
| #define MPL3115_CTRL_REG5_INT_CFG_TW_MASK ((uint8_t) 0x10) |
| #define MPL3115_DR_STATUS_PDR_DRDY ((uint8_t) 0x04) /* Set to 1 whenever a new Pressure/Altitude data */ |
| #define MPL3115_DR_STATUS_POW_OWR ((uint8_t) 0x40) /* Set to 1 whenever a new Pressure/Altitude */ |
| #define MPL3115_DR_STATUS_PTDR_DRDY ((uint8_t) 0x08) /* Signals that a new acquisition for either */ |
| #define MPL3115_DR_STATUS_PTDR_MASK ((uint8_t) 0x08) |
| #define MPL3115_DR_STATUS_PTOW_OWR ((uint8_t) 0x80) /* Set to 1 whenever new data is acquired before */ |
| #define MPL3115_DR_STATUS_TDR_DRDY ((uint8_t) 0x02) /* Set to 1 whenever a Temperature data acquisition is */ |
| #define MPL3115_DR_STATUS_TOW_OWR ((uint8_t) 0x20) /* Set to 1 whenever a new Temperature acquisition is */ |
| #define MPL3115_F_SETUP_F_MODE_CIR_MODE ((uint8_t) 0x40) /* FIFO contains the most recent samples when overflowed */ |
| #define MPL3115_F_SETUP_F_MODE_FIFO_OFF ((uint8_t) 0x00) /* FIFO is disabled. */ |
| #define MPL3115_F_SETUP_F_MODE_STOP_MODE ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed. */ |
| #define MPL3115_F_STATUS_F_OVF_NOOVFL ((uint8_t) 0x00) /* No FIFO overflow events detected. */ |
| #define MPL3115_F_STATUS_F_OVF_OVFLDET ((uint8_t) 0x80) /* FIFO Overflow event has been detected. */ |
| #define MPL3115_F_STATUS_F_WMKF_FLAG_EVTDET ((uint8_t) 0x40) /* FIFO Watermark event has been detected. */ |
| #define MPL3115_F_STATUS_F_WMKF_FLAG_MASK ((uint8_t) 0x40) |
| #define MPL3115_F_STATUS_F_WMKF_FLAG_NOEVT ((uint8_t) 0x00) /* No FIFO watermark event detected. */ |
| #define MPL3115_PT_DATA_CFG_DREM_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
| #define MPL3115_PT_DATA_CFG_DREM_ENABLED ((uint8_t) 0x04) /* Event detection enabled. Generate data ready */ |
| #define MPL3115_PT_DATA_CFG_PDEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
| #define MPL3115_PT_DATA_CFG_PDEFE_ENABLED ((uint8_t) 0x02) /* Event detection enabled. Raise event flag on new */ |
| #define MPL3115_PT_DATA_CFG_TDEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */ |
| #define MPL3115_PT_DATA_CFG_TDEFE_ENABLED ((uint8_t) 0x01) /* Event detection enabled. Raise event flag on new */ |
| #define MPL3115_SYSMOD_SYSMOD_ACTIVE ((uint8_t) 0x01) /* ACTIVE Mode. */ |
| #define MPL3115_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* STANDBY Mode. */ |
| #define MPL3115_WHOAMI_VALUE (0xC4) |
| typedef uint8_t MPL3115_BAR_IN_LSB_t |
| typedef uint8_t MPL3115_BAR_IN_MSB_t |
| typedef uint8_t MPL3115_F_DATA_t |
| typedef uint8_t MPL3115_OFF_H_t |
| typedef uint8_t MPL3115_OFF_P_t |
| typedef uint8_t MPL3115_OFF_T_t |
| typedef uint8_t MPL3115_OUT_P_CSB_t |
| typedef uint8_t MPL3115_OUT_P_DELTA_CSB_t |
| typedef uint8_t MPL3115_OUT_P_DELTA_MSB_t |
| typedef uint8_t MPL3115_OUT_P_MSB_t |
| typedef uint8_t MPL3115_OUT_T_DELTA_MSB_t |
| typedef uint8_t MPL3115_OUT_T_MSB_t |
| typedef uint8_t MPL3115_P_MAX_CSB_t |
| typedef uint8_t MPL3115_P_MAX_MSB_t |
| typedef uint8_t MPL3115_P_MIN_CSB_t |
| typedef uint8_t MPL3115_P_MIN_MSB_t |
| typedef uint8_t MPL3115_P_TGT_LSB_t |
| typedef uint8_t MPL3115_P_TGT_MSB_t |
| typedef uint8_t MPL3115_P_WND_LSB_t |
| typedef uint8_t MPL3115_P_WND_MSB_t |
| typedef uint8_t MPL3115_STATUS_t |
| typedef uint8_t MPL3115_T_MAX_MSB_t |
| typedef uint8_t MPL3115_T_MIN_MSB_t |
| typedef uint8_t MPL3115_T_TGT_t |
| typedef uint8_t MPL3115_T_WND_t |
| typedef uint8_t MPL3115_TIME_DLY_t |
| typedef uint8_t MPL3115_WHO_AM_I_t |
| anonymous enum |
MPL3115 Sensor Internal Registers