ISSDK  1.8
IoT Sensing Software Development Kit
clock_config.c
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 /*
10  * How to setup clock using clock driver functions:
11  *
12  * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
13  * Note: The clock could not be set when it is being used as system clock.
14  * In default out of reset, the CPU is clocked from FIRC(IRC48M),
15  * so before setting FIRC, change to use another avaliable clock source.
16  *
17  * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
18  *
19  * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
20  * Wait until the system clock source is changed to target source.
21  *
22  * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
23  * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
24  * Supported run mode and clock restrictions could be found in Reference Manual.
25  */
26 
27 /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
28 !!ClocksProfile
29 product: Clocks v1.0
30 processor: MKE15Z256xxx7
31 package_id: MKE15Z256VLL7
32 mcu_data: ksdk2_0
33 processor_version: 1.1.0
34  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
35 
36 #include "fsl_smc.h"
37 #include "clock_config.h"
38 
39 /*******************************************************************************
40  * Definitions
41  ******************************************************************************/
42 
43 /*******************************************************************************
44  * Variables
45  ******************************************************************************/
46 /* System clock frequency. */
47 extern uint32_t SystemCoreClock;
48 
49 /*******************************************************************************
50  * Code
51  ******************************************************************************/
52 /*FUNCTION**********************************************************************
53  *
54  * Function Name : CLOCK_CONFIG_FircSafeConfig
55  * Description : This function is used to safely configure FIRC clock.
56  * In default out of reset, the CPU is clocked from FIRC(IRC48M).
57  * Before setting FIRC, change to use SIRC as system clock,
58  * then configure FIRC. After FIRC is set, change back to use FIRC
59  * in case SIRC need to be configured.
60  * Param fircConfig : FIRC configuration.
61  *
62  *END**************************************************************************/
63 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
64 {
65  scg_sys_clk_config_t curConfig;
66  const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
67  .div1 = kSCG_AsyncClkDisable,
68  .div2 = kSCG_AsyncClkDivBy2,
69  .range = kSCG_SircRangeHigh};
70  scg_sys_clk_config_t sysClkSafeConfigSource = {
71  .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
72  .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
73  .src = kSCG_SysClkSrcSirc /* System clock source */
74  };
75  /* Init Sirc. */
76  CLOCK_InitSirc(&scgSircConfig);
77  /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
78  CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
79  /* Wait for clock source switch finished. */
80  do
81  {
82  CLOCK_GetCurSysClkConfig(&curConfig);
83  } while (curConfig.src != sysClkSafeConfigSource.src);
84 
85  /* Init Firc. */
86  CLOCK_InitFirc(fircConfig);
87  /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
88  sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
89  CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
90  /* Wait for clock source switch finished. */
91  do
92  {
93  CLOCK_GetCurSysClkConfig(&curConfig);
94  } while (curConfig.src != sysClkSafeConfigSource.src);
95 }
96 
97 /*******************************************************************************
98  ********************** Configuration BOARD_BootClockRUN ***********************
99  ******************************************************************************/
100 /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
101 !!Configuration
102 name: BOARD_BootClockRUN
103 outputs:
104 - {id: Bus_clock.outFreq, value: 24 MHz}
105 - {id: Core_clock.outFreq, value: 72 MHz}
106 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
107 - {id: FLLDIV2_CLK.outFreq, value: 36 MHz}
108 - {id: Flash_clock.outFreq, value: 24 MHz}
109 - {id: LPO1KCLK.outFreq, value: 1 kHz}
110 - {id: LPO_clock.outFreq, value: 128 kHz}
111 - {id: SIRCDIV2_CLK.outFreq, value: 4 MHz}
112 - {id: SIRC_CLK.outFreq, value: 8 MHz}
113 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
114 - {id: SOSC_CLK.outFreq, value: 8 MHz}
115 - {id: System_clock.outFreq, value: 72 MHz}
116 settings:
117 - {id: SCGMode, value: LPFLL}
118 - {id: OSC32_CR_ROSCE_CFG, value: Enabled}
119 - {id: SCG.DIVCORE.scale, value: '1', locked: true}
120 - {id: SCG.DIVSLOW.scale, value: '3', locked: true}
121 - {id: SCG.FIRCDIV2.scale, value: '1'}
122 - {id: SCG.LPFLLDIV2.scale, value: '2'}
123 - {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
124 - {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
125 - {id: SCG.SIRCDIV2.scale, value: '2'}
126 - {id: SCG.SOSCDIV2.scale, value: '1'}
127 - {id: SCG.TRIMDIV.scale, value: '4'}
128 - {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
129 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
130 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
131 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
132 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
133 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
134 sources:
135 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
136  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
137 
138 /*******************************************************************************
139  * Variables for BOARD_BootClockRUN configuration
140  ******************************************************************************/
141 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
142  {
143  .divSlow = kSCG_SysClkDivBy3, /* Slow Clock Divider: divided by 3 */
144  .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
145  .src = kSCG_SysClkSrcLpFll, /* Low power FLL is selected as System Clock Source */
146  };
147 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
148  {
149  .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
150  .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableInLowPower,/* Enable System OSC clock, Enable System OSC in low power mode */
151  .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
152  .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
153  .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
154  };
155 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
156  {
157  .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
158  .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
159  .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
160  };
161 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
162  {
163  .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
164  .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
165  .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
166  .trimConfig = NULL, /* Fast IRC Trim disabled */
167  };
168 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
169  {
170  .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
171  .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
172  .range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
173  .trimConfig = NULL,
174  };
175 /*******************************************************************************
176  * Code for BOARD_BootClockRUN configuration
177  ******************************************************************************/
179 {
180  scg_sys_clk_config_t curConfig;
181 
182  /* Init SOSC according to board configuration. */
183  CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
184  /* Set the XTAL0 frequency based on board settings. */
185  CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
186  /* Init FIRC. */
187  CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
188  /* Init SIRC. */
189  CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
190  /* Init LPFLL. */
191  CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
192  /* Set SCG to LPFLL mode. */
193  CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
194  /* Wait for clock source switch finished. */
195  do
196  {
197  CLOCK_GetCurSysClkConfig(&curConfig);
198  } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
199  /* Set SystemCoreClock variable. */
201 }
202 
203 /*******************************************************************************
204  ********************* Configuration BOARD_BootClockVLPR ***********************
205  ******************************************************************************/
206 /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
207 !!Configuration
208 name: BOARD_BootClockVLPR
209 outputs:
210 - {id: Bus_clock.outFreq, value: 1 MHz}
211 - {id: Core_clock.outFreq, value: 4 MHz}
212 - {id: Flash_clock.outFreq, value: 1 MHz}
213 - {id: LPO1KCLK.outFreq, value: 1 kHz}
214 - {id: LPO_clock.outFreq, value: 128 kHz}
215 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
216 - {id: SOSC_CLK.outFreq, value: 8 MHz}
217 - {id: System_clock.outFreq, value: 4 MHz}
218 settings:
219 - {id: SCGMode, value: SOSC}
220 - {id: powerMode, value: VLPR}
221 - {id: OSC32_CR_ROSCE_CFG, value: Enabled}
222 - {id: SCG.DIVCORE.scale, value: '2', locked: true}
223 - {id: SCG.DIVSLOW.scale, value: '4', locked: true}
224 - {id: SCG.FIRCDIV2.scale, value: '1'}
225 - {id: SCG.LPFLLDIV2.scale, value: '2'}
226 - {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
227 - {id: SCG.SCSSEL.sel, value: SCG.SOSC}
228 - {id: SCG.SIRCDIV2.scale, value: '2'}
229 - {id: SCG.SOSCDIV2.scale, value: '1'}
230 - {id: SCG.TRIMDIV.scale, value: '4'}
231 - {id: 'SCG::RCCR[DIVSLOW].bitField', value: Divide-by-3}
232 - {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
233 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
234 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
235 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
236 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
237 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
238 sources:
239 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
240  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
241 
242 /*******************************************************************************
243  * Variables for BOARD_BootClockVLPR configuration
244  ******************************************************************************/
245 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
246  {
247  .divSlow = kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
248  .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
249  .src = kSCG_SysClkSrcSysOsc, /* System OSC is selected as System Clock Source */
250  };
251 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
252  {
253  .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
254  .enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableInLowPower,/* Enable System OSC clock, Enable System OSC in low power mode */
255  .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
256  .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
257  .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
258  };
259 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
260  {
261  .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
262  .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
263  .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
264  };
265 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
266  {
267  .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
268  .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
269  .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
270  .trimConfig = NULL, /* Fast IRC Trim disabled */
271  };
272 const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR =
273  {
274  .enableMode = kSCG_LpFllEnable, /* Enable LPFLL clock */
275  .div2 = kSCG_AsyncClkDivBy2, /* Low Power FLL Clock Divider 2: divided by 2 */
276  .range = kSCG_LpFllRange72M, /* LPFLL is trimmed to 72MHz */
277  .trimConfig = NULL,
278  };
279 /*******************************************************************************
280  * Code for BOARD_BootClockVLPR configuration
281  ******************************************************************************/
283 {
284  /* Init SOSC according to board configuration. */
285  CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockVLPR);
286  /* Set the XTAL0 frequency based on board settings. */
287  CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockVLPR.freq);
288  /* Set SCG to SOSC mode. */
289  CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
290  /* Allow SMC all power modes. */
291  SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
292  /* Set VLPR power mode. */
294  while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
295  {
296  }
297  /* Set SystemCoreClock variable. */
299 }
300 
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN
SIRC set for BOARD_BootClockRUN configuration.
Definition: clock_config.c:155
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN
SCG set for BOARD_BootClockRUN configuration.
Definition: clock_config.c:141
const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR
SCG set for BOARD_BootClockVLPR configuration.
Definition: clock_config.c:245
void BOARD_BootClockVLPR(void)
This function executes configuration of clocks.
Definition: clock_config.c:266
status_t SMC_SetPowerModeVlpr(void *arg)
Configures the system to VLPR power mode. API name used from Kinetis family to maintain compatibility...
Definition: lpc54114.c:169
#define SMC
Definition: lpc54114.h:118
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN
System OSC set for BOARD_BootClockRUN configuration.
Definition: clock_config.c:147
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR
Definition: clock_config.c:265
const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR
System OSC set for BOARD_BootClockVLPR configuration.
Definition: clock_config.c:251
const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN
Definition: clock_config.c:161
uint32_t SystemCoreClock
void BOARD_BootClockRUN(void)
This function executes configuration of clocks.
Definition: clock_config.c:168
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK
Definition: clock_config.h:60
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR
Definition: clock_config.c:272
const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR
SIRC set for BOARD_BootClockVLPR configuration.
Definition: clock_config.c:259
const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN
Definition: clock_config.c:168
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK
Definition: clock_config.h:25