LPC865

Clock Driver

enum _clock_ip_name

Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock.

Values:

enumerator kCLOCK_IpInvalid: Invalid Ip Name.

enumerator kCLOCK_Rom: Clock gate name: Rom.

enumerator kCLOCK_Ram0_1: Clock gate name: Ram0_1.

enumerator kCLOCK_I2c0: Clock gate name: I2c0.

enumerator kCLOCK_Gpio0: Clock gate name: Gpio0.

enumerator kCLOCK_Swm: Clock gate name: Swm.

enumerator kCLOCK_Wkt: Clock gate name: Wkt.

enumerator kCLOCK_Mrt: Clock gate name: Mrt.

enumerator kCLOCK_Spi0: Clock gate name: Spi0.

enumerator kCLOCK_Spi1: Clock gate name: Spi1.

enumerator kCLOCK_Crc: Clock gate name: Crc.

enumerator kCLOCK_Uart0: Clock gate name: Uart0.

enumerator kCLOCK_Uart1: Clock gate name: Uart1.

enumerator kCLOCK_Uart2: Clock gate name: Uart2.

enumerator kCLOCK_Wwdt: Clock gate name: Wwdt.

enumerator kCLOCK_Iocon: Clock gate name: Iocon.

enumerator kCLOCK_Acmp: Clock gate name: Acmp.

enumerator kCLOCK_Gpio1: Clock gate name: Gpio1.

enumerator kCLOCK_Ftm0: Clock gate name: Ftm0.

enumerator kCLOCK_Ftm1: Clock gate name: Ftm1.

enumerator kCLOCK_I3c0: Clock gate name: I3c0.

enumerator kCLOCK_Adc: Clock gate name: Adc.

enumerator kCLOCK_GpioInt: Clock gate name: GpioInt.

enumerator kCLOCK_Dma: Clock gate name: Dma.

enum _clock_name

Clock name used to get clock frequency.

Values:

enumerator kCLOCK_CoreSysClk: Cpu/AHB/AHB matrix/Memories,etc

enumerator kCLOCK_MainClk: Main clock

enumerator kCLOCK_Fro: FRO18/24/30

enumerator kCLOCK_FroDiv: FRO div clock

enumerator kCLOCK_ExtClk: External Clock

enumerator kCLOCK_PllOut: PLL Output

enumerator kCLOCK_LpOsc: Low power Oscillator

enumerator kCLOCK_Frg0: fractional rate0

enumerator kCLOCK_Frg1: fractional rate1

enum _clock_select

Clock Mux Switches CLK_MUX_DEFINE(reg, mux) reg is used to define the mux register mux is used to define the mux value.

Values:

enumerator kADC_Clk_From_Fro: Mux ADC_Clk from Fro.

enumerator kADC_Clk_From_SysPll_DIV: Mux ADC_Clk from SysPllDiv.

enumerator kEXT_Clk_From_SysOsc: Mux EXT_Clk from SysOsc.

enumerator kEXT_Clk_From_ClkIn: Mux EXT_Clk from ClkIn.

enumerator kUART0_Clk_From_Fro: Mux UART0_Clk from Fro.

enumerator kUART0_Clk_From_MainClk: Mux UART0_Clk from MainClk.

enumerator kUART0_Clk_From_Frg0Clk: Mux UART0_Clk from Frg0Clk.

enumerator kUART0_Clk_From_Frg1Clk: Mux UART0_Clk from Frg1Clk.

enumerator kUART0_Clk_From_Fro_Div: Mux UART0_Clk from Fro_Div.

enumerator kUART1_Clk_From_Fro: Mux UART1_Clk from Fro.

enumerator kUART1_Clk_From_MainClk: Mux UART1_Clk from MainClk.

enumerator kUART1_Clk_From_Frg0Clk: Mux UART1_Clk from Frg0Clk.

enumerator kUART1_Clk_From_Frg1Clk: Mux UART1_Clk from Frg1Clk.

enumerator kUART1_Clk_From_Fro_Div: Mux UART1_Clk from Fro_Div.

enumerator kUART2_Clk_From_Fro: Mux UART2_Clk from Fro.

enumerator kUART2_Clk_From_MainClk: Mux UART2_Clk from MainClk.

enumerator kUART2_Clk_From_Frg0Clk: Mux UART2_Clk from Frg0Clk.

enumerator kUART2_Clk_From_Frg1Clk: Mux UART2_Clk from Frg1Clk.

enumerator kUART2_Clk_From_Fro_Div: Mux UART2_Clk from Fro_Div.

enumerator kI2C0_Clk_From_Fro: Mux I2C0_Clk from Fro.

enumerator kI2C0_Clk_From_MainClk: Mux I2C0_Clk from MainClk.

enumerator kI2C0_Clk_From_Frg0Clk: Mux I2C0_Clk from Frg0Clk.

enumerator kI2C0_Clk_From_Frg1Clk: Mux I2C0_Clk from Frg1Clk.

enumerator kI2C0_Clk_From_Fro_Div: Mux I2C0_Clk from Fro_Div.

enumerator kI3C_Clk_From_Fro: Mux I3C_Clk from Fro.

enumerator kI3C_Clk_From_ExtClk: Mux I3C_Clk from ExtClk.

enumerator kI3C_TC_Clk_From_I3C_Clk: Mux I3C_TC_Clk from I3C_Clk.

enumerator kI3C_TC_Clk_From_LpOsc: Mux I3C_TC_Clk from LpOsc.

enumerator kSPI0_Clk_From_Fro: Mux SPI0_Clk from Fro.

enumerator kSPI0_Clk_From_MainClk: Mux SPI0_Clk from MainClk.

enumerator kSPI0_Clk_From_Frg0Clk: Mux SPI0_Clk from Frg0Clk.

enumerator kSPI0_Clk_From_Frg1Clk: Mux SPI0_Clk from Frg1Clk.

enumerator kSPI0_Clk_From_Fro_Div: Mux SPI0_Clk from Fro_Div.

enumerator kSPI1_Clk_From_Fro: Mux SPI1_Clk from Fro.

enumerator kSPI1_Clk_From_MainClk: Mux SPI1_Clk from MainClk.

enumerator kSPI1_Clk_From_Frg0Clk: Mux SPI1_Clk from Frg0Clk.

enumerator kSPI1_Clk_From_Frg1Clk: Mux SPI1_Clk from Frg1Clk.

enumerator kSPI1_Clk_From_Fro_Div: Mux SPI1_Clk from Fro_Div.

enumerator kFRG0_Clk_From_Fro: Mux FRG0_Clk from Fro.

enumerator kFRG0_Clk_From_MainClk: Mux FRG0_Clk from MainClk.

enumerator kFRG0_Clk_From_SysPll_DIV: Mux FRG0_Clk from SysPllDiv.

enumerator kFRG1_Clk_From_Fro: Mux FRG1_Clk from Fro.

enumerator kFRG1_Clk_From_MainClk: Mux FRG1_Clk from MainClk.

enumerator kFRG1_Clk_From_SysPll_DIV: Mux FRG1_Clk from SysPllDiv.

enumerator kCLKOUT_From_Fro: Mux CLKOUT from Fro.

enumerator kCLKOUT_From_MainClk: Mux CLKOUT from MainClk.

enumerator kCLKOUT_From_SysPll_DIV: Mux CLKOUT from SysPllDiv.

enumerator kCLKOUT_From_ExtClk: Mux CLKOUT from ExtClk.

enumerator kCLKOUT_From_LpOsc: Mux CLKOUT from LpOsc.

enumerator kWKT_Clk_From_Fro: Mux Wkt_Clk from FroOsc.

enumerator kWKT_Clk_From_LpOsc: Mux Wkt_Clk from LpOsc.

enum _clock_divider

Clock divider.

Values:

enumerator kCLOCK_DivPllClk: Pll Clock Divider.

enumerator kCLOCK_DivAdcClk: Adc Clock Divider.

enumerator kCLOCK_DivClkOut: Clk Out Divider.

enumerator kCLOCK_IOCONCLKDiv6: IOCON Clock Div6 Divider.

enumerator kCLOCK_IOCONCLKDiv5: IOCON Clock Div5 Divider.

enumerator kCLOCK_IOCONCLKDiv4: IOCON Clock Div4 Divider.

enumerator kCLOCK_IOCONCLKDiv3: IOCON Clock Div3 Divider.

enumerator kCLOCK_IOCONCLKDiv2: IOCON Clock Div2 Divider.

enumerator kCLOCK_IOCONCLKDiv1: IOCON Clock Div1 Divider.

enumerator kCLOCK_IOCONCLKDiv0: IOCON Clock Div0 Divider.

enum _clock_fro_src

fro output frequency source definition

Values:

enumerator kCLOCK_FroSrcFroOscDiv: fro source from the fro oscillator divided by 2

enumerator kCLOCK_FroSrcFroOsc: fre source from the fro oscillator directly

enum _clock_fro_osc_freq

fro oscillator output frequency value definition

Values:

enumerator kCLOCK_FroOscOut36M: FRO oscillator output 36M

enumerator kCLOCK_FroOscOut48M: FRO oscillator output 48M

enumerator kCLOCK_FroOscOut60M: FRO oscillator output 60M

enum _clock_sys_pll_src

PLL clock definition.

Values:

enumerator kCLOCK_SysPllSrcFRO: system pll source from FRO

enumerator kCLOCK_SysPllSrcExtClk: system pll source from external clock

enumerator kCLOCK_SysPllSrcLpOsc: system pll source from Low power oscillator

enumerator kCLOCK_SysPllSrcFroDiv: system pll source from FRO divided clock

enum _clock_main_clk_src

Main clock source definition.

Values:

enumerator kCLOCK_MainClkSrcFro: main clock source from FRO

enumerator kCLOCK_MainClkSrcExtClk: main clock source from Ext clock

enumerator kCLOCK_MainClkSrcLpOsc: main clock source from Low power oscillator

enumerator kCLOCK_MainClkSrcFroDiv: main clock source from FRO Div

enumerator kCLOCK_MainClkSrcSysPll: main clock source from system pll

typedef enum _clock_ip_name clock_ip_name_t: Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock.

typedef enum _clock_name clock_name_t: Clock name used to get clock frequency.

typedef enum _clock_select clock_select_t: Clock Mux Switches CLK_MUX_DEFINE(reg, mux) reg is used to define the mux register mux is used to define the mux value.

typedef enum _clock_divider clock_divider_t: Clock divider.

typedef enum _clock_fro_src clock_fro_src_t: fro output frequency source definition

typedef enum _clock_fro_osc_freq clock_fro_osc_freq_t: fro oscillator output frequency value definition

typedef enum _clock_sys_pll_src clock_sys_pll_src: PLL clock definition.

typedef enum _clock_main_clk_src clock_main_clk_src_t: Main clock source definition.

typedef struct _clock_sys_pll clock_sys_pll_t: PLL configuration structure.

volatile uint32_t g_Ext_Clk_Freq

external clock frequency.

This variable is used to store the external clock frequency which is include external oscillator clock and external clk in clock frequency value, it is set by CLOCK_InitExtClkin when CLK IN is used as external clock or by CLOCK_InitSysOsc when external oscillator is used as external clock ,and it is returned by CLOCK_GetExtClkFreq.

FSL_CLOCK_DRIVER_VERSION: CLOCK driver version 2.3.3.

SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY

g_Lp_Osc_Freq

Low power oscilltor clock frequency.

Definition for the low power oscillator frequency which is 1 Mhz at default, and it is returned by CLOCK_GetLpOscFreq.

CLOCK_FRO_SETTING_API_ROM_ADDRESS: FRO clock setting API address in ROM.

CLOCK_FAIM_BASE: FAIM base address.

ADC_CLOCKS: Clock ip name array for ADC.

ACMP_CLOCKS: Clock ip name array for ACMP.

SWM_CLOCKS: Clock ip name array for SWM.

ROM_CLOCKS: Clock ip name array for ROM.

SRAM_CLOCKS: Clock ip name array for SRAM.

IOCON_CLOCKS: Clock ip name array for IOCON.

GPIO_CLOCKS: Clock ip name array for GPIO.

GPIO_INT_CLOCKS: Clock ip name array for GPIO_INT.

DMA_CLOCKS: Clock ip name array for DMA.

CRC_CLOCKS: Clock ip name array for CRC.

WWDT_CLOCKS: Clock ip name array for WWDT.

I2C_CLOCKS: Clock ip name array for I2C.

USART_CLOCKS: Clock ip name array for I2C.

SPI_CLOCKS: Clock ip name array for SPI.

MRT_CLOCKS: Clock ip name array for MRT.

WKT_CLOCKS: Clock ip name array for WKT.

FTM_CLOCKS: Clock ip name array for FLEXTMR.

I3C_CLOCKS: Clock ip name array for I3C.

CLK_GATE_DEFINE(reg, bit): Internal used Clock definition only.

CLK_GATE_GET_REG(x)

CLK_GATE_GET_BITS_SHIFT(x)

CLK_MUX_DEFINE(reg, mux)

CLK_MUX_GET_REG(x)

CLK_MUX_GET_MUX(x)

CLK_MAIN_CLK_MUX_DEFINE(preMux, mux)

CLK_MAIN_CLK_MUX_GET_PRE_MUX(x)

CLK_MAIN_CLK_MUX_GET_MUX(x)

CLK_DIV_DEFINE(reg)

CLK_DIV_GET_REG(x)

CLK_WDT_OSC_DEFINE(freq, regValue)

CLK_WDT_OSC_GET_FREQ(x)

CLK_WDT_OSC_GET_REG(x)

CLK_FRG_DIV_REG_MAP(base)

CLK_FRG_MUL_REG_MAP(base)

CLK_FRG_SEL_REG_MAP(base)

SYS_AHB_CLK_CTRL0

SYS_AHB_CLK_CTRL1

static inline void CLOCK_EnableClock(clock_ip_name_t clk)

static inline void CLOCK_DisableClock(clock_ip_name_t clk)

static inline void CLOCK_Select(clock_select_t sel)

static inline void CLOCK_SetClkDivider(clock_divider_t name, uint32_t value)

static inline uint32_t CLOCK_GetClkDivider(clock_divider_t name)

static inline void CLOCK_SetCoreSysClkDiv(uint32_t value)

static inline void CLOCK_SetI3CFClkDiv(uint32_t value)

static inline void CLOCK_SetI3CTCClkDiv(uint32_t value)

static inline void CLOCK_SetI3CSClkDiv(uint32_t value)

void CLOCK_SetMainClkSrc(clock_main_clk_src_t src)

Set main clock reference source.

Parameters:

src – Refer to clock_main_clk_src_t to set the main clock source.

void CLOCK_SetFroOutClkSrc(clock_fro_src_t src)

Set FRO clock source.

Parameters:

src – Please refer to _clock_fro_src definition.

static inline void CLOCK_SetFRGClkMul(uint32_t *base, uint32_t mul)

void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq)

Set the flash wait states for the input freuqency.

Parameters:

iFreq – : Input frequency

uint32_t CLOCK_GetFRG0ClkFreq(void)

Return Frequency of FRG0 Clock.

Returns:: Frequency of FRG0 Clock.

uint32_t CLOCK_GetFRG1ClkFreq(void)

Return Frequency of FRG1 Clock.

Returns:: Frequency of FRG1 Clock.

uint32_t CLOCK_GetMainClkFreq(void)

Return Frequency of Main Clock.

Returns:: Frequency of Main Clock.

uint32_t CLOCK_GetFroFreq(void)

Return Frequency of FRO.

Returns:: Frequency of FRO.

static inline uint32_t CLOCK_GetCoreSysClkFreq(void)

Return Frequency of core.

Returns:: Frequency of core.

uint32_t CLOCK_GetClockOutClkFreq(void)

Return Frequency of ClockOut.

Returns:: Frequency of ClockOut

uint32_t CLOCK_GetUart0ClkFreq(void)

Get UART0 frequency.

Return values:: UART0 – frequency value.

uint32_t CLOCK_GetUart1ClkFreq(void)

Get UART1 frequency.

Return values:: UART1 – frequency value.

uint32_t CLOCK_GetUart2ClkFreq(void)

Get UART2 frequency.

Return values:: UART2 – frequency value.

uint32_t CLOCK_GetUart3ClkFreq(void)

Get UART3 frequency.

Return values:: UART3 – frequency value.

uint32_t CLOCK_GetUart4ClkFreq(void)

Get UART4 frequency.

Return values:: UART4 – frequency value.

uint32_t CLOCK_GetI3cClkFreq(void)

Get I3C frequency.

Return values:: I3C – frequency value.

uint32_t CLOCK_GetLpOscClkFreq(void)

Get LP_OSC frequency.

Return values:: LP_OSC – frequency value.

uint32_t CLOCK_GetFreq(clock_name_t clockName)

Return Frequency of selected clock.

Returns:: Frequency of selected clock

uint32_t CLOCK_GetSystemPLLInClockRate(void)

Return System PLL input clock rate.

Returns:: System PLL input clock rate

static inline uint32_t CLOCK_GetSystemPLLFreq(void)

Return Frequency of System PLL.

Returns:: Frequency of PLL

static inline uint32_t CLOCK_GetLpOscFreq(void)

Get low power OSC frequency.

Return values:: low – power OSC frequency value.

static inline uint32_t CLOCK_GetExtClkFreq(void)

Get external clock frequency.

Return values:: external – clock frequency value.

void CLOCK_InitSystemPll(const clock_sys_pll_t *config)

System PLL initialize.

Parameters:

config – System PLL configurations.

static inline void CLOCK_DenitSystemPll(void): System PLL Deinitialize.

bool CLOCK_SetFRG0ClkFreq(uint32_t freq)

Set FRG0 output frequency.

Parameters:

freq – Target output frequency, freq < input and (input / freq) < 2 should be satisfy.

Return values:

true – - successfully, false - input argument is invalid.

bool CLOCK_SetFRG1ClkFreq(uint32_t freq)

Set FRG1 output frequency.

Parameters:

freq – Target output frequency, freq < input and (input / freq) < 2 should be satisfy.

Return values:

true – - successfully, false - input argument is invalid.

void CLOCK_InitExtClkin(uint32_t clkInFreq)

Init external CLK IN, select the CLKIN as the external clock source.

Parameters:

clkInFreq – external clock in frequency.

void CLOCK_InitSysOsc(uint32_t oscFreq)

Init SYS OSC.

Parameters:

oscFreq – oscillator frequency value.

void CLOCK_InitXtalin(uint32_t xtalInFreq)

XTALIN init function system oscillator is bypassed, sys_osc_clk is fed driectly from the XTALIN.

Parameters:

xtalInFreq – XTALIN frequency value

Returns:

Frequency of PLL

static inline void CLOCK_DeinitSysOsc(void): Deinit SYS OSC.

static inline void CLOCK_SetFroOscFreq(clock_fro_osc_freq_t freq)

Set FRO oscillator output frequency. Initialize the FRO clock to given frequency (36, 48 or 60 MHz).

Parameters:

freq – Please refer to clock_fro_osc_freq_t definition, frequency must be one of 36000, 48000 or 60000 KHz.

uint32_t targetFreq: System pll fclk output frequency, the output frequency should be lower than 100MHZ

clock_sys_pll_src src: System pll clock source

struct _clock_sys_pll: #include <fsl_clock.h>

PLL configuration structure.

CRC: Cyclic Redundancy Check Driver

FSL_CRC_DRIVER_VERSION

CRC driver version. Version 2.1.1.

Current version: 2.1.1

Change log:

Version 2.0.0
- initial version
Version 2.0.1
- add explicit type cast when writing to WR_DATA
Version 2.0.2
- Fix MISRA issue
Version 2.1.0
- Add CRC_WriteSeed function
Version 2.1.1
- Fix MISRA issue

enum _crc_polynomial

CRC polynomials to use.

Values:

enumerator kCRC_Polynomial_CRC_CCITT: x^16+x^12+x^5+1

enumerator kCRC_Polynomial_CRC_16: x^16+x^15+x^2+1

enumerator kCRC_Polynomial_CRC_32: x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1

typedef enum _crc_polynomial crc_polynomial_t: CRC polynomials to use.

typedef struct _crc_config crc_config_t

CRC protocol configuration.

This structure holds the configuration for the CRC protocol.

void CRC_Init(CRC_Type *base, const crc_config_t *config)

Enables and configures the CRC peripheral module.

This functions enables the CRC peripheral clock in the LPC SYSCON block. It also configures the CRC engine and starts checksum computation by writing the seed.

Parameters:

base – CRC peripheral address.
config – CRC module configuration structure.

static inline void CRC_Deinit(CRC_Type *base)

Disables the CRC peripheral module.

This functions disables the CRC peripheral clock in the LPC SYSCON block.

Parameters:

base – CRC peripheral address.

void CRC_Reset(CRC_Type *base)

resets CRC peripheral module.

Parameters:

base – CRC peripheral address.

void CRC_WriteSeed(CRC_Type *base, uint32_t seed)

Write seed to CRC peripheral module.

Parameters:

base – CRC peripheral address.
seed – CRC Seed value.

void CRC_GetDefaultConfig(crc_config_t *config)

Loads default values to CRC protocol configuration structure.

Loads default values to CRC protocol configuration structure. The default values are:

config->polynomial = kCRC_Polynomial_CRC_CCITT;
config->reverseIn = false;
config->complementIn = false;
config->reverseOut = false;
config->complementOut = false;
config->seed = 0xFFFFU;

Parameters:

config – CRC protocol configuration structure

void CRC_GetConfig(CRC_Type *base, crc_config_t *config)

Loads actual values configured in CRC peripheral to CRC protocol configuration structure.

The values, including seed, can be used to resume CRC calculation later.

Parameters:

base – CRC peripheral address.
config – CRC protocol configuration structure

void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)

Writes data to the CRC module.

Writes input data buffer bytes to CRC data register.

Parameters:

base – CRC peripheral address.
data – Input data stream, MSByte in data[0].
dataSize – Size of the input data buffer in bytes.

static inline uint32_t CRC_Get32bitResult(CRC_Type *base)

Reads 32-bit checksum from the CRC module.

Reads CRC data register.

Parameters:

base – CRC peripheral address.

Returns:

final 32-bit checksum, after configured bit reverse and complement operations.

static inline uint16_t CRC_Get16bitResult(CRC_Type *base)

Reads 16-bit checksum from the CRC module.

Reads CRC data register.

Parameters:

base – CRC peripheral address.

Returns:

final 16-bit checksum, after configured bit reverse and complement operations.

CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT: Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default.

struct _crc_config

#include <fsl_crc.h>

CRC protocol configuration.

This structure holds the configuration for the CRC protocol.

Public Members

crc_polynomial_t polynomial: CRC polynomial.

bool reverseIn: Reverse bits on input.

bool complementIn: Perform 1’s complement on input.

bool reverseOut: Reverse bits on output.

bool complementOut: Perform 1’s complement on output.

uint32_t seed: Starting checksum value.

CTIMER: Standard counter/timers

void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)

Ungates the clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application before using the driver.

Parameters:

base – Ctimer peripheral base address
config – Pointer to the user configuration structure.

void CTIMER_Deinit(CTIMER_Type *base)

Gates the timer clock.

Parameters:

base – Ctimer peripheral base address

void CTIMER_GetDefaultConfig(ctimer_config_t *config)

Fills in the timers configuration structure with the default settings.

The default values are:

config->mode = kCTIMER_TimerMode;
config->input = kCTIMER_Capture_0;
config->prescale = 0;

Parameters:

config – Pointer to the user configuration structure.

status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, const ctimer_match_t pwmPeriodChannel, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt)

Configures the PWM signal parameters.

Enables PWM mode on the match channel passed in and will then setup the match value and other match parameters to generate a PWM signal. This function can manually assign the specified channel to set the PWM cycle.

Note

When setting PWM output from multiple output pins, all should use the same PWM period

Parameters:

base – Ctimer peripheral base address
pwmPeriodChannel – Specify the channel to control the PWM period
matchChannel – Match pin to be used to output the PWM signal
pwmPeriod – PWM period match value
pulsePeriod – Pulse width match value
enableInt – Enable interrupt when the timer value reaches the match value of the PWM pulse, if it is 0 then no interrupt will be generated.

Returns:

kStatus_Success on success kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle If PWM pulse width register value is larger than 0xFFFFFFFF.

status_t CTIMER_SetupPwm(CTIMER_Type *base, const ctimer_match_t pwmPeriodChannel, ctimer_match_t matchChannel, uint8_t dutyCyclePercent, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz, bool enableInt)

Configures the PWM signal parameters.

Enables PWM mode on the match channel passed in and will then setup the match value and other match parameters to generate a PWM signal. This function can manually assign the specified channel to set the PWM cycle.

Note

When setting PWM output from multiple output pins, all should use the same PWM frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution.

Parameters:

base – Ctimer peripheral base address
pwmPeriodChannel – Specify the channel to control the PWM period
matchChannel – Match pin to be used to output the PWM signal
dutyCyclePercent – PWM pulse width; the value should be between 0 to 100
pwmFreq_Hz – PWM signal frequency in Hz
srcClock_Hz – Timer counter clock in Hz
enableInt – Enable interrupt when the timer value reaches the match value of the PWM pulse, if it is 0 then no interrupt will be generated.

static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod)

Updates the pulse period of an active PWM signal.

Parameters:

base – Ctimer peripheral base address
matchChannel – Match pin to be used to output the PWM signal
pulsePeriod – New PWM pulse width match value

status_t CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, const ctimer_match_t pwmPeriodChannel, ctimer_match_t matchChannel, uint8_t dutyCyclePercent)

Updates the duty cycle of an active PWM signal.

Note

Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. This function can manually assign the specified channel to set the PWM cycle.

Parameters:

base – Ctimer peripheral base address
pwmPeriodChannel – Specify the channel to control the PWM period
matchChannel – Match pin to be used to output the PWM signal
dutyCyclePercent – New PWM pulse width; the value should be between 0 to 100

Returns:

kStatus_Success on success kStatus_Fail If PWM pulse width register value is larger than 0xFFFFFFFF.

static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)

Enables the selected Timer interrupts.

Parameters:

base – Ctimer peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration ctimer_interrupt_enable_t

static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)

Disables the selected Timer interrupts.

Parameters:

base – Ctimer peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration ctimer_interrupt_enable_t

static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)

Gets the enabled Timer interrupts.

Parameters:

base – Ctimer peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration ctimer_interrupt_enable_t

static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base)

Gets the Timer status flags.

Parameters:

base – Ctimer peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration ctimer_status_flags_t

static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask)

Clears the Timer status flags.

Parameters:

base – Ctimer peripheral base address
mask – The status flags to clear. This is a logical OR of members of the enumeration ctimer_status_flags_t

static inline void CTIMER_StartTimer(CTIMER_Type *base)

Starts the Timer counter.

Parameters:

base – Ctimer peripheral base address

static inline void CTIMER_StopTimer(CTIMER_Type *base)

Stops the Timer counter.

Parameters:

base – Ctimer peripheral base address

FSL_CTIMER_DRIVER_VERSION: Version 2.3.3

enum _ctimer_capture_channel

List of Timer capture channels.

Values:

enumerator kCTIMER_Capture_0: Timer capture channel 0

enumerator kCTIMER_Capture_1: Timer capture channel 1

enumerator kCTIMER_Capture_2: Timer capture channel 2

enum _ctimer_capture_edge

List of capture edge options.

Values:

enumerator kCTIMER_Capture_RiseEdge: Capture on rising edge

enumerator kCTIMER_Capture_FallEdge: Capture on falling edge

enumerator kCTIMER_Capture_BothEdge: Capture on rising and falling edge

enum _ctimer_match

List of Timer match registers.

Values:

enumerator kCTIMER_Match_0: Timer match register 0

enumerator kCTIMER_Match_1: Timer match register 1

enumerator kCTIMER_Match_2: Timer match register 2

enumerator kCTIMER_Match_3: Timer match register 3

enum _ctimer_external_match

List of external match.

Values:

enumerator kCTIMER_External_Match_0: External match 0

enumerator kCTIMER_External_Match_1: External match 1

enumerator kCTIMER_External_Match_2: External match 2

enumerator kCTIMER_External_Match_3: External match 3

enum _ctimer_match_output_control

List of output control options.

Values:

enumerator kCTIMER_Output_NoAction: No action is taken

enumerator kCTIMER_Output_Clear: Clear the EM bit/output to 0

enumerator kCTIMER_Output_Set: Set the EM bit/output to 1

enumerator kCTIMER_Output_Toggle: Toggle the EM bit/output

enum _ctimer_timer_mode

List of Timer modes.

Values:

enumerator kCTIMER_TimerMode

enumerator kCTIMER_IncreaseOnRiseEdge

enumerator kCTIMER_IncreaseOnFallEdge

enumerator kCTIMER_IncreaseOnBothEdge

enum _ctimer_interrupt_enable

List of Timer interrupts.

Values:

enumerator kCTIMER_Match0InterruptEnable: Match 0 interrupt

enumerator kCTIMER_Match1InterruptEnable: Match 1 interrupt

enumerator kCTIMER_Match2InterruptEnable: Match 2 interrupt

enumerator kCTIMER_Match3InterruptEnable: Match 3 interrupt

enumerator kCTIMER_Capture0InterruptEnable: Capture 0 interrupt

enumerator kCTIMER_Capture1InterruptEnable: Capture 1 interrupt

enumerator kCTIMER_Capture2InterruptEnable: Capture 2 interrupt

enum _ctimer_status_flags

List of Timer flags.

Values:

enumerator kCTIMER_Match0Flag: Match 0 interrupt flag

enumerator kCTIMER_Match1Flag: Match 1 interrupt flag

enumerator kCTIMER_Match2Flag: Match 2 interrupt flag

enumerator kCTIMER_Match3Flag: Match 3 interrupt flag

enumerator kCTIMER_Capture0Flag: Capture 0 interrupt flag

enumerator kCTIMER_Capture1Flag: Capture 1 interrupt flag

enumerator kCTIMER_Capture2Flag: Capture 2 interrupt flag

enum ctimer_callback_type_t

Callback type when registering for a callback. When registering a callback an array of function pointers is passed the size could be 1 or 8, the callback type will tell that.

Values:

enumerator kCTIMER_SingleCallback: Single Callback type where there is only one callback for the timer. based on the status flags different channels needs to be handled differently

enumerator kCTIMER_MultipleCallback: Multiple Callback type where there can be 8 valid callbacks, one per channel. for both match/capture

typedef enum _ctimer_capture_channel ctimer_capture_channel_t: List of Timer capture channels.

typedef enum _ctimer_capture_edge ctimer_capture_edge_t: List of capture edge options.

typedef enum _ctimer_match ctimer_match_t: List of Timer match registers.

typedef enum _ctimer_external_match ctimer_external_match_t: List of external match.

typedef enum _ctimer_match_output_control ctimer_match_output_control_t: List of output control options.

typedef enum _ctimer_timer_mode ctimer_timer_mode_t: List of Timer modes.

typedef enum _ctimer_interrupt_enable ctimer_interrupt_enable_t: List of Timer interrupts.

typedef enum _ctimer_status_flags ctimer_status_flags_t: List of Timer flags.

typedef void (*ctimer_callback_t)(uint32_t flags)

typedef struct _ctimer_match_config ctimer_match_config_t

Match configuration.

This structure holds the configuration settings for each match register.

typedef struct _ctimer_config ctimer_config_t

Timer configuration structure.

This structure holds the configuration settings for the Timer peripheral. To initialize this structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a pointer to the configuration structure instance.

The configuration structure can be made constant so as to reside in flash.

void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config)

Setup the match register.

User configuration is used to setup the match value and action to be taken when a match occurs.

Parameters:

base – Ctimer peripheral base address
matchChannel – Match register to configure
config – Pointer to the match configuration structure

uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel)

Get the status of output match.

This function gets the status of output MAT, whether or not this output is connected to a pin. This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.

Parameters:

base – Ctimer peripheral base address
matchChannel – External match channel, user can obtain the status of multiple match channels at the same time by using the logic of “|” enumeration ctimer_external_match_t

Returns:

The mask of external match channel status flags. Users need to use the _ctimer_external_match type to decode the return variables.

void CTIMER_SetupCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, ctimer_capture_edge_t edge, bool enableInt)

Setup the capture.

Parameters:

base – Ctimer peripheral base address
capture – Capture channel to configure
edge – Edge on the channel that will trigger a capture
enableInt – Flag to enable channel interrupts, if enabled then the registered call back is called upon capture

static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base)

Get the timer count value from TC register.

Parameters:

base – Ctimer peripheral base address.

Returns:

return the timer count value.

void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type)

Register callback.

Parameters:

base – Ctimer peripheral base address
cb_func – callback function
cb_type – callback function type, singular or multiple

static inline void CTIMER_Reset(CTIMER_Type *base)

Reset the counter.

The timer counter and prescale counter are reset on the next positive edge of the APB clock.

Parameters:

base – Ctimer peripheral base address

static inline void CTIMER_SetPrescale(CTIMER_Type *base, uint32_t prescale)

Setup the timer prescale value.

Specifies the maximum value for the Prescale Counter.

Parameters:

base – Ctimer peripheral base address
prescale – Prescale value

static inline uint32_t CTIMER_GetCaptureValue(CTIMER_Type *base, ctimer_capture_channel_t capture)

Get capture channel value.

Get the counter/timer value on the corresponding capture channel.

Parameters:

base – Ctimer peripheral base address
capture – Select capture channel

Returns:

The timer count capture value.

static inline void CTIMER_EnableResetMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable)

Enable reset match channel.

Set the specified match channel reset operation.

Parameters:

base – Ctimer peripheral base address
match – match channel used
enable – Enable match channel reset operation.

static inline void CTIMER_EnableStopMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable)

Enable stop match channel.

Set the specified match channel stop operation.

Parameters:

base – Ctimer peripheral base address.
match – match channel used.
enable – Enable match channel stop operation.

static inline void CTIMER_EnableRisingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable)

Enable capture channel rising edge.

Sets the specified capture channel for rising edge capture.

Parameters:

base – Ctimer peripheral base address.
capture – capture channel used.
enable – Enable rising edge capture.

static inline void CTIMER_EnableFallingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable)

Enable capture channel falling edge.

Sets the specified capture channel for falling edge capture.

Parameters:

base – Ctimer peripheral base address.
capture – capture channel used.
enable – Enable falling edge capture.

struct _ctimer_match_config

#include <fsl_ctimer.h>

Match configuration.

This structure holds the configuration settings for each match register.

Public Members

uint32_t matchValue: This is stored in the match register

bool enableCounterReset: true: Match will reset the counter false: Match will not reser the counter

bool enableCounterStop: true: Match will stop the counter false: Match will not stop the counter

ctimer_match_output_control_t outControl: Action to be taken on a match on the EM bit/output

bool outPinInitState: Initial value of the EM bit/output

bool enableInterrupt: true: Generate interrupt upon match false: Do not generate interrupt on match

struct _ctimer_config

#include <fsl_ctimer.h>

Timer configuration structure.

This structure holds the configuration settings for the Timer peripheral. To initialize this structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a pointer to the configuration structure instance.

The configuration structure can be made constant so as to reside in flash.

Public Members

ctimer_timer_mode_t mode: Timer mode

ctimer_capture_channel_t input: Input channel to increment the timer, used only in timer modes that rely on this input signal to increment TC

uint32_t prescale: Prescale value

DMA: Direct Memory Access Controller Driver

void DMA_Init(DMA_Type *base)

Initializes DMA peripheral.

This function enable the DMA clock, set descriptor table and enable DMA peripheral.

Parameters:

base – DMA peripheral base address.

void DMA_Deinit(DMA_Type *base)

Deinitializes DMA peripheral.

This function gates the DMA clock.

Parameters:

base – DMA peripheral base address.

void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr)

Install DMA descriptor memory.

This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has a default DMA descriptor buffer, but it support one DMA descriptor for one channel only.

Parameters:

base – DMA base address.
addr – DMA descriptor address

static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel)

Return whether DMA channel is processing transfer.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.

Returns:

True for active state, false otherwise.

static inline bool DMA_ChannelIsBusy(DMA_Type *base, uint32_t channel)

Return whether DMA channel is busy.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.

Returns:

True for busy state, false otherwise.

static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel)

Enables the interrupt source for the DMA transfer.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.

static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel)

Disables the interrupt source for the DMA transfer.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.

static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel)

Enable DMA channel.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.

static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel)

Disable DMA channel.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.

static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel)

Set PERIPHREQEN of channel configuration register.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.

static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel)

Get PERIPHREQEN value of channel configuration register.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.

Returns:

True for enabled PeriphRq, false for disabled.

void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger)

Set trigger settings of DMA channel.

Deprecated:: Do not use this function. It has been superceded by DMA_SetChannelConfig.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.
trigger – trigger configuration.

void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph)

set channel config.

This function provide a interface to configure channel configuration reisters.

Parameters:

base – DMA base address.
channel – DMA channel number.
trigger – channel configurations structure.
isPeriph – true is periph request, false is not.

static inline uint32_t DMA_SetChannelXferConfig(bool reload, bool clrTrig, bool intA, bool intB, uint8_t width, uint8_t srcInc, uint8_t dstInc, uint32_t bytes)

DMA channel xfer transfer configurations.

Parameters:

reload – true is reload link descriptor after current exhaust, false is not
clrTrig – true is clear trigger status, wait software trigger, false is not
intA – enable interruptA
intB – enable interruptB
width – transfer width
srcInc – source address interleave size
dstInc – destination address interleave size
bytes – transfer bytes

Returns:

The vaule of xfer config

uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)

Gets the remaining bytes of the current DMA descriptor transfer.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.

Returns:

The number of bytes which have not been transferred yet.

static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority)

Set priority of channel configuration register.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.
priority – Channel priority value.

static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel)

Get priority of channel configuration register.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.

Returns:

Channel priority value.

static inline void DMA_SetChannelConfigValid(DMA_Type *base, uint32_t channel)

Set channel configuration valid.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.

static inline void DMA_DoChannelSoftwareTrigger(DMA_Type *base, uint32_t channel)

Do software trigger for the channel.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.

static inline void DMA_LoadChannelTransferConfig(DMA_Type *base, uint32_t channel, uint32_t xfer)

Load channel transfer configurations.

Parameters:

base – DMA peripheral base address.
channel – DMA channel number.
xfer – transfer configurations.

void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc)

Create application specific DMA descriptor to be used in a chain in transfer.

Deprecated:: Do not use this function. It has been superceded by DMA_SetupDescriptor.

Parameters:

desc – DMA descriptor address.
xfercfg – Transfer configuration for DMA descriptor.
srcAddr – Address of last item to transmit
dstAddr – Address of last item to receive.
nextDesc – Address of next descriptor in chain.

void DMA_SetupDescriptor(dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc)

setup dma descriptor

Note: This function do not support configure wrap descriptor.

Parameters:

desc – DMA descriptor address.
xfercfg – Transfer configuration for DMA descriptor.
srcStartAddr – Start address of source address.
dstStartAddr – Start address of destination address.
nextDesc – Address of next descriptor in chain.

void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc, dma_burst_wrap_t wrapType, uint32_t burstSize)

setup dma channel descriptor

Note: This function support configure wrap descriptor.

Parameters:

desc – DMA descriptor address.
xfercfg – Transfer configuration for DMA descriptor.
srcStartAddr – Start address of source address.
dstStartAddr – Start address of destination address.
nextDesc – Address of next descriptor in chain.
wrapType – burst wrap type.
burstSize – burst size, reference _dma_burst_size.

void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor)

load channel transfer decriptor.

This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA transfer, the head descriptor table is defined in DMA driver, it is useful for the case:

for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly and then call this api to load the configured descriptor to driver descriptor table.

DMA_Init(DMA0);
DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL);
DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL);
DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc);
DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL);
while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL))
{}

Parameters:

base – DMA base address.
channel – DMA channel.
descriptor – configured DMA descriptor.

void DMA_AbortTransfer(dma_handle_t *handle)

Abort running transfer by handle.

This function aborts DMA transfer specified by handle.

Parameters:

handle – DMA handle pointer.

void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel)

Creates the DMA handle.

This function is called if using transaction API for DMA. This function initializes the internal state of DMA handle.

Parameters:

handle – DMA handle pointer. The DMA handle stores callback function and parameters.
base – DMA peripheral base address.
channel – DMA channel number.

void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData)

Installs a callback function for the DMA transfer.

This callback is called in DMA IRQ handler. Use the callback to do something after the current major loop transfer completes.

Parameters:

handle – DMA handle pointer.
callback – DMA callback function pointer.
userData – Parameter for callback function.

void DMA_PrepareTransfer(dma_transfer_config_t *config, void *srcAddr, void *dstAddr, uint32_t byteWidth, uint32_t transferBytes, dma_transfer_type_t type, void *nextDesc)

Prepares the DMA transfer structure.

Deprecated:: Do not use this function. It has been superceded by DMA_PrepareChannelTransfer. This function prepares the transfer configuration structure according to the user input.

Note

The data address and the data width must be consistent. For example, if the SRC is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in source address error(SAE).

Parameters:

config – The user configuration structure of type dma_transfer_t.
srcAddr – DMA transfer source address.
dstAddr – DMA transfer destination address.
byteWidth – DMA transfer destination address width(bytes).
transferBytes – DMA transfer bytes to be transferred.
type – DMA transfer type.
nextDesc – Chain custom descriptor to transfer.

void DMA_PrepareChannelTransfer(dma_channel_config_t *config, void *srcStartAddr, void *dstStartAddr, uint32_t xferCfg, dma_transfer_type_t type, dma_channel_trigger_t *trigger, void *nextDesc)

Prepare channel transfer configurations.

This function used to prepare channel transfer configurations.

Parameters:

config – Pointer to DMA channel transfer configuration structure.
srcStartAddr – source start address.
dstStartAddr – destination start address.
xferCfg – xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value.
type – transfer type.
trigger – DMA channel trigger configurations.
nextDesc – address of next descriptor.

status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config)

Submits the DMA transfer request.

Deprecated:: Do not use this function. It has been superceded by DMA_SubmitChannelTransfer.

This function submits the DMA transfer request according to the transfer configuration structure. If the user submits the transfer request repeatedly, this function packs an unprocessed request as a TCD and enables scatter/gather feature to process it in the next time.

Parameters:

handle – DMA handle pointer.
config – Pointer to DMA transfer configuration structure.

Return values:

kStatus_DMA_Success – It means submit transfer request succeed.
kStatus_DMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.
kStatus_DMA_Busy – It means the given channel is busy, need to submit request later.

void DMA_SubmitChannelTransferParameter(dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc)

Submit channel transfer paramter directly.

This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table is defined in DMA driver, it is useful for the case:

for the single transfer, application doesn’t need to allocate descriptor table, the head descriptor can be used for it.

   DMA_SetChannelConfig(base, channel, trigger, isPeriph);
   DMA_CreateHandle(handle, base, channel)
   DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc,
bytes), srcStartAddr, dstStartAddr, NULL);
   DMA_StartTransfer(handle)

for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is required, then application should prepare three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.

   define link descriptor table in application with macro
   DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]);

   DMA_SetupDescriptor(nextDesc0,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
srcStartAddr, dstStartAddr, nextDesc1);
   DMA_SetupDescriptor(nextDesc1,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
srcStartAddr, dstStartAddr, nextDesc2);
   DMA_SetupDescriptor(nextDesc2,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
srcStartAddr, dstStartAddr, NULL);
   DMA_SetChannelConfig(base, channel, trigger, isPeriph);
   DMA_CreateHandle(handle, base, channel)
   DMA_SubmitChannelTransferParameter(handle, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc,
bytes), srcStartAddr, dstStartAddr, nextDesc0);
   DMA_StartTransfer(handle);

Parameters:

handle – Pointer to DMA handle.
xferCfg – xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value.
srcStartAddr – source start address.
dstStartAddr – destination start address.
nextDesc – address of next descriptor.

void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descriptor)

Submit channel descriptor.

This function used to configue channel head descriptor that is used to start DMA transfer, the head descriptor table is defined in DMA driver, this functiono is typical for the ping pong case:

for the ping pong case, application should responsible for the descriptor, for example, application should prepare two descriptor table with macro.

   define link descriptor table in application with macro
   DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]);

   DMA_SetupDescriptor(nextDesc0,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
srcStartAddr, dstStartAddr, nextDesc1);
   DMA_SetupDescriptor(nextDesc1,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
srcStartAddr, dstStartAddr, nextDesc0);
   DMA_SetChannelConfig(base, channel, trigger, isPeriph);
   DMA_CreateHandle(handle, base, channel)
   DMA_SubmitChannelDescriptor(handle,  nextDesc0);
   DMA_StartTransfer(handle);

Parameters:

handle – Pointer to DMA handle.
descriptor – descriptor to submit.

status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config)

Submits the DMA channel transfer request.

This function submits the DMA transfer request according to the transfer configuration structure. If the user submits the transfer request repeatedly, this function packs an unprocessed request as a TCD and enables scatter/gather feature to process it in the next time. It is used for the case:

for the single transfer, application doesn’t need to allocate descriptor table, the head descriptor can be used for it.

DMA_CreateHandle(handle, base, channel)
DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,NULL);
DMA_SubmitChannelTransfer(handle, config)
DMA_StartTransfer(handle)

for the linked transfer, application should responsible for link descriptor, for example, if 4 transfer is required, then application should prepare three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.

   define link descriptor table in application with macro
   DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc);
   DMA_SetupDescriptor(nextDesc0,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
srcStartAddr, dstStartAddr, nextDesc1);
   DMA_SetupDescriptor(nextDesc1,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
srcStartAddr, dstStartAddr, nextDesc2);
   DMA_SetupDescriptor(nextDesc2,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
srcStartAddr, dstStartAddr, NULL);
   DMA_CreateHandle(handle, base, channel)
   DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0);
   DMA_SubmitChannelTransfer(handle, config)
   DMA_StartTransfer(handle)

for the ping pong case, application should responsible for link descriptor, for example, application should prepare two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor.

   define link descriptor table in application with macro
   DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc);

   DMA_SetupDescriptor(nextDesc0,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
srcStartAddr, dstStartAddr, nextDesc1);
   DMA_SetupDescriptor(nextDesc1,  DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes),
srcStartAddr, dstStartAddr, nextDesc0);
   DMA_CreateHandle(handle, base, channel)
   DMA_PrepareChannelTransfer(config,srcStartAddr,dstStartAddr,xferCfg,type,trigger,nextDesc0);
   DMA_SubmitChannelTransfer(handle, config)
   DMA_StartTransfer(handle)

Parameters:

handle – DMA handle pointer.
config – Pointer to DMA transfer configuration structure.

Return values:

kStatus_DMA_Success – It means submit transfer request succeed.
kStatus_DMA_QueueFull – It means TCD queue is full. Submit transfer request is not allowed.
kStatus_DMA_Busy – It means the given channel is busy, need to submit request later.

void DMA_StartTransfer(dma_handle_t *handle)

DMA start transfer.

This function enables the channel request. User can call this function after submitting the transfer request It will trigger transfer start with software trigger only when hardware trigger is not used.

Parameters:

handle – DMA handle pointer.

void DMA_IRQHandle(DMA_Type *base)

DMA IRQ handler for descriptor transfer complete.

This function clears the channel major interrupt flag and call the callback function if it is not NULL.

Parameters:

base – DMA base address.

FSL_DMA_DRIVER_VERSION

DMA driver version.

Version 2.5.3.

_dma_transfer_status DMA transfer status

Values:

enumerator kStatus_DMA_Busy: Channel is busy and can’t handle the transfer request.

_dma_addr_interleave_size dma address interleave size

Values:

enumerator kDMA_AddressInterleave0xWidth: dma source/destination address no interleave

enumerator kDMA_AddressInterleave1xWidth: dma source/destination address interleave 1xwidth

enumerator kDMA_AddressInterleave2xWidth: dma source/destination address interleave 2xwidth

enumerator kDMA_AddressInterleave4xWidth: dma source/destination address interleave 3xwidth

_dma_transfer_width dma transfer width

Values:

enumerator kDMA_Transfer8BitWidth: dma channel transfer bit width is 8 bit

enumerator kDMA_Transfer16BitWidth: dma channel transfer bit width is 16 bit

enumerator kDMA_Transfer32BitWidth: dma channel transfer bit width is 32 bit

enum _dma_priority

DMA channel priority.

Values:

enumerator kDMA_ChannelPriority0: Highest channel priority - priority 0

enumerator kDMA_ChannelPriority1: Channel priority 1

enumerator kDMA_ChannelPriority2: Channel priority 2

enumerator kDMA_ChannelPriority3: Channel priority 3

enumerator kDMA_ChannelPriority4: Channel priority 4

enumerator kDMA_ChannelPriority5: Channel priority 5

enumerator kDMA_ChannelPriority6: Channel priority 6

enumerator kDMA_ChannelPriority7: Lowest channel priority - priority 7

enum _dma_int

DMA interrupt flags.

Values:

enumerator kDMA_IntA: DMA interrupt flag A

enumerator kDMA_IntB: DMA interrupt flag B

enumerator kDMA_IntError: DMA interrupt flag error

enum _dma_trigger_type

DMA trigger type.

Values:

enumerator kDMA_NoTrigger: Trigger is disabled

enumerator kDMA_LowLevelTrigger: Low level active trigger

enumerator kDMA_HighLevelTrigger: High level active trigger

enumerator kDMA_FallingEdgeTrigger: Falling edge active trigger

enumerator kDMA_RisingEdgeTrigger: Rising edge active trigger

_dma_burst_size DMA burst size

Values:

enumerator kDMA_BurstSize1: burst size 1 transfer

enumerator kDMA_BurstSize2: burst size 2 transfer

enumerator kDMA_BurstSize4: burst size 4 transfer

enumerator kDMA_BurstSize8: burst size 8 transfer

enumerator kDMA_BurstSize16: burst size 16 transfer

enumerator kDMA_BurstSize32: burst size 32 transfer

enumerator kDMA_BurstSize64: burst size 64 transfer

enumerator kDMA_BurstSize128: burst size 128 transfer

enumerator kDMA_BurstSize256: burst size 256 transfer

enumerator kDMA_BurstSize512: burst size 512 transfer

enumerator kDMA_BurstSize1024: burst size 1024 transfer

enum _dma_trigger_burst

DMA trigger burst.

Values:

enumerator kDMA_SingleTransfer: Single transfer

enumerator kDMA_LevelBurstTransfer: Burst transfer driven by level trigger

enumerator kDMA_EdgeBurstTransfer1: Perform 1 transfer by edge trigger

enumerator kDMA_EdgeBurstTransfer2: Perform 2 transfers by edge trigger

enumerator kDMA_EdgeBurstTransfer4: Perform 4 transfers by edge trigger

enumerator kDMA_EdgeBurstTransfer8: Perform 8 transfers by edge trigger

enumerator kDMA_EdgeBurstTransfer16: Perform 16 transfers by edge trigger

enumerator kDMA_EdgeBurstTransfer32: Perform 32 transfers by edge trigger

enumerator kDMA_EdgeBurstTransfer64: Perform 64 transfers by edge trigger

enumerator kDMA_EdgeBurstTransfer128: Perform 128 transfers by edge trigger

enumerator kDMA_EdgeBurstTransfer256: Perform 256 transfers by edge trigger

enumerator kDMA_EdgeBurstTransfer512: Perform 512 transfers by edge trigger

enumerator kDMA_EdgeBurstTransfer1024: Perform 1024 transfers by edge trigger

enum _dma_burst_wrap

DMA burst wrapping.

Values:

enumerator kDMA_NoWrap: Wrapping is disabled

enumerator kDMA_SrcWrap: Wrapping is enabled for source

enumerator kDMA_DstWrap: Wrapping is enabled for destination

enumerator kDMA_SrcAndDstWrap: Wrapping is enabled for source and destination

enum _dma_transfer_type

DMA transfer type.

Values:

enumerator kDMA_MemoryToMemory: Transfer from memory to memory (increment source and destination)

enumerator kDMA_PeripheralToMemory: Transfer from peripheral to memory (increment only destination)

enumerator kDMA_MemoryToPeripheral: Transfer from memory to peripheral (increment only source)

enumerator kDMA_StaticToStatic: Peripheral to static memory (do not increment source or destination)

typedef struct _dma_descriptor dma_descriptor_t: DMA descriptor structure.

typedef struct _dma_xfercfg dma_xfercfg_t: DMA transfer configuration.

typedef enum _dma_priority dma_priority_t: DMA channel priority.

typedef enum _dma_int dma_irq_t: DMA interrupt flags.

typedef enum _dma_trigger_type dma_trigger_type_t: DMA trigger type.

typedef enum _dma_trigger_burst dma_trigger_burst_t: DMA trigger burst.

typedef enum _dma_burst_wrap dma_burst_wrap_t: DMA burst wrapping.

typedef enum _dma_transfer_type dma_transfer_type_t: DMA transfer type.

typedef struct _dma_channel_trigger dma_channel_trigger_t: DMA channel trigger.

typedef struct _dma_channel_config dma_channel_config_t: DMA channel trigger.

typedef struct _dma_transfer_config dma_transfer_config_t: DMA transfer configuration.

typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode): Define Callback function for DMA.

typedef struct _dma_handle dma_handle_t: DMA transfer handle structure.

DMA_MAX_TRANSFER_COUNT: DMA max transfer size.

FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x): DMA channel numbers.

FSL_FEATURE_DMA_MAX_CHANNELS

FSL_FEATURE_DMA_ALL_CHANNELS

FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE: DMA head link descriptor table align size.

DMA_ALLOCATE_HEAD_DESCRIPTORS(name, number)

DMA head descriptor table allocate macro To simplify user interface, this macro will help allocate descriptor memory, user just need to provide the name and the number for the allocate descriptor.

Parameters:

name – Allocate decriptor name.
number – Number of descriptor to be allocated.

DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(name, number)

DMA head descriptor table allocate macro at noncacheable section To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, user just need to provide the name and the number for the allocate descriptor.

Parameters:

name – Allocate decriptor name.
number – Number of descriptor to be allocated.

DMA_ALLOCATE_LINK_DESCRIPTORS(name, number)

DMA link descriptor table allocate macro To simplify user interface, this macro will help allocate descriptor memory, user just need to provide the name and the number for the allocate descriptor.

Parameters:

name – Allocate decriptor name.
number – Number of descriptor to be allocated.

DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(name, number)

DMA link descriptor table allocate macro at noncacheable section To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, user just need to provide the name and the number for the allocate descriptor.

Parameters:

name – Allocate decriptor name.
number – Number of descriptor to be allocated.

DMA_ALLOCATE_DATA_TRANSFER_BUFFER(name, width): DMA transfer buffer address need to align with the transfer width.

DMA_CHANNEL_GROUP(channel)

DMA_CHANNEL_INDEX(base, channel)

DMA_COMMON_REG_GET(base, channel, reg): DMA linked descriptor address algin size.

DMA_COMMON_CONST_REG_GET(base, channel, reg)

DMA_COMMON_REG_SET(base, channel, reg, value)

DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width)

DMA descriptor end address calculate.

Parameters:

start – start address
inc – address interleave size
bytes – transfer bytes
width – transfer width

DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes)

struct _dma_descriptor

#include <fsl_dma.h>

DMA descriptor structure.

Public Members

volatile uint32_t xfercfg: Transfer configuration

void *srcEndAddr: Last source address of DMA transfer

void *dstEndAddr: Last destination address of DMA transfer

void *linkToNextDesc: Address of next DMA descriptor in chain

struct _dma_xfercfg

#include <fsl_dma.h>

DMA transfer configuration.

Public Members

bool valid: Descriptor is ready to transfer

bool reload: Reload channel configuration register after current descriptor is exhausted

bool swtrig: Perform software trigger. Transfer if fired when ‘valid’ is set

bool clrtrig: Clear trigger

bool intA: Raises IRQ when transfer is done and set IRQA status register flag

bool intB: Raises IRQ when transfer is done and set IRQB status register flag

uint8_t byteWidth: Byte width of data to transfer

uint8_t srcInc: Increment source address by ‘srcInc’ x ‘byteWidth’

uint8_t dstInc: Increment destination address by ‘dstInc’ x ‘byteWidth’

uint16_t transferCount: Number of transfers

struct _dma_channel_trigger

#include <fsl_dma.h>

DMA channel trigger.

Public Members

dma_trigger_type_t type: Select hardware trigger as edge triggered or level triggered.

dma_trigger_burst_t burst: Select whether hardware triggers cause a single or burst transfer.

dma_burst_wrap_t wrap: Select wrap type, source wrap or dest wrap, or both.

struct _dma_channel_config

#include <fsl_dma.h>

DMA channel trigger.

Public Members

void *srcStartAddr: Source data address

void *dstStartAddr: Destination data address

void *nextDesc: Chain custom descriptor

uint32_t xferCfg: channel transfer configurations

dma_channel_trigger_t *trigger: DMA trigger type

bool isPeriph: select the request type

struct _dma_transfer_config

#include <fsl_dma.h>

DMA transfer configuration.

Public Members

uint8_t *srcAddr: Source data address

uint8_t *dstAddr: Destination data address

uint8_t *nextDesc: Chain custom descriptor

dma_xfercfg_t xfercfg: Transfer options

bool isPeriph: DMA transfer is driven by peripheral

struct _dma_handle

#include <fsl_dma.h>

DMA transfer handle structure.

Public Members

dma_callback callback: Callback function. Invoked when transfer of descriptor with interrupt flag finishes

void *userData: Callback function parameter

DMA_Type *base: DMA peripheral base address

uint8_t channel: DMA channel number

FTM: FlexTimer Driver

status_t FTM_Init(FTM_Type *base, const ftm_config_t *config)

Ungates the FTM clock and configures the peripheral for basic operation.

Note

This API should be called at the beginning of the application which is using the FTM driver. If the FTM instance has only TPM features, please use the TPM driver.

Parameters:

base – FTM peripheral base address
config – Pointer to the user configuration structure.

Returns:

kStatus_Success indicates success; Else indicates failure.

void FTM_Deinit(FTM_Type *base)

Gates the FTM clock.

Parameters:

base – FTM peripheral base address

void FTM_GetDefaultConfig(ftm_config_t *config)

Fills in the FTM configuration structure with the default settings.

The default values are:

config->prescale = kFTM_Prescale_Divide_1;
config->bdmMode = kFTM_BdmMode_0;
config->pwmSyncMode = kFTM_SoftwareTrigger;
config->reloadPoints = 0;
config->faultMode = kFTM_Fault_Disable;
config->faultFilterValue = 0;
config->deadTimePrescale = kFTM_Deadtime_Prescale_1;
config->deadTimeValue =  0;
config->extTriggers = 0;
config->chnlInitState = 0;
config->chnlPolarity = 0;
config->useGlobalTimeBase = false;
config->hwTriggerResetCount = false;
config->swTriggerResetCount = true;

Parameters:

config – Pointer to the user configuration structure.

static inline ftm_clock_prescale_t FTM_CalculateCounterClkDiv(FTM_Type *base, uint32_t counterPeriod_Hz, uint32_t srcClock_Hz)

brief Calculates the counter clock prescaler.

This function calculates the values for SC[PS] bit.

param base FTM peripheral base address param counterPeriod_Hz The desired frequency in Hz which corresponding to the time when the counter reaches the mod value param srcClock_Hz FTM counter clock in Hz

return Calculated clock prescaler value, see ftm_clock_prescale_t.

status_t FTM_SetupPwm(FTM_Type *base, const ftm_chnl_pwm_signal_param_t *chnlParams, uint8_t numOfChnls, ftm_pwm_mode_t mode, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz)

Configures the PWM signal parameters.

Call this function to configure the PWM signal period, mode, duty cycle, and edge. Use this function to configure all FTM channels that are used to output a PWM signal.

Parameters:

base – FTM peripheral base address
chnlParams – Array of PWM channel parameters to configure the channel(s)
numOfChnls – Number of channels to configure; This should be the size of the array passed in
mode – PWM operation mode, options available in enumeration ftm_pwm_mode_t
pwmFreq_Hz – PWM signal frequency in Hz
srcClock_Hz – FTM counter clock in Hz

Returns:

kStatus_Success if the PWM setup was successful kStatus_Error on failure

status_t FTM_UpdatePwmDutycycle(FTM_Type *base, ftm_chnl_t chnlNumber, ftm_pwm_mode_t currentPwmMode, uint8_t dutyCyclePercent)

Updates the duty cycle of an active PWM signal.

Parameters:

base – FTM peripheral base address
chnlNumber – The channel/channel pair number. In combined mode, this represents the channel pair number
currentPwmMode – The current PWM mode set during PWM setup
dutyCyclePercent – New PWM pulse width; The value should be between 0 to 100 0=inactive signal(0% duty cycle)… 100=active signal (100% duty cycle)

Returns:

kStatus_Success if the PWM update was successful kStatus_Error on failure

void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level)

Updates the edge level selection for a channel.

Parameters:

base – FTM peripheral base address
chnlNumber – The channel number
level – The level to be set to the ELSnB:ELSnA field; Valid values are 00, 01, 10, 11. See the Kinetis SoC reference manual for details about this field.

status_t FTM_SetupPwmMode(FTM_Type *base, const ftm_chnl_pwm_config_param_t *chnlParams, uint8_t numOfChnls, ftm_pwm_mode_t mode)

Configures the PWM mode parameters.

Call this function to configure the PWM signal mode, duty cycle in ticks, and edge. Use this function to configure all FTM channels that are used to output a PWM signal. Please note that: This API is similar with FTM_SetupPwm() API, but will not set the timer period, and this API will set channel match value in timer ticks, not period percent.

Parameters:

base – FTM peripheral base address
chnlParams – Array of PWM channel parameters to configure the channel(s)
numOfChnls – Number of channels to configure; This should be the size of the array passed in
mode – PWM operation mode, options available in enumeration ftm_pwm_mode_t

Returns:

kStatus_Success if the PWM setup was successful kStatus_Error on failure

void FTM_SetupInputCapture(FTM_Type *base, ftm_chnl_t chnlNumber, ftm_input_capture_edge_t captureMode, uint32_t filterValue)

Enables capturing an input signal on the channel using the function parameters.

When the edge specified in the captureMode argument occurs on the channel, the FTM counter is captured into the CnV register. The user has to read the CnV register separately to get this value. The filter function is disabled if the filterVal argument passed in is 0. The filter function is available only for channels 0, 1, 2, 3.

Parameters:

base – FTM peripheral base address
chnlNumber – The channel number
captureMode – Specifies which edge to capture
filterValue – Filter value, specify 0 to disable filter. Available only for channels 0-3.

void FTM_SetupOutputCompare(FTM_Type *base, ftm_chnl_t chnlNumber, ftm_output_compare_mode_t compareMode, uint32_t compareValue)

Configures the FTM to generate timed pulses.

When the FTM counter matches the value of compareVal argument (this is written into CnV reg), the channel output is changed based on what is specified in the compareMode argument.

Parameters:

base – FTM peripheral base address
chnlNumber – The channel number
compareMode – Action to take on the channel output when the compare condition is met
compareValue – Value to be programmed in the CnV register.

void FTM_SetupDualEdgeCapture(FTM_Type *base, ftm_chnl_t chnlPairNumber, const ftm_dual_edge_capture_param_t *edgeParam, uint32_t filterValue)

Configures the dual edge capture mode of the FTM.

This function sets up the dual edge capture mode on a channel pair. The capture edge for the channel pair and the capture mode (one-shot or continuous) is specified in the parameter argument. The filter function is disabled if the filterVal argument passed is zero. The filter function is available only on channels 0 and 2. The user has to read the channel CnV registers separately to get the capture values.

Parameters:

base – FTM peripheral base address
chnlPairNumber – The FTM channel pair number; options are 0, 1, 2, 3
edgeParam – Sets up the dual edge capture function
filterValue – Filter value, specify 0 to disable filter. Available only for channel pair 0 and 1.

void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask)

Enables the selected FTM interrupts.

Parameters:

base – FTM peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration ftm_interrupt_enable_t

void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask)

Disables the selected FTM interrupts.

Parameters:

base – FTM peripheral base address
mask – The interrupts to enable. This is a logical OR of members of the enumeration ftm_interrupt_enable_t

uint32_t FTM_GetEnabledInterrupts(FTM_Type *base)

Gets the enabled FTM interrupts.

Parameters:

base – FTM peripheral base address

Returns:

The enabled interrupts. This is the logical OR of members of the enumeration ftm_interrupt_enable_t

uint32_t FTM_GetInstance(FTM_Type *base)

Gets the instance from the base address.

Parameters:

base – FTM peripheral base address

Returns:

The FTM instance

uint32_t FTM_GetStatusFlags(FTM_Type *base)

Gets the FTM status flags.

Parameters:

base – FTM peripheral base address

Returns:

The status flags. This is the logical OR of members of the enumeration ftm_status_flags_t

void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask)

Clears the FTM status flags.

Parameters:

base – FTM peripheral base address
mask – The status flags to clear. This is a logical OR of members of the enumeration ftm_status_flags_t

static inline void FTM_SetTimerPeriod(FTM_Type *base, uint32_t ticks)

Sets the timer period in units of ticks.

Timers counts from 0 until it equals the count value set here. The count value is written to the MOD register.

Note

This API allows the user to use the FTM module as a timer. Do not mix usage of this API with FTM’s PWM setup API’s.
Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks.

Parameters:

base – FTM peripheral base address
ticks – A timer period in units of ticks, which should be equal or greater than 1.

static inline uint32_t FTM_GetCurrentTimerCount(FTM_Type *base)

Reads the current timer counting value.

This function returns the real-time timer counting value in a range from 0 to a timer period.

Note

Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.

Parameters:

base – FTM peripheral base address

Returns:

The current counter value in ticks

static inline uint32_t FTM_GetInputCaptureValue(FTM_Type *base, ftm_chnl_t chnlNumber)

Reads the captured value.

This function returns the captured value of a FTM channel configured in input capture or dual edge capture mode.

Note

Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.

Parameters:

base – FTM peripheral base address
chnlNumber – Channel to be read

Returns:

The captured FTM counter value of the input modes.

static inline void FTM_StartTimer(FTM_Type *base, ftm_clock_source_t clockSource)

Starts the FTM counter.

Parameters:

base – FTM peripheral base address
clockSource – FTM clock source; After the clock source is set, the counter starts running.

static inline void FTM_StopTimer(FTM_Type *base)

Stops the FTM counter.

Parameters:

base – FTM peripheral base address

static inline void FTM_SetSoftwareCtrlEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)

Enables or disables the channel software output control.

Parameters:

base – FTM peripheral base address
chnlNumber – Channel to be enabled or disabled
value – true: channel output is affected by software output control false: channel output is unaffected by software output control

static inline void FTM_SetSoftwareCtrlVal(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)

Sets the channel software output control value.

Parameters:

base – FTM peripheral base address.
chnlNumber – Channel to be configured
value – true to set 1, false to set 0

static inline void FTM_SetFaultControlEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)

This function enables/disables the fault control in a channel pair.

Parameters:

base – FTM peripheral base address
chnlPairNumber – The FTM channel pair number; options are 0, 1, 2, 3
value – true: Enable fault control for this channel pair; false: No fault control

static inline void FTM_SetDeadTimeEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)

This function enables/disables the dead time insertion in a channel pair.

Parameters:

base – FTM peripheral base address
chnlPairNumber – The FTM channel pair number; options are 0, 1, 2, 3
value – true: Insert dead time in this channel pair; false: No dead time inserted

static inline void FTM_SetComplementaryEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)

This function enables/disables complementary mode in a channel pair.

Parameters:

base – FTM peripheral base address
chnlPairNumber – The FTM channel pair number; options are 0, 1, 2, 3
value – true: enable complementary mode; false: disable complementary mode

static inline void FTM_SetInvertEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value)

This function enables/disables inverting control in a channel pair.

Parameters:

base – FTM peripheral base address
chnlPairNumber – The FTM channel pair number; options are 0, 1, 2, 3
value – true: enable inverting; false: disable inverting

void FTM_SetupQuadDecode(FTM_Type *base, const ftm_phase_params_t *phaseAParams, const ftm_phase_params_t *phaseBParams, ftm_quad_decode_mode_t quadMode)

Configures the parameters and activates the quadrature decoder mode.

Parameters:

base – FTM peripheral base address
phaseAParams – Phase A configuration parameters
phaseBParams – Phase B configuration parameters
quadMode – Selects encoding mode used in quadrature decoder mode

static inline uint32_t FTM_GetQuadDecoderFlags(FTM_Type *base)

Gets the FTM Quad Decoder flags.

Parameters:

base – FTM peripheral base address.

Returns:

Flag mask of FTM Quad Decoder, see _ftm_quad_decoder_flags.

static inline void FTM_SetQuadDecoderModuloValue(FTM_Type *base, uint32_t startValue, uint32_t overValue)

Sets the modulo values for Quad Decoder.

The modulo values configure the minimum and maximum values that the Quad decoder counter can reach. After the counter goes over, the counter value goes to the other side and decrease/increase again.

Parameters:

base – FTM peripheral base address.
startValue – The low limit value for Quad Decoder counter.
overValue – The high limit value for Quad Decoder counter.

static inline uint32_t FTM_GetQuadDecoderCounterValue(FTM_Type *base)

Gets the current Quad Decoder counter value.

Parameters:

base – FTM peripheral base address.

Returns:

Current quad Decoder counter value.

static inline void FTM_ClearQuadDecoderCounterValue(FTM_Type *base)

Clears the current Quad Decoder counter value.

The counter is set as the initial value.

Parameters:

base – FTM peripheral base address.

FSL_FTM_DRIVER_VERSION: FTM driver version 2.6.1.

enum _ftm_chnl

List of FTM channels.

Note

Actual number of available channels is SoC dependent

Values:

enumerator kFTM_Chnl_0: FTM channel number 0

enumerator kFTM_Chnl_1: FTM channel number 1

enumerator kFTM_Chnl_2: FTM channel number 2

enumerator kFTM_Chnl_3: FTM channel number 3

enumerator kFTM_Chnl_4: FTM channel number 4

enumerator kFTM_Chnl_5: FTM channel number 5

enumerator kFTM_Chnl_6: FTM channel number 6

enumerator kFTM_Chnl_7: FTM channel number 7

enum _ftm_fault_input

List of FTM faults.

Values:

enumerator kFTM_Fault_0: FTM fault 0 input pin

enumerator kFTM_Fault_1: FTM fault 1 input pin

enumerator kFTM_Fault_2: FTM fault 2 input pin

enumerator kFTM_Fault_3: FTM fault 3 input pin

enum _ftm_pwm_mode

FTM PWM operation modes.

Values:

enumerator kFTM_EdgeAlignedPwm: Edge-aligned PWM

enumerator kFTM_CenterAlignedPwm: Center-aligned PWM

enumerator kFTM_EdgeAlignedCombinedPwm: Edge-aligned combined PWM

enumerator kFTM_CenterAlignedCombinedPwm: Center-aligned combined PWM

enumerator kFTM_AsymmetricalCombinedPwm: Asymmetrical combined PWM

enum _ftm_pwm_level_select

FTM PWM output pulse mode: high-true, low-true or no output.

Values:

enumerator kFTM_NoPwmSignal: No PWM output on pin

enumerator kFTM_LowTrue: Low true pulses

enumerator kFTM_HighTrue: High true pulses

enum _ftm_output_compare_mode

FlexTimer output compare mode.

Values:

enumerator kFTM_NoOutputSignal: No channel output when counter reaches CnV

enumerator kFTM_ToggleOnMatch: Toggle output

enumerator kFTM_ClearOnMatch: Clear output

enumerator kFTM_SetOnMatch: Set output

enum _ftm_input_capture_edge

FlexTimer input capture edge.

Values:

enumerator kFTM_RisingEdge: Capture on rising edge only

enumerator kFTM_FallingEdge: Capture on falling edge only

enumerator kFTM_RiseAndFallEdge: Capture on rising or falling edge

enum _ftm_dual_edge_capture_mode

FlexTimer dual edge capture modes.

Values:

enumerator kFTM_OneShot: One-shot capture mode

enumerator kFTM_Continuous: Continuous capture mode

enum _ftm_quad_decode_mode

FlexTimer quadrature decode modes.

Values:

enumerator kFTM_QuadPhaseEncode: Phase A and Phase B encoding mode

enumerator kFTM_QuadCountAndDir: Count and direction encoding mode

enum _ftm_phase_polarity

FlexTimer quadrature phase polarities.

Values:

enumerator kFTM_QuadPhaseNormal: Phase input signal is not inverted

enumerator kFTM_QuadPhaseInvert: Phase input signal is inverted

enum _ftm_deadtime_prescale

FlexTimer pre-scaler factor for the dead time insertion.

Values:

enumerator kFTM_Deadtime_Prescale_1: Divide by 1

enumerator kFTM_Deadtime_Prescale_4: Divide by 4

enumerator kFTM_Deadtime_Prescale_16: Divide by 16

enum _ftm_clock_source

FlexTimer clock source selection.

Values:

enumerator kFTM_SystemClock: System clock selected

enumerator kFTM_FixedClock: Fixed frequency clock

enumerator kFTM_ExternalClock: External clock

enum _ftm_clock_prescale

FlexTimer pre-scaler factor selection for the clock source.

Values:

enumerator kFTM_Prescale_Divide_1: Divide by 1

enumerator kFTM_Prescale_Divide_2: Divide by 2

enumerator kFTM_Prescale_Divide_4: Divide by 4

enumerator kFTM_Prescale_Divide_8: Divide by 8

enumerator kFTM_Prescale_Divide_16: Divide by 16

enumerator kFTM_Prescale_Divide_32: Divide by 32

enumerator kFTM_Prescale_Divide_64: Divide by 64

enumerator kFTM_Prescale_Divide_128: Divide by 128

enum _ftm_bdm_mode

Options for the FlexTimer behaviour in BDM Mode.

Values:

enumerator kFTM_BdmMode_0: FTM counter stopped, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V registers bypass the register buffers

enumerator kFTM_BdmMode_1: FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are forced to their safe value , writes to MOD,CNTIN and C(n)V registers bypass the register buffers

enumerator kFTM_BdmMode_2: FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are frozen when chip enters in BDM mode, writes to MOD,CNTIN and C(n)V registers bypass the register buffers

enumerator kFTM_BdmMode_3: FTM counter in functional mode, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V registers is in fully functional mode

enum _ftm_fault_mode

Options for the FTM fault control mode.

Values:

enumerator kFTM_Fault_Disable: Fault control is disabled for all channels

enumerator kFTM_Fault_EvenChnls: Enabled for even channels only(0,2,4,6) with manual fault clearing

enumerator kFTM_Fault_AllChnlsMan: Enabled for all channels with manual fault clearing

enumerator kFTM_Fault_AllChnlsAuto: Enabled for all channels with automatic fault clearing

enum _ftm_external_trigger

FTM external trigger options.

Note

Actual available external trigger sources are SoC-specific

Values:

enumerator kFTM_Chnl0Trigger: Generate trigger when counter equals chnl 0 CnV reg

enumerator kFTM_Chnl1Trigger: Generate trigger when counter equals chnl 1 CnV reg

enumerator kFTM_Chnl2Trigger: Generate trigger when counter equals chnl 2 CnV reg

enumerator kFTM_Chnl3Trigger: Generate trigger when counter equals chnl 3 CnV reg

enumerator kFTM_Chnl4Trigger: Generate trigger when counter equals chnl 4 CnV reg

enumerator kFTM_Chnl5Trigger: Generate trigger when counter equals chnl 5 CnV reg

enumerator kFTM_Chnl6Trigger: Available on certain SoC’s, generate trigger when counter equals chnl 6 CnV reg

enumerator kFTM_Chnl7Trigger: Available on certain SoC’s, generate trigger when counter equals chnl 7 CnV reg

enumerator kFTM_InitTrigger: Generate Trigger when counter is updated with CNTIN

enumerator kFTM_ReloadInitTrigger: Available on certain SoC’s, trigger on reload point

enum _ftm_pwm_sync_method

FlexTimer PWM sync options to update registers with buffer.

Values:

enumerator kFTM_SoftwareTrigger: Software triggers PWM sync

enumerator kFTM_HardwareTrigger_0: Hardware trigger 0 causes PWM sync

enumerator kFTM_HardwareTrigger_1: Hardware trigger 1 causes PWM sync

enumerator kFTM_HardwareTrigger_2: Hardware trigger 2 causes PWM sync

enum _ftm_reload_point

FTM options available as loading point for register reload.

Note

Actual available reload points are SoC-specific

Values:

enumerator kFTM_Chnl0Match: Channel 0 match included as a reload point

enumerator kFTM_Chnl1Match: Channel 1 match included as a reload point

enumerator kFTM_Chnl2Match: Channel 2 match included as a reload point

enumerator kFTM_Chnl3Match: Channel 3 match included as a reload point

enumerator kFTM_Chnl4Match: Channel 4 match included as a reload point

enumerator kFTM_Chnl5Match: Channel 5 match included as a reload point

enumerator kFTM_Chnl6Match: Channel 6 match included as a reload point

enumerator kFTM_Chnl7Match: Channel 7 match included as a reload point

enumerator kFTM_CntMax: Use in up-down count mode only, reload when counter reaches the maximum value

enumerator kFTM_CntMin: Use in up-down count mode only, reload when counter reaches the minimum value

enumerator kFTM_HalfCycMatch: Available on certain SoC’s, half cycle match reload point

enum _ftm_interrupt_enable

List of FTM interrupts.

Note

Actual available interrupts are SoC-specific

Values:

enumerator kFTM_Chnl0InterruptEnable: Channel 0 interrupt

enumerator kFTM_Chnl1InterruptEnable: Channel 1 interrupt

enumerator kFTM_Chnl2InterruptEnable: Channel 2 interrupt

enumerator kFTM_Chnl3InterruptEnable: Channel 3 interrupt

enumerator kFTM_Chnl4InterruptEnable: Channel 4 interrupt

enumerator kFTM_Chnl5InterruptEnable: Channel 5 interrupt

enumerator kFTM_Chnl6InterruptEnable: Channel 6 interrupt

enumerator kFTM_Chnl7InterruptEnable: Channel 7 interrupt

enumerator kFTM_FaultInterruptEnable: Fault interrupt

enumerator kFTM_TimeOverflowInterruptEnable: Time overflow interrupt

enumerator kFTM_ReloadInterruptEnable: Reload interrupt; Available only on certain SoC’s

enum _ftm_status_flags

List of FTM flags.

Note

Actual available flags are SoC-specific

Values:

enumerator kFTM_Chnl0Flag: Channel 0 Flag

enumerator kFTM_Chnl1Flag: Channel 1 Flag

enumerator kFTM_Chnl2Flag: Channel 2 Flag

enumerator kFTM_Chnl3Flag: Channel 3 Flag

enumerator kFTM_Chnl4Flag: Channel 4 Flag

enumerator kFTM_Chnl5Flag: Channel 5 Flag

enumerator kFTM_Chnl6Flag: Channel 6 Flag

enumerator kFTM_Chnl7Flag: Channel 7 Flag

enumerator kFTM_FaultFlag: Fault Flag

enumerator kFTM_TimeOverflowFlag: Time overflow Flag

enumerator kFTM_ChnlTriggerFlag: Channel trigger Flag

enumerator kFTM_ReloadFlag: Reload Flag; Available only on certain SoC’s

List of FTM Quad Decoder flags.

Values:

enumerator kFTM_QuadDecoderCountingIncreaseFlag: Counting direction is increasing (FTM counter increment), or the direction is decreasing.

enumerator kFTM_QuadDecoderCountingOverflowOnTopFlag: Indicates if the TOF bit was set on the top or the bottom of counting.

typedef enum _ftm_chnl ftm_chnl_t: List of FTM channels.

Note

Actual number of available channels is SoC dependent

typedef enum _ftm_fault_input ftm_fault_input_t: List of FTM faults.

typedef enum _ftm_pwm_mode ftm_pwm_mode_t: FTM PWM operation modes.

typedef enum _ftm_pwm_level_select ftm_pwm_level_select_t: FTM PWM output pulse mode: high-true, low-true or no output.

typedef struct _ftm_chnl_pwm_signal_param ftm_chnl_pwm_signal_param_t: Options to configure a FTM channel’s PWM signal.

typedef struct _ftm_chnl_pwm_config_param ftm_chnl_pwm_config_param_t: Options to configure a FTM channel using precise setting.

typedef enum _ftm_output_compare_mode ftm_output_compare_mode_t: FlexTimer output compare mode.

typedef enum _ftm_input_capture_edge ftm_input_capture_edge_t: FlexTimer input capture edge.

typedef enum _ftm_dual_edge_capture_mode ftm_dual_edge_capture_mode_t: FlexTimer dual edge capture modes.

typedef struct _ftm_dual_edge_capture_param ftm_dual_edge_capture_param_t: FlexTimer dual edge capture parameters.

typedef enum _ftm_quad_decode_mode ftm_quad_decode_mode_t: FlexTimer quadrature decode modes.

typedef enum _ftm_phase_polarity ftm_phase_polarity_t: FlexTimer quadrature phase polarities.

typedef struct _ftm_phase_param ftm_phase_params_t: FlexTimer quadrature decode phase parameters.

typedef struct _ftm_fault_param ftm_fault_param_t: Structure is used to hold the parameters to configure a FTM fault.

typedef enum _ftm_deadtime_prescale ftm_deadtime_prescale_t: FlexTimer pre-scaler factor for the dead time insertion.

typedef enum _ftm_clock_source ftm_clock_source_t: FlexTimer clock source selection.

typedef enum _ftm_clock_prescale ftm_clock_prescale_t: FlexTimer pre-scaler factor selection for the clock source.

typedef enum _ftm_bdm_mode ftm_bdm_mode_t: Options for the FlexTimer behaviour in BDM Mode.

typedef enum _ftm_fault_mode ftm_fault_mode_t: Options for the FTM fault control mode.

typedef enum _ftm_external_trigger ftm_external_trigger_t: FTM external trigger options.

Note

Actual available external trigger sources are SoC-specific

typedef enum _ftm_pwm_sync_method ftm_pwm_sync_method_t: FlexTimer PWM sync options to update registers with buffer.

typedef enum _ftm_reload_point ftm_reload_point_t: FTM options available as loading point for register reload.

Note

Actual available reload points are SoC-specific

typedef enum _ftm_interrupt_enable ftm_interrupt_enable_t: List of FTM interrupts.

Note

Actual available interrupts are SoC-specific

typedef enum _ftm_status_flags ftm_status_flags_t: List of FTM flags.

Note

Actual available flags are SoC-specific

typedef struct _ftm_config ftm_config_t

FTM configuration structure.

This structure holds the configuration settings for the FTM peripheral. To initialize this structure to reasonable defaults, call the FTM_GetDefaultConfig() function and pass a pointer to the configuration structure instance.

The configuration structure can be made constant so as to reside in flash.

void FTM_SetupFaultInput(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams)

Sets up the working of the FTM fault inputs protection.

FTM can have up to 4 fault inputs. This function sets up fault parameters, fault level, and input filter.

Parameters:

base – FTM peripheral base address
faultNumber – FTM fault to configure.
faultParams – Parameters passed in to set up the fault

static inline void FTM_SetGlobalTimeBaseOutputEnable(FTM_Type *base, bool enable)

Enables or disables the FTM global time base signal generation to other FTMs.

Parameters:

base – FTM peripheral base address
enable – true to enable, false to disable

static inline void FTM_SetOutputMask(FTM_Type *base, ftm_chnl_t chnlNumber, bool mask)

Sets the FTM peripheral timer channel output mask.

Parameters:

base – FTM peripheral base address
chnlNumber – Channel to be configured
mask – true: masked, channel is forced to its inactive state; false: unmasked

static inline void FTM_SetPwmOutputEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value)

Allows users to enable an output on an FTM channel.

To enable the PWM channel output call this function with val=true. For input mode, call this function with val=false.

Parameters:

base – FTM peripheral base address
chnlNumber – Channel to be configured
value – true: enable output; false: output is disabled, used in input mode

static inline void FTM_SetSoftwareTrigger(FTM_Type *base, bool enable)

Enables or disables the FTM software trigger for PWM synchronization.

Parameters:

base – FTM peripheral base address
enable – true: software trigger is selected, false: software trigger is not selected

static inline void FTM_SetWriteProtection(FTM_Type *base, bool enable)

Enables or disables the FTM write protection.

Parameters:

base – FTM peripheral base address
enable – true: Write-protection is enabled, false: Write-protection is disabled

static inline void FTM_EnableDmaTransfer(FTM_Type *base, ftm_chnl_t chnlNumber, bool enable)

Enable DMA transfer or not.

Note: CHnIE bit needs to be set when calling this API. The channel DMA transfer request is generated and the channel interrupt is not generated if (CHnF = 1) when DMA and CHnIE bits are set.

Parameters:

base – FTM peripheral base address.
chnlNumber – Channel to be configured
enable – true to enable, false to disable

static inline void FTM_SetLdok(FTM_Type *base, bool value)

Enable the LDOK bit.

This function enables loading updated values.

Parameters:

base – FTM peripheral base address
value – true: loading updated values is enabled; false: loading updated values is disabled.

static inline void FTM_SetHalfCycReloadMatchValue(FTM_Type *base, uint32_t ticks)

Sets the half cycle relade period in units of ticks.

This function can be callled to set the half-cycle reload value when half-cycle matching is enabled as a reload point. Note: Need enable kFTM_HalfCycMatch as reload point, and when this API call after FTM_StartTimer(), the new HCR value will not be active until next reload point (need call FTM_SetLdok to set LDOK) or register synchronization.

Parameters:

base – FTM peripheral base address
ticks – A timer period in units of ticks, which should be equal or greater than 1.

static inline void FTM_SetLoadFreq(FTM_Type *base, uint32_t loadfreq)

Set load frequency value.

Parameters:

base – FTM peripheral base address.
loadfreq – PWM reload frequency, range: 0 ~ 31.

struct _ftm_chnl_pwm_signal_param

#include <fsl_ftm.h>

Options to configure a FTM channel’s PWM signal.

Public Members

ftm_chnl_t chnlNumber: The channel/channel pair number. In combined mode, this represents the channel pair number.

ftm_pwm_level_select_t level: PWM output active level select.

uint8_t dutyCyclePercent: PWM pulse width, value should be between 0 to 100 0 = inactive signal(0% duty cycle)… 100 = always active signal (100% duty cycle).

uint8_t firstEdgeDelayPercent: Used only in kFTM_AsymmetricalCombinedPwm mode to generate an asymmetrical PWM. Specifies the delay to the first edge in a PWM period. If unsure leave as 0; Should be specified as a percentage of the PWM period

bool enableComplementary: Used only in combined PWM mode. true: The combined channels output complementary signals; false: The combined channels output same signals;

bool enableDeadtime: Used only in combined PWM mode with enable complementary. true: The deadtime insertion in this pair of channels is enabled; false: The deadtime insertion in this pair of channels is disabled.

struct _ftm_chnl_pwm_config_param

#include <fsl_ftm.h>

Options to configure a FTM channel using precise setting.

Public Members

ftm_chnl_t chnlNumber: The channel/channel pair number. In combined mode, this represents the channel pair number.

ftm_pwm_level_select_t level: PWM output active level select.

uint16_t dutyValue: PWM pulse width, the uint of this value is timer ticks.

uint16_t firstEdgeValue: Used only in kFTM_AsymmetricalCombinedPwm mode to generate an asymmetrical PWM. Specifies the delay to the first edge in a PWM period. If unsure leave as 0, uint of this value is timer ticks.

bool enableComplementary: Used only in combined PWM mode. true: The combined channels output complementary signals; false: The combined channels output same signals;

bool enableDeadtime: Used only in combined PWM mode with enable complementary. true: The deadtime insertion in this pair of channels is enabled; false: The deadtime insertion in this pair of channels is disabled.

struct _ftm_dual_edge_capture_param

#include <fsl_ftm.h>

FlexTimer dual edge capture parameters.

Public Members

ftm_dual_edge_capture_mode_t mode: Dual Edge Capture mode

ftm_input_capture_edge_t currChanEdgeMode: Input capture edge select for channel n

ftm_input_capture_edge_t nextChanEdgeMode: Input capture edge select for channel n+1

struct _ftm_phase_param

#include <fsl_ftm.h>

FlexTimer quadrature decode phase parameters.

Public Members

bool enablePhaseFilter: True: enable phase filter; false: disable filter

uint32_t phaseFilterVal: Filter value, used only if phase filter is enabled

ftm_phase_polarity_t phasePolarity: Phase polarity

struct _ftm_fault_param

#include <fsl_ftm.h>

Structure is used to hold the parameters to configure a FTM fault.

Public Members

bool enableFaultInput: True: Fault input is enabled; false: Fault input is disabled

bool faultLevel: True: Fault polarity is active low; in other words, ‘0’ indicates a fault; False: Fault polarity is active high

bool useFaultFilter: True: Use the filtered fault signal; False: Use the direct path from fault input

struct _ftm_config

#include <fsl_ftm.h>

FTM configuration structure.

This structure holds the configuration settings for the FTM peripheral. To initialize this structure to reasonable defaults, call the FTM_GetDefaultConfig() function and pass a pointer to the configuration structure instance.

The configuration structure can be made constant so as to reside in flash.

Public Members

ftm_clock_prescale_t prescale: FTM clock prescale value

ftm_bdm_mode_t bdmMode: FTM behavior in BDM mode

uint32_t pwmSyncMode: Synchronization methods to use to update buffered registers; Multiple update modes can be used by providing an OR’ed list of options available in enumeration ftm_pwm_sync_method_t.

uint32_t reloadPoints: FTM reload points; When using this, the PWM synchronization is not required. Multiple reload points can be used by providing an OR’ed list of options available in enumeration ftm_reload_point_t.

ftm_fault_mode_t faultMode: FTM fault control mode

uint8_t faultFilterValue: Fault input filter value

ftm_deadtime_prescale_t deadTimePrescale: The dead time prescalar value

uint32_t deadTimeValue: The dead time value deadTimeValue’s available range is 0-1023 when register has DTVALEX, otherwise its available range is 0-63.

uint32_t extTriggers: External triggers to enable. Multiple trigger sources can be enabled by providing an OR’ed list of options available in enumeration ftm_external_trigger_t.

uint8_t chnlInitState: Defines the initialization value of the channels in OUTINT register

uint8_t chnlPolarity: Defines the output polarity of the channels in POL register

bool useGlobalTimeBase: True: Use of an external global time base is enabled; False: disabled

bool swTriggerResetCount: FTM counter synchronization activated by software trigger, avtive when (syncMethod & FTM_SYNC_SWSYNC_MASK) != 0U

bool hwTriggerResetCount: FTM counter synchronization activated by hardware trigger, avtive when (syncMethod & (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK)) != 0U

I2C: Inter-Integrated Circuit Driver

I2C DMA Driver

void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_dma_transfer_callback_t callback, void *userData, dma_handle_t *dmaHandle)

Init the I2C handle which is used in transactional functions.

Parameters:

base – I2C peripheral base address
handle – pointer to i2c_master_dma_handle_t structure
callback – pointer to user callback function
userData – user param passed to the callback function
dmaHandle – DMA handle pointer

status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer)

Performs a master dma non-blocking transfer on the I2C bus.

Parameters:

base – I2C peripheral base address
handle – pointer to i2c_master_dma_handle_t structure
xfer – pointer to transfer structure of i2c_master_transfer_t

Return values:

kStatus_Success – Sucessully complete the data transmission.
kStatus_I2C_Busy – Previous transmission still not finished.
kStatus_I2C_Timeout – Transfer error, wait signal timeout.
kStatus_I2C_ArbitrationLost – Transfer error, arbitration lost.
kStataus_I2C_Nak – Transfer error, receive Nak during transfer.

status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count)

Get master transfer status during a dma non-blocking transfer.

Parameters:

base – I2C peripheral base address
handle – pointer to i2c_master_dma_handle_t structure
count – Number of bytes transferred so far by the non-blocking transaction.

void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle)

Abort a master dma non-blocking transfer in a early time.

Parameters:

base – I2C peripheral base address
handle – pointer to i2c_master_dma_handle_t structure

FSL_I2C_DMA_DRIVER_VERSION: I2C DMA driver version.

typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t: I2C master dma handle typedef.

typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, i2c_master_dma_handle_t *handle, status_t status, void *userData): I2C master dma transfer callback typedef.

I2C_MAX_DMA_TRANSFER_COUNT: Maximum lenght of single DMA transfer (determined by capability of the DMA engine)

struct _i2c_master_dma_handle

#include <fsl_i2c_dma.h>

I2C master dma transfer structure.

Public Members

uint8_t state: Transfer state machine current state.

uint32_t transferCount: Indicates progress of the transfer

uint32_t remainingBytesDMA: Remaining byte count to be transferred using DMA.

uint8_t *buf: Buffer pointer for current state.

dma_handle_t *dmaHandle: The DMA handler used.

i2c_master_transfer_t transfer: Copy of the current transfer info.

i2c_master_dma_transfer_callback_t completionCallback: Callback function called after dma transfer finished.

void *userData: Callback parameter passed to callback function.

I2C Driver

FSL_I2C_DRIVER_VERSION: I2C driver version.

I2C status return codes.

Values:

enumerator kStatus_I2C_Busy: The master is already performing a transfer.

enumerator kStatus_I2C_Idle: The slave driver is idle.

enumerator kStatus_I2C_Nak: The slave device sent a NAK in response to a byte.

enumerator kStatus_I2C_InvalidParameter: Unable to proceed due to invalid parameter.

enumerator kStatus_I2C_BitError: Transferred bit was not seen on the bus.

enumerator kStatus_I2C_ArbitrationLost: Arbitration lost error.

enumerator kStatus_I2C_NoTransferInProgress: Attempt to abort a transfer when one is not in progress.

enumerator kStatus_I2C_DmaRequestFail: DMA request failed.

enumerator kStatus_I2C_StartStopError: Start and stop error.

enumerator kStatus_I2C_UnexpectedState: Unexpected state.

enumerator kStatus_I2C_Addr_Nak: NAK received during the address probe.

enumerator kStatus_I2C_Timeout: Timeout polling status flags.

I2C_RETRY_TIMES: Retry times for waiting flag.

I2C_STAT_MSTCODE_IDLE: Master Idle State Code

I2C_STAT_MSTCODE_RXREADY: Master Receive Ready State Code

I2C_STAT_MSTCODE_TXREADY: Master Transmit Ready State Code

I2C_STAT_MSTCODE_NACKADR: Master NACK by slave on address State Code

I2C_STAT_MSTCODE_NACKDAT: Master NACK by slave on data State Code

I2C_STAT_SLVST_ADDR

I2C_STAT_SLVST_RX

I2C_STAT_SLVST_TX

I2C Master Driver

void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)

Provides a default configuration for the I2C master peripheral.

This function provides the following default configuration for the I2C master peripheral:

masterConfig->enableMaster            = true;
masterConfig->baudRate_Bps            = 100000U;
masterConfig->enableTimeout           = false;

After calling this function, you can override any settings in order to customize the configuration, prior to initializing the master driver with I2C_MasterInit().

Parameters:

masterConfig – [out] User provided configuration structure for default values. Refer to i2c_master_config_t.

void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)

Initializes the I2C master peripheral.

This function enables the peripheral clock and initializes the I2C master peripheral as described by the user provided configuration. A software reset is performed prior to configuration.

Parameters:

base – The I2C peripheral base address.
masterConfig – User provided peripheral configuration. Use I2C_MasterGetDefaultConfig() to get a set of defaults that you can override.
srcClock_Hz – Frequency in Hertz of the I2C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods.

void I2C_MasterDeinit(I2C_Type *base)

Deinitializes the I2C master peripheral.

This function disables the I2C master peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

base – The I2C peripheral base address.

uint32_t I2C_GetInstance(I2C_Type *base)

Returns an instance number given a base address.

If an invalid base address is passed, debug builds will assert. Release builds will just return instance number 0.

Parameters:

base – The I2C peripheral base address.

Returns:

I2C instance number starting from 0.

static inline void I2C_MasterReset(I2C_Type *base)

Performs a software reset.

Restores the I2C master peripheral to reset conditions.

Parameters:

base – The I2C peripheral base address.

static inline void I2C_MasterEnable(I2C_Type *base, bool enable)

Enables or disables the I2C module as master.

Parameters:

base – The I2C peripheral base address.
enable – Pass true to enable or false to disable the specified I2C as master.

static inline uint32_t I2C_GetStatusFlags(I2C_Type *base)

Gets the I2C status flags.

A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit in the return value is set if the flag is asserted.

I2C Slave Driver

void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig)

Provides a default configuration for the I2C slave peripheral.

This function provides the following default configuration for the I2C slave peripheral:

slaveConfig->enableSlave = true;
slaveConfig->address0.disable = false;
slaveConfig->address0.address = 0u;
slaveConfig->address1.disable = true;
slaveConfig->address2.disable = true;
slaveConfig->address3.disable = true;
slaveConfig->busSpeed = kI2C_SlaveStandardMode;

After calling this function, override any settings to customize the configuration, prior to initializing the master driver with I2C_SlaveInit(). Be sure to override at least the address0.address member of the configuration structure with the desired slave address.

Parameters:

slaveConfig – [out] User provided configuration structure that is set to default values. Refer to i2c_slave_config_t.

status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz)

Initializes the I2C slave peripheral.

This function enables the peripheral clock and initializes the I2C slave peripheral as described by the user provided configuration.

Parameters:

base – The I2C peripheral base address.
slaveConfig – User provided peripheral configuration. Use I2C_SlaveGetDefaultConfig() to get a set of defaults that you can override.
srcClock_Hz – Frequency in Hertz of the I2C functional clock. Used to calculate CLKDIV value to provide enough data setup time for master when slave stretches the clock.

void I2C_SlaveSetAddress(I2C_Type *base, i2c_slave_address_register_t addressRegister, uint8_t address, bool addressDisable)

Configures Slave Address n register.

This function writes new value to Slave Address register.

Parameters:

base – The I2C peripheral base address.
addressRegister – The module supports multiple address registers. The parameter determines which one shall be changed.
address – The slave address to be stored to the address register for matching.
addressDisable – Disable matching of the specified address register.

void I2C_SlaveDeinit(I2C_Type *base)

Deinitializes the I2C slave peripheral.

This function disables the I2C slave peripheral and gates the clock. It also performs a software reset to restore the peripheral to reset conditions.

Parameters:

base – The I2C peripheral base address.

static inline void I2C_SlaveEnable(I2C_Type *base, bool enable)

Enables or disables the I2C module as slave.

Parameters:

base – The I2C peripheral base address.
enable – True to enable or flase to disable.

static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask)

Clears the I2C status flag state.

The following status register flags can be cleared:

slave deselected flag

Attempts to clear other flags has no effect.

I3C: I3C Driver

FSL_I3C_DRIVER_VERSION: I3C driver version.

I3C status return codes.

Values:

enumerator kStatus_I3C_Busy: The master is already performing a transfer.

enumerator kStatus_I3C_Idle: The slave driver is idle.

enumerator kStatus_I3C_Nak: The slave device sent a NAK in response to an address.

enumerator kStatus_I3C_WriteAbort: The slave device sent a NAK in response to a write.

enumerator kStatus_I3C_Term: The master terminates slave read.

enumerator kStatus_I3C_HdrParityError: Parity error from DDR read.

enumerator kStatus_I3C_CrcError: CRC error from DDR read.

enumerator kStatus_I3C_ReadFifoError: Read from M/SRDATAB register when FIFO empty.

enumerator kStatus_I3C_WriteFifoError: Write to M/SWDATAB register when FIFO full.

enumerator kStatus_I3C_MsgError: Message SDR/DDR mismatch or read/write message in wrong state

enumerator kStatus_I3C_InvalidReq: Invalid use of request.

enumerator kStatus_I3C_Timeout: The module has stalled too long in a frame.

enumerator kStatus_I3C_SlaveCountExceed: The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.

enumerator kStatus_I3C_IBIWon: The I3C slave event IBI or MR or HJ won the arbitration on a header address.

enumerator kStatus_I3C_OverrunError: Slave internal from-bus buffer/FIFO overrun.

enumerator kStatus_I3C_UnderrunError: Slave internal to-bus buffer/FIFO underrun

enumerator kStatus_I3C_UnderrunNak: Slave internal from-bus buffer/FIFO underrun and NACK error

enumerator kStatus_I3C_InvalidStart: Slave invalid start flag

enumerator kStatus_I3C_SdrParityError: SDR parity error

enumerator kStatus_I3C_S0S1Error: S0 or S1 error

enum _i3c_hdr_mode

I3C HDR modes.

Values:

enumerator kI3C_HDRModeNone

enumerator kI3C_HDRModeDDR

enumerator kI3C_HDRModeTSP

enumerator kI3C_HDRModeTSL

typedef enum _i3c_hdr_mode i3c_hdr_mode_t: I3C HDR modes.

typedef struct _i3c_device_info i3c_device_info_t: I3C device information.

I3C_RETRY_TIMES: Timeout times for waiting flag.

I3C_MAX_DEVCNT

I3C_IBI_BUFF_SIZE

struct _i3c_device_info

#include <fsl_i3c.h>

I3C device information.

Public Members

uint8_t dynamicAddr: Device dynamic address.

uint8_t staticAddr: Static address.

uint8_t dcr: Device characteristics register information.

uint8_t bcr: Bus characteristics register information.

uint16_t vendorID: Device vendor ID(manufacture ID).

uint32_t partNumber: Device part number info

uint16_t maxReadLength: Maximum read length.

uint16_t maxWriteLength: Maximum write length.

uint8_t hdrMode: Support hdr mode, could be OR logic in i3c_hdr_mode.

I3C Common Driver

typedef struct _i3c_config i3c_config_t

Structure with settings to initialize the I3C module, could both initialize master and slave functionality.

This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_GetDefaultConfig() function and pass a pointer to your configuration structure instance.

The configuration structure can be made constant so it resides in flash.

uint32_t I3C_GetInstance(I3C_Type *base)

Get which instance current I3C is used.

Parameters:

base – The I3C peripheral base address.

void I3C_GetDefaultConfig(i3c_config_t *config)

Provides a default configuration for the I3C peripheral, the configuration covers both master functionality and slave functionality.

This function provides the following default configuration for I3C:

config->disableTimeout config->hKeep config->enableOpenDrainStop config->enableOpenDrainHigh config->baudRate_Hzconfig->baudRate_Hzconfig->baudRate_Hzconfig->masterDynamicAddress config->slowClock_Hz config->enableSlave config->vendorID config->enableRandomPart config->partNumber config->dcr config->bcr config->hdrMode config->nakAllRequest config->ignoreS0S1Error config->offline config->matchSlaveStartStop 

notranslate">

config->enableMaster                 = kI3C_MasterCapable; = false; = kI3C_MasterHighKeeperNone; = true; = true; class="o">.i2cBaud          = 400000U; class="o">.i3cPushPullBaud  = 12500000U; class="o">.i3cOpenDrainBaud = 2500000U; = 0x0AU; = 1000000U; = true; = 0x11BU; = false; = 0; = 0; = 0; = (uint8_t)kI3C_HDRModeDDR; = false; = false; = false; = false;
After calling this function, you can override any settings in order to customize the configuration, prior to initializing the common I3C driver with I3C_Init().

Parameters:

config – [out] User provided configuration structure for default values. Refer to i3c_config_t. 







void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz)

Initializes the I3C peripheral. This function enables the peripheral clock and initializes the I3C peripheral as described by the user provided configuration. This will initialize both the master peripheral and slave peripheral so that I3C module could work as pure master, pure slave or secondary master, etc. A software reset is performed prior to configuration. 

Parameters:

base – The I3C peripheral base address. 
config – User provided peripheral configuration. Use I3C_GetDefaultConfig() to get a set of defaults that you can override. 
sourceClock_Hz – Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, filter widths, and timeout periods. 







struct _i3c_config


#include <fsl_i3c.h>
Structure with settings to initialize the I3C module, could both initialize master and slave functionality. 
This structure holds configuration settings for the I3C peripheral. To initialize this structure to reasonable defaults, call the I3C_GetDefaultConfig() function and pass a pointer to your configuration structure instance.
The configuration structure can be made constant so it resides in flash. 

Public Members


i3c_master_enable_t enableMaster

Enable master mode. 




bool disableTimeout

Whether to disable timeout to prevent the ERRWARN. 




i3c_master_hkeep_t hKeep

High keeper mode setting. 




bool enableOpenDrainStop

Whether to emit open-drain speed STOP. 




bool enableOpenDrainHigh

Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. 




i3c_baudrate_hz_t baudRate_Hz

Desired baud rate settings. 




uint8_t masterDynamicAddress

Main master dynamic address configuration. 




uint32_t maxWriteLength

Maximum write length. 




uint32_t maxReadLength

Maximum read length. 




bool enableSlave

Whether to enable slave. 




bool isHotJoin

Whether to enable slave hotjoin before enable slave. 




uint8_t staticAddr

Static address. 




uint16_t vendorID

Device vendor ID(manufacture ID). 




uint32_t partNumber

Device part number info 




uint8_t dcr

Device characteristics register information. 




uint8_t bcr

Bus characteristics register information. 




uint8_t hdrMode

Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t. 




bool nakAllRequest

Whether to reply NAK to all requests except broadcast CCC. 




bool ignoreS0S1Error

Whether to ignore S0/S1 error in SDR mode. 




bool offline

Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely. 




bool matchSlaveStartStop

Whether to assert start/stop status only the time slave is addressed.

LPC865

Clock Driver

CRC: Cyclic Redundancy Check Driver

CTIMER: Standard counter/timers

DMA: Direct Memory Access Controller Driver

FTM: FlexTimer Driver

I2C: Inter-Integrated Circuit Driver

I2C DMA Driver

I2C Driver

I2C Master Driver

I2C Slave Driver

I3C: I3C Driver

I3C Common Driver

I3C Master DMA Driver

I3C Master Driver

I3C Slave DMA Driver

I3C Slave Driver

IAP: In Application Programming Driver

INPUTMUX: Input Multiplexing Driver

Common Driver

LPC_ACOMP: Analog comparator Driver

ADC: 12-bit SAR Analog-to-Digital Converter Driver

GPIO: General Purpose I/O

IOCON: I/O pin configuration

MRT: Multi-Rate Timer

PINT: Pin Interrupt and Pattern Match Driver

Power

Reset

SCTimer: SCTimer/PWM (SCT)

SPI: Serial Peripheral Interface Driver

SPI Driver

SWM: Switch Matrix Module

SYSCON: System Configuration

USART: Universal Asynchronous Receiver/Transmitter Driver

USART Driver

WKT: Self-wake-up Timer

WWDT: Windowed Watchdog Timer Driver