ISSDK  1.8
IoT Sensing Software Development Kit
mma845x.h
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 /**
10  * @file mma845x.h
11  * @brief The mma845x.h contains the MMA845x sensor register definitions and its bit mask.
12  */
13 
14 #ifndef MMA845x_H_
15 #define MMA845x_H_
16 
17 /**
18  ** MMA845x I2C Address
19  */
20 #define MMA845x_I2C_ADDRESS_SA0_0 0x1C /*MMA845x Address - SA0=0*/
21 #define MMA845x_I2C_ADDRESS_SA0_1 0x1D /*MMA845x Address - SA0=1*/
22 
23 /**
24  **
25  ** MMA845x Sensor Internal Registers
26  */
27 enum {
28  MMA845x_STATUS = 0x00, /*!< FMODE = 0, real time status */
29  MMA845x_F_STATUS = 0x00, /*!< FMODE > 0, FIFO status */
30  MMA845x_OUT_X_MSB = 0x01, /*!< data registers */
31  MMA845x_OUT_X_LSB = 0x02, /*!< data registers */
32  MMA845x_OUT_Y_MSB = 0x03, /*!< data registers */
33  MMA845x_OUT_Y_LSB = 0x04, /*!< data registers */
34  MMA845x_OUT_Z_MSB = 0x05, /*!< data registers */
35  MMA845x_OUT_Z_LSB = 0x06, /*!< data registers */
36  MMA845x_F_SETUP = 0x09, /*!< FIFO setup */
37  MMA845x_TRIG_CFG = 0x0A, /*!< Map of FIFO data capture events */
38  MMA845x_SYSMOD = 0x0B, /*!< SYSMOD System Mode register */
39  MMA845x_INT_SOURCE = 0x0C, /*!< INT_SOURCE System Interrupt Status register */
40  MMA845x_WHO_AM_I = 0x0D, /*!< WHO_AM_I Device ID register */
41  MMA845x_XYZ_DATA_CFG = 0x0E, /*!< XYZ_DATA_CFG register */
42  MMA845x_HP_FILTER_CUTOFF = 0x0F, /*!< MMA845x only */
43  MMA845x_PL_STATUS = 0x10, /*!< PL_STATUS Portrait/Landscape Status register */
44  MMA845x_PL_CFG = 0x11, /*!< Portrait/Landscape Configuration register */
45  MMA845x_PL_COUNT = 0x12, /*!< Portrait/Landscape Debounce register */
46  MMA845x_PL_BF_ZCOMP = 0x13, /*!< PL_BF_ZCOMP Back/Front and Z Compensation register */
47  MMA845x_PL_THS_REG = 0x14, /*!< P_L_THS_REG Portrait/Landscape Threshold and Hysteresis register */
48  MMA845x_FF_MT_CFG = 0x15, /*!< FF_MT_CFG Freefall/Motion Configuration register */
49  MMA845x_FF_MT_SRC = 0x16, /*!< FF_MT_SRC Freefall/Motion Source register */
50  MMA845x_FF_MT_THS = 0x17, /*!< FF_MT_THS Freefall and Motion Threshold register */
51  MMA845x_FF_MT_COUNT = 0x18, /*!< FF_MT_COUNT Debounce register */
52  MMA845x_TRANSIENT_CFG = 0x1D, /*!< Transient_CFG register */
53  MMA845x_TRANSIENT_SRC = 0x1E, /*!< TRANSIENT_SRC register */
54  MMA845x_TRANSIENT_THS = 0x1F, /*!< TRANSIENT_THS register */
55  MMA845x_TRANSIENT_COUNT = 0x20, /*!< TRANSIENT_COUNT register */
56  MMA845x_PULSE_CFG = 0x21, /*!< PULSE_CFG Pulse Configuration register */
57  MMA845x_PULSE_SRC = 0x22, /*!< PULSE_SRC Pulse Source register */
58  MMA845x_PULSE_THSX = 0x23, /*!< PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers */
59  MMA845x_PULSE_THSY = 0x24, /*!< PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers */
60  MMA845x_PULSE_THSZ = 0x25, /*!< PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers */
61  MMA845x_PULSE_TMLT = 0x26, /*!< PULSE_TMLT Pulse Time Window 1 register */
62  MMA845x_PULSE_LTCY = 0x27, /*!< PULSE_LTCY Pulse Latency Timer register */
63  MMA845x_PULSE_WIND = 0x28, /*!< PULSE_WIND register (Read/Write) */
64  MMA845x_ASLP_COUNT = 0x29, /*!< ASLP_COUNT, Auto-WAKE/SLEEP Detection register (Read/Write) */
65  MMA845x_CTRL_REG1 = 0x2A, /*!< CTRL_REG1 System Control 1 register */
66  MMA845x_CTRL_REG2 = 0x2B, /*!< CTRL_REG2 System Control 1 register */
67  MMA845x_CTRL_REG3 = 0x2C, /*!< CTRL_REG3 Interrupt Control register */
68  MMA845x_CTRL_REG4 = 0x2D, /*!< CTRL_REG4 Interrupt Enable register (Read/Write) */
69  MMA845x_CTRL_REG5 = 0x2E, /*!< CTRL_REG5 Interrupt Configuration register (Read/Write) */
70  MMA845x_OFF_X = 0x2F, /*!< OFF_X Offset Correction X register */
71  MMA845x_OFF_Y = 0x30, /*!< OFF_Y Offset Correction Y register */
72  MMA845x_OFF_Z = 0x31, /*!< OFF_Z Offset Correction Z register */
73 };
74 
75 
76 /*--------------------------------
77 ** Register: STATUS
78 ** Enum: MMA845x_STATUS
79 ** --
80 ** Offset : 0x00 - Real time status.
81 ** ------------------------------*/
82 typedef union {
83  struct {
84  uint8_t xdr : 1; /* - X-axis new Data Available. */
85 
86  uint8_t ydr : 1; /* - Y-axis new Data Available. */
87 
88  uint8_t zdr : 1; /* - Z-axis new Data Available. */
89 
90  uint8_t zyxdr : 1; /* - X, Y, Z-axis new Data Ready. */
91 
92  uint8_t xow : 1; /* - X-axis Data Overwrite. */
93 
94  uint8_t yow : 1; /* - Y-axis Data Overwrite. */
95 
96  uint8_t zow : 1; /* - Z-axis Data Overwrite */
97 
98  uint8_t zyxow : 1; /* - X, Y, Z-axis Data Overwrite. */
99 
100  } b;
101  uint8_t w;
102 } MMA845x_STATUS_t;
103 
104 
105 /*
106 ** STATUS - Bit field mask definitions
107 */
108 #define MMA845x_STATUS_XDR_MASK ((uint8_t) 0x01)
109 #define MMA845x_STATUS_XDR_SHIFT ((uint8_t) 0)
110 
111 #define MMA845x_STATUS_YDR_MASK ((uint8_t) 0x02)
112 #define MMA845x_STATUS_YDR_SHIFT ((uint8_t) 1)
113 
114 #define MMA845x_STATUS_ZDR_MASK ((uint8_t) 0x04)
115 #define MMA845x_STATUS_ZDR_SHIFT ((uint8_t) 2)
116 
117 #define MMA845x_STATUS_ZYXDR_MASK ((uint8_t) 0x08)
118 #define MMA845x_STATUS_ZYXDR_SHIFT ((uint8_t) 3)
119 
120 #define MMA845x_STATUS_XOW_MASK ((uint8_t) 0x10)
121 #define MMA845x_STATUS_XOW_SHIFT ((uint8_t) 4)
122 
123 #define MMA845x_STATUS_YOW_MASK ((uint8_t) 0x20)
124 #define MMA845x_STATUS_YOW_SHIFT ((uint8_t) 5)
125 
126 #define MMA845x_STATUS_ZOW_MASK ((uint8_t) 0x40)
127 #define MMA845x_STATUS_ZOW_SHIFT ((uint8_t) 6)
128 
129 #define MMA845x_STATUS_ZYXOW_MASK ((uint8_t) 0x80)
130 #define MMA845x_STATUS_ZYXOW_SHIFT ((uint8_t) 7)
131 
132 
133 /*
134 ** STATUS - Bit field value definitions
135 */
136 #define MMA845x_STATUS_XDR_XDATAREADY ((uint8_t) 0x01) /* A new X-axis data is ready. */
137 #define MMA845x_STATUS_YDR_YDATAREADY ((uint8_t) 0x02) /* A new Y-axis data is ready. */
138 #define MMA845x_STATUS_ZDR_ZDATAREADY ((uint8_t) 0x04) /* A new Z-axis data is ready. */
139 #define MMA845x_STATUS_ZYXDR_ZYXDATAREADY ((uint8_t) 0x08) /* A new set of XYZ data is ready. */
140 #define MMA845x_STATUS_XOW_XDATAOW ((uint8_t) 0x10) /* Previous X-axis data was overwritten by new X-axis */
141  /* data before it was read. */
142 #define MMA845x_STATUS_YOW_YDATAOW ((uint8_t) 0x20) /* Previous Y-axis data was overwritten by new X-axis */
143  /* data before it was read. */
144 #define MMA845x_STATUS_ZOW_ZDATAOW ((uint8_t) 0x40) /* Previous Z-axis data was overwritten by new X-axis */
145  /* data before it was read. */
146 #define MMA845x_STATUS_ZYXOW_XYZDATAOW ((uint8_t) 0x80) /* Previous X, Y, or Z data was overwritten by new X, Y, */
147  /* or Z data before it was read. */
148 /*------------------------------*/
149 
150 
151 
152 /*--------------------------------
153 ** Register: F_STATUS
154 ** Enum: MMA845x_F_STATUS
155 ** --
156 ** Offset : 0x00 - FIFO STATUS Register.
157 ** ------------------------------*/
158 typedef union {
159  struct {
160  uint8_t f_cnt : 6; /* - FIFO sample counter. 00_0001 to 10_0000 indicates 1 to 32 samples stored */
161  /* in FIFO. */
162 
163  uint8_t f_wmrk_flag : 1; /* - FIFO watermark flag. */
164 
165  uint8_t f_ovf : 1; /* - FIFO overflow flag. */
166 
167  } b;
168  uint8_t w;
169 } MMA845x_F_STATUS_t;
170 
171 
172 /*
173 ** F_STATUS - Bit field mask definitions
174 */
175 #define MMA845x_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F)
176 #define MMA845x_F_STATUS_F_CNT_SHIFT ((uint8_t) 0)
177 
178 #define MMA845x_F_STATUS_F_WMRK_FLAG_MASK ((uint8_t) 0x40)
179 #define MMA845x_F_STATUS_F_WMRK_FLAG_SHIFT ((uint8_t) 6)
180 
181 #define MMA845x_F_STATUS_F_OVF_MASK ((uint8_t) 0x80)
182 #define MMA845x_F_STATUS_F_OVF_SHIFT ((uint8_t) 7)
183 
184 
185 /*
186 ** F_STATUS - Bit field value definitions
187 */
188 #define MMA845x_F_STATUS_F_WMRK_FLAG_NOTDETECTED ((uint8_t) 0x00) /* No FIFO watermark events detected. */
189 #define MMA845x_F_STATUS_F_WMRK_FLAG_DETECTED ((uint8_t) 0x40) /* FIFO Watermark event detected. FIFO sample count is */
190  /* greater than watermark value. */
191 #define MMA845x_F_STATUS_F_OVF_NOTDETECTED ((uint8_t) 0x00) /* No FIFO overflow events detected. */
192 #define MMA845x_F_STATUS_F_OVF_DETECTED ((uint8_t) 0x80) /* FIFO event detected; FIFO has overflowed. */
193 /*------------------------------*/
194 
195 
196 
197 /*--------------------------------
198 ** Register: OUT_X_MSB
199 ** Enum: MMA845x_OUT_X_MSB
200 ** --
201 ** Offset : 0x01 - Bits 4-11 of 12-bit X Axis current sample data.
202 ** ------------------------------*/
203 typedef uint8_t MMA845x_OUT_X_MSB_t;
204 
205 
206 /*--------------------------------
207 ** Register: OUT_X_LSB
208 ** Enum: MMA845x_OUT_X_LSB
209 ** --
210 ** Offset : 0x02 - Bits 0-3 of 12-bit X Axis current sample data.
211 ** ------------------------------*/
212 typedef uint8_t MMA845x_OUT_X_LSB_t;
213 
214 
215 
216 /*--------------------------------
217 ** Register: OUT_Y_MSB
218 ** Enum: MMA845x_OUT_Y_MSB
219 ** --
220 ** Offset : 0x03 - Bits 4-11 of 12-bit Y Axis current sample data.
221 ** ------------------------------*/
222 typedef uint8_t MMA845x_OUT_Y_MSB_t;
223 
224 
225 /*--------------------------------
226 ** Register: OUT_Y_LSB
227 ** Enum: MMA845x_OUT_Y_LSB
228 ** --
229 ** Offset : 0x04 - Bits 0-3 of 12-bit Y Axis current sample data.
230 ** ------------------------------*/
231 typedef uint8_t MMA845x_OUT_Y_LSB_t;
232 
233 
234 
235 /*--------------------------------
236 ** Register: OUT_Z_MSB
237 ** Enum: MMA845x_OUT_Z_MSB
238 ** --
239 ** Offset : 0x05 - Bits 4-11 of 12-bit Z Axis current sample data.
240 ** ------------------------------*/
241 typedef uint8_t MMA845x_OUT_Z_MSB_t;
242 
243 
244 /*--------------------------------
245 ** Register: OUT_Z_LSB
246 ** Enum: MMA845x_OUT_Z_LSB
247 ** --
248 ** Offset : 0x06 - Bits 0-3 of 12-bit Z Axis current sample data.
249 ** ------------------------------*/
250 typedef uint8_t MMA845x_OUT_Z_LSB_t;
251 
252 
253 
254 /*--------------------------------
255 ** Register: F_SETUP
256 ** Enum: MMA845x_F_SETUP
257 ** --
258 ** Offset : 0x09 - FIFO Setup Register.
259 ** ------------------------------*/
260 typedef union {
261  struct {
262  uint8_t f_wmrk : 6; /* - FIFO Event Sample Count Watermark. These bits set the number of FIFO */
263  /* samples required to trigger a watermark interrupt. */
264 
265  uint8_t f_mode : 2; /* - FIFO buffer overflow mode. */
266 
267  } b;
268  uint8_t w;
269 } MMA845x_F_SETUP_t;
270 
271 
272 /*
273 ** F_SETUP - Bit field mask definitions
274 */
275 #define MMA845x_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F)
276 #define MMA845x_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0)
277 
278 #define MMA845x_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0)
279 #define MMA845x_F_SETUP_F_MODE_SHIFT ((uint8_t) 6)
280 
281 
282 /*
283 ** F_SETUP - Bit field value definitions
284 */
285 #define MMA845x_F_SETUP_F_MODE_FIFODISABLED ((uint8_t) 0x00) /* FIFO is disabled. */
286 #define MMA845x_F_SETUP_F_MODE_FIFOMOSTRECENT ((uint8_t) 0x40) /* FIFO contains the Most Recent samples when overflowed */
287  /* (circular buffer). */
288 #define MMA845x_F_SETUP_F_MODE_FIFOSTOP ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed. */
289 #define MMA845x_F_SETUP_F_MODE_TRIGGERMODE ((uint8_t) 0xc0) /* The FIFO will be in a circular mode up to the number */
290  /* of samples in the watermark. The FIFO will be in a */
291  /* circular mode until the trigger event occurs. */
292 /*------------------------------*/
293 
294 
295 
296 /*--------------------------------
297 ** Register: TRIG_CFG
298 ** Enum: MMA845x_TRIG_CFG
299 ** --
300 ** Offset : 0x0A - Trigger Configuration Register.
301 ** ------------------------------*/
302 typedef union {
303  struct {
304  uint8_t _reserved_ : 2;
305  uint8_t trig_ff_mt : 1; /* - Freefall/Motion trigger bit. */
306 
307  uint8_t trig_pulse : 1; /* - Pulse interrupt trigger bit. */
308 
309  uint8_t trig_lndprt : 1; /* - Landscape/Portrait Orientation interrupt trigger bit. */
310 
311  uint8_t trig_trans : 1; /* - Transient interrupt trigger bit. */
312 
313  } b;
314  uint8_t w;
315 } MMA845x_TRIG_CFG_t;
316 
317 
318 /*
319 ** TRIG_CFG - Bit field mask definitions
320 */
321 #define MMA845x_TRIG_CFG_TRIG_FF_MT_MASK ((uint8_t) 0x04)
322 #define MMA845x_TRIG_CFG_TRIG_FF_MT_SHIFT ((uint8_t) 2)
323 
324 #define MMA845x_TRIG_CFG_TRIG_PULSE_MASK ((uint8_t) 0x08)
325 #define MMA845x_TRIG_CFG_TRIG_PULSE_SHIFT ((uint8_t) 3)
326 
327 #define MMA845x_TRIG_CFG_TRIG_LNDPRT_MASK ((uint8_t) 0x10)
328 #define MMA845x_TRIG_CFG_TRIG_LNDPRT_SHIFT ((uint8_t) 4)
329 
330 #define MMA845x_TRIG_CFG_TRIG_TRANS_MASK ((uint8_t) 0x20)
331 #define MMA845x_TRIG_CFG_TRIG_TRANS_SHIFT ((uint8_t) 5)
332 
333 
334 /*
335 ** TRIG_CFG - Bit field value definitions
336 */
337 #define MMA845x_TRIG_CFG_TRIG_FF_MT_CLEARED ((uint8_t) 0x00) /* Freefall/Motion trigger bit is cleared. */
338 #define MMA845x_TRIG_CFG_TRIG_FF_MT_SET ((uint8_t) 0x04) /* Pulse interrupt trigger bit bit is set. */
339 #define MMA845x_TRIG_CFG_TRIG_PULSE_CLEARED ((uint8_t) 0x00) /* Pulse interrupt trigger bit is cleared. */
340 #define MMA845x_TRIG_CFG_TRIG_PULSE_SET ((uint8_t) 0x08) /* Pulse interrupt trigger bit is set. */
341 #define MMA845x_TRIG_CFG_TRIG_LNDPRT_CLEARED ((uint8_t) 0x00) /* Landscape/Portrait Orientation interrupt trigger bit */
342  /* is cleared. */
343 #define MMA845x_TRIG_CFG_TRIG_LNDPRT_SET ((uint8_t) 0x10) /* Landscape/Portrait Orientation interrupt trigger bit */
344  /* is set. */
345 #define MMA845x_TRIG_CFG_TRIG_TRANS_CLEARED ((uint8_t) 0x00) /* Transient interrupt trigger bit is cleared. */
346 #define MMA845x_TRIG_CFG_TRIG_TRANS_SET ((uint8_t) 0x20) /* Transient interrupt trigger bit is set. */
347 /*------------------------------*/
348 
349 
350 
351 /*--------------------------------
352 ** Register: SYSMOD
353 ** Enum: MMA845x_SYSMOD
354 ** --
355 ** Offset : 0x0B - System Mode Register indicates the current device operating mode.
356 ** ------------------------------*/
357 typedef union {
358  struct {
359  uint8_t sysmod : 2; /* - System mode data bits. */
360 
361  uint8_t fgt : 5; /* - Number of ODR time units since FGERR was asserted. Reset when FGERR */
362  /* Cleared. */
363 
364  uint8_t fgerr : 1; /* - FIFO Gate Error. */
365 
366  } b;
367  uint8_t w;
368 } MMA845x_SYSMOD_t;
369 
370 
371 /*
372 ** SYSMOD - Bit field mask definitions
373 */
374 #define MMA845x_SYSMOD_SYSMOD_MASK ((uint8_t) 0x03)
375 #define MMA845x_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0)
376 
377 #define MMA845x_SYSMOD_FGT_MASK ((uint8_t) 0x7C)
378 #define MMA845x_SYSMOD_FGT_SHIFT ((uint8_t) 2)
379 
380 #define MMA845x_SYSMOD_FGERR_MASK ((uint8_t) 0x80)
381 #define MMA845x_SYSMOD_FGERR_SHIFT ((uint8_t) 7)
382 
383 
384 /*
385 ** SYSMOD - Bit field value definitions
386 */
387 #define MMA845x_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* STANDBY Mode. */
388 #define MMA845x_SYSMOD_SYSMOD_WAKE ((uint8_t) 0x01) /* ACTIVE Mode. */
389 #define MMA845x_SYSMOD_SYSMOD_SLEEP ((uint8_t) 0x02) /* SLEEP Mode. */
390 #define MMA845x_SYSMOD_FGERR_NTDETECTED ((uint8_t) 0x00) /* No FIFO Gate Error detected. */
391 #define MMA845x_SYSMOD_FGERR_DETECTED ((uint8_t) 0x80) /* FIFO Gate Error was detected. */
392 /*------------------------------*/
393 
394 
395 
396 /*--------------------------------
397 ** Register: INT_SOURCE
398 ** Enum: MMA845x_INT_SOURCE
399 ** --
400 ** Offset : 0x0C - System Interrupt Status Register. The bits that are set (logic ‘1’) indicate which function has asserted its interrupt and conversely, bits that are cleared (logic ‘0’) indicate which function has not asserted its interrupt.
401 ** ------------------------------*/
402 typedef union {
403  struct {
404  uint8_t src_drdy : 1; /* Data Ready Interrupt bit status. */
405 
406  uint8_t _reserved_ : 1;
407  uint8_t src_ff_mt : 1; /* Freefall/Motion interrupt status bit. */
408 
409  uint8_t src_pulse : 1; /* Pulse interrupt status bit. */
410 
411  uint8_t src_lndprt : 1; /* Landscape/Portrait Orientation interrupt status bit. */
412 
413  uint8_t src_trans : 1; /* Transient interrupt status bit. */
414 
415  uint8_t src_fifo : 1; /* FIFO interrupt status bit. */
416 
417  uint8_t src_aslp : 1; /* Auto-SLEEP/WAKE interrupt status bit. */
418 
419  } b;
420  uint8_t w;
421 } MMA845x_INT_SOURCE_t;
422 
423 
424 /*
425 ** INT_SOURCE - Bit field mask definitions
426 */
427 #define MMA845x_INT_SOURCE_SRC_DRDY_MASK ((uint8_t) 0x01)
428 #define MMA845x_INT_SOURCE_SRC_DRDY_SHIFT ((uint8_t) 0)
429 
430 #define MMA845x_INT_SOURCE_SRC_FF_MT_MASK ((uint8_t) 0x04)
431 #define MMA845x_INT_SOURCE_SRC_FF_MT_SHIFT ((uint8_t) 2)
432 
433 #define MMA845x_INT_SOURCE_SRC_PULSE_MASK ((uint8_t) 0x08)
434 #define MMA845x_INT_SOURCE_SRC_PULSE_SHIFT ((uint8_t) 3)
435 
436 #define MMA845x_INT_SOURCE_SRC_LNDPRT_MASK ((uint8_t) 0x10)
437 #define MMA845x_INT_SOURCE_SRC_LNDPRT_SHIFT ((uint8_t) 4)
438 
439 #define MMA845x_INT_SOURCE_SRC_TRANS_MASK ((uint8_t) 0x20)
440 #define MMA845x_INT_SOURCE_SRC_TRANS_SHIFT ((uint8_t) 5)
441 
442 #define MMA845x_INT_SOURCE_SRC_FIFO_MASK ((uint8_t) 0x40)
443 #define MMA845x_INT_SOURCE_SRC_FIFO_SHIFT ((uint8_t) 6)
444 
445 #define MMA845x_INT_SOURCE_SRC_ASLP_MASK ((uint8_t) 0x80)
446 #define MMA845x_INT_SOURCE_SRC_ASLP_SHIFT ((uint8_t) 7)
447 
448 
449 /*------------------------------*/
450 
451 
452 
453 /*--------------------------------
454 ** Register: WHO_AM_I
455 ** Enum: MMA845x_WHO_AM_I
456 ** --
457 ** Offset : 0x0D - Fixed Device ID Number.
458 ** ------------------------------*/
459 typedef union {
460  struct {
461  uint8_t whoami; /* The WHO_AM_I register contains the device identifier which is factory */
462  /* programmed. */
463 
464  } b;
465  uint8_t w;
466 } MMA845x_WHO_AM_I_t;
467 
468 
469 /*
470 ** WHO_AM_I - Bit field mask definitions
471 */
472 #define MMA845x_WHO_AM_I_WHOAMI_MASK ((uint8_t) 0xFF)
473 #define MMA845x_WHO_AM_I_WHOAMI_SHIFT ((uint8_t) 0)
474 
475 
476 /*------------------------------*/
477 
478 
479 /*
480 ** WHO_AM_I - Bit field value definitions
481 */
482 #define MMA8451_WHO_AM_I_WHOAMI_VALUE ((uint8_t) 0x1a) /* Device identifier for MMA8451 */
483 #define MMA8452_WHO_AM_I_WHOAMI_VALUE ((uint8_t) 0x2a) /* Device identifier for MMA8452 */
484 #define MMA8453_WHO_AM_I_WHOAMI_VALUE ((uint8_t) 0x3a) /* Device identifier for MMA8452 */
485 /*------------------------------*/
486 
487 
488 
489 /*--------------------------------
490 ** Register: XYZ_DATA_CFG
491 ** Enum: MMA845x_XYZ_DATA_CFG
492 ** --
493 ** Offset : 0x0E - XYZ Data Configuration Register. sets the dynamic range and sets the high-pass filter for the output data.
494 ** ------------------------------*/
495 typedef union {
496  struct {
497  uint8_t fs : 2; /* Output buffer data format full scale. */
498 
499  uint8_t _reserved_ : 2;
500  uint8_t hpf_out : 1; /* Enable High-Pass output data. */
501 
502  } b;
503  uint8_t w;
504 } MMA845x_XYZ_DATA_CFG_t;
505 
506 
507 /*
508 ** XYZ_DATA_CFG - Bit field mask definitions
509 */
510 #define MMA845x_XYZ_DATA_CFG_FS_MASK ((uint8_t) 0x03)
511 #define MMA845x_XYZ_DATA_CFG_FS_SHIFT ((uint8_t) 0)
512 
513 #define MMA845x_XYZ_DATA_CFG_HPF_OUT_MASK ((uint8_t) 0x10)
514 #define MMA845x_XYZ_DATA_CFG_HPF_OUT_SHIFT ((uint8_t) 4)
515 
516 
517 /*
518 ** XYZ_DATA_CFG - Bit field value definitions
519 */
520 #define MMA845x_XYZ_DATA_CFG_FS_FS_RANGE_2G ((uint8_t) 0x00) /* Output buffer data full scale range is 2g. */
521 #define MMA845x_XYZ_DATA_CFG_FS_FS_RANGE_4G ((uint8_t) 0x01) /* Output buffer data full scale range is 4g. */
522 #define MMA845x_XYZ_DATA_CFG_FS_FS_RANGE_8G ((uint8_t) 0x02) /* Output buffer data full scale range is 8g. */
523 #define MMA845x_XYZ_DATA_CFG_HPF_OUT_DISABLED ((uint8_t) 0x00) /* High-Pass output data disabled. */
524 #define MMA845x_XYZ_DATA_CFG_HPF_OUT_ENABLED ((uint8_t) 0x10) /* High-Pass output data enabled. */
525 /*------------------------------*/
526 
527 
528 
529 /*--------------------------------
530 ** Register: HP_FILTER_CUTOFF
531 ** Enum: MMA845x_HP_FILTER_CUTOFF
532 ** --
533 ** Offset : 0x0F - HP_FILTER_CUTOFF High-Pass Filter Register. This register sets the high-pass filter cutoff frequency for removal of the offset and slower changing acceleration data.
534 ** ------------------------------*/
535 typedef union {
536  struct {
537  uint8_t sel : 2; /* HPF Cutoff frequency selection. */
538 
539  uint8_t _reserved_ : 2;
540  uint8_t pulse_lpf_en : 1; /* Enable Low-Pass Filter for Pulse Processing Function. */
541 
542  uint8_t pulse_hpf_byp : 1; /* Bypass High-Pass Filter for Pulse Processing Function. */
543 
544  } b;
545  uint8_t w;
546 } MMA845x_HP_FILTER_CUTOFF_t;
547 
548 
549 /*
550 ** HP_FILTER_CUTOFF - Bit field mask definitions
551 */
552 #define MMA845x_HP_FILTER_CUTOFF_SEL_MASK ((uint8_t) 0x03)
553 #define MMA845x_HP_FILTER_CUTOFF_SEL_SHIFT ((uint8_t) 0)
554 
555 #define MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_MASK ((uint8_t) 0x10)
556 #define MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_SHIFT ((uint8_t) 4)
557 
558 #define MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_MASK ((uint8_t) 0x20)
559 #define MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_SHIFT ((uint8_t) 5)
560 
561 
562 /*
563 ** HP_FILTER_CUTOFF - Bit field value definitions
564 */
565 #define MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_DISABLED ((uint8_t) 0x00) /* LPF disabled for Pulse Processing. */
566 #define MMA845x_HP_FILTER_CUTOFF_PULSE_LPF_EN_ENABLED ((uint8_t) 0x10) /* LPF Enabled for Pulse Processing. */
567 #define MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_DISABLED ((uint8_t) 0x00) /* HPF enabled for Pulse Processing. */
568 #define MMA845x_HP_FILTER_CUTOFF_PULSE_HPF_BYP_ENABLED ((uint8_t) 0x20) /* HPF Bypassed for Pulse Processing. */
569 /*------------------------------*/
570 
571 
572 
573 /*--------------------------------
574 ** Register: PL_STATUS
575 ** Enum: MMA845x_PL_STATUS
576 ** --
577 ** Offset : 0x10 - Portrait/Landscape Status Register.
578 ** ------------------------------*/
579 typedef union {
580  struct {
581  uint8_t bafro : 1; /* Back or Front orientation. */
582 
583  uint8_t lapo : 2; /* Landscape/Portrait orientation. */
584 
585  uint8_t _reserved_ : 3;
586  uint8_t lo : 1; /* Z-Tilt Angle Lockout. */
587 
588  uint8_t newlp : 1; /* Landscape/Portrait status change flag. */
589 
590  } b;
591  uint8_t w;
592 } MMA845x_PL_STATUS_t;
593 
594 
595 /*
596 ** PL_STATUS - Bit field mask definitions
597 */
598 #define MMA845x_PL_STATUS_BAFRO_MASK ((uint8_t) 0x01)
599 #define MMA845x_PL_STATUS_BAFRO_SHIFT ((uint8_t) 0)
600 
601 #define MMA845x_PL_STATUS_LAPO_MASK ((uint8_t) 0x06)
602 #define MMA845x_PL_STATUS_LAPO_SHIFT ((uint8_t) 1)
603 
604 #define MMA845x_PL_STATUS_LO_MASK ((uint8_t) 0x40)
605 #define MMA845x_PL_STATUS_LO_SHIFT ((uint8_t) 6)
606 
607 #define MMA845x_PL_STATUS_NEWLP_MASK ((uint8_t) 0x80)
608 #define MMA845x_PL_STATUS_NEWLP_SHIFT ((uint8_t) 7)
609 
610 
611 /*
612 ** PL_STATUS - Bit field value definitions
613 */
614 #define MMA845x_PL_STATUS_BAFRO_FRONT ((uint8_t) 0x00) /* Front: Equipment is in the front facing */
615  /* orientation. */
616 #define MMA845x_PL_STATUS_BAFRO_BACK ((uint8_t) 0x01) /* Back: Equipment is in the back facing orientation. */
617 #define MMA845x_PL_STATUS_LAPO_UP ((uint8_t) 0x00) /* Portrait Up: Equipment standing vertically in the */
618  /* normal orientation. */
619 #define MMA845x_PL_STATUS_LAPO_DOWN ((uint8_t) 0x02) /* Portrait Down: Equipment standing vertically in the */
620  /* inverted orientation. */
621 #define MMA845x_PL_STATUS_LAPO_RIGHT ((uint8_t) 0x04) /* Landscape Right: Equipment is in landscape mode to */
622  /* the right. */
623 #define MMA845x_PL_STATUS_LAPO_LEFT ((uint8_t) 0x06) /* Landscape Left: Equipment is in landscape mode to */
624  /* the left. */
625 #define MMA845x_PL_STATUS_LO_NOTDETECTED ((uint8_t) 0x00) /* Lockout condition has not been detected. */
626 #define MMA845x_PL_STATUS_LO_DETECTED ((uint8_t) 0x40) /* Z-Tilt lockout trip angle has been exceeded. */
627  /* Lockout has been detected. */
628 #define MMA845x_PL_STATUS_NEWLP_NOCHANGE ((uint8_t) 0x00) /* No change. */
629 #define MMA845x_PL_STATUS_NEWLP_DETECTED ((uint8_t) 0x80) /* BAFRO and/or LAPO and/or Z-Tilt lockout value has */
630  /* changed. */
631 /*------------------------------*/
632 
633 
634 
635 /*--------------------------------
636 ** Register: PL_CFG
637 ** Enum: MMA845x_PL_CFG
638 ** --
639 ** Offset : 0x11 - Portrait/Landscape Configuration Register.
640 ** ------------------------------*/
641 typedef union {
642  struct {
643  uint8_t reserved : 6; /* - Bits 5-0 are reserved, will always read 0. */
644 
645  uint8_t pl_en : 1; /* - Portrait/Landscape Detection Enable. */
646 
647  uint8_t dbcntm : 1; /* - Debounce counter mode selection. */
648 
649  } b;
650  uint8_t w;
651 } MMA845x_PL_CFG_t;
652 
653 
654 /*
655 ** PL_CFG - Bit field mask definitions
656 */
657 #define MMA845x_PL_CFG_RESERVED_MASK ((uint8_t) 0x3F)
658 #define MMA845x_PL_CFG_RESERVED_SHIFT ((uint8_t) 0)
659 
660 #define MMA845x_PL_CFG_PL_EN_MASK ((uint8_t) 0x40)
661 #define MMA845x_PL_CFG_PL_EN_SHIFT ((uint8_t) 6)
662 
663 #define MMA845x_PL_CFG_DBCNTM_MASK ((uint8_t) 0x80)
664 #define MMA845x_PL_CFG_DBCNTM_SHIFT ((uint8_t) 7)
665 
666 
667 /*
668 ** PL_CFG - Bit field value definitions
669 */
670 #define MMA845x_PL_CFG_PL_EN_DISABLED ((uint8_t) 0x00) /* Portrait/Landscape Detection is Disabled. */
671 #define MMA845x_PL_CFG_PL_EN_ENABLED ((uint8_t) 0x40) /* Portrait/Landscape Detection is Enabled. */
672 #define MMA845x_PL_CFG_DBCNTM_DEC ((uint8_t) 0x00) /* Decrements debounce whenever condition of interest is */
673  /* no longer valid. */
674 #define MMA845x_PL_CFG_DBCNTM_CLR ((uint8_t) 0x80) /* Clears counter whenever condition of interest is no */
675  /* longer valid. */
676 /*------------------------------*/
677 
678 
679 
680 /*--------------------------------
681 ** Register: PL_COUNT
682 ** Enum: MMA845x_PL_COUNT
683 ** --
684 ** Offset : 0x12 - Portrait/Landscape Debounce Counter.
685 ** ------------------------------*/
686 typedef union {
687  struct {
688  uint8_t dbcne; /* - Debounce Count value. */
689 
690  } b;
691  uint8_t w;
692 } MMA845x_PL_COUNT_t;
693 
694 
695 /*
696 ** PL_COUNT - Bit field mask definitions
697 */
698 #define MMA845x_PL_COUNT_DBCNE_MASK ((uint8_t) 0xFF)
699 #define MMA845x_PL_COUNT_DBCNE_SHIFT ((uint8_t) 0)
700 
701 
702 /*------------------------------*/
703 
704 
705 
706 /*--------------------------------
707 ** Register: PL_BF_ZCOMP
708 ** Enum: MMA845x_PL_BF_ZCOMP
709 ** --
710 ** Offset : 0x13 - Back/Front and Z Compensation Register.
711 ** ------------------------------*/
712 typedef union {
713  struct {
714  uint8_t zlock : 3; /* - Z-Lock Angle Fixed Threshold. */
715 
716  uint8_t _reserved_ : 3;
717  uint8_t bkfr : 2; /* - Back Front Trip Angle Fixed Threshold. */
718 
719  } b;
720  uint8_t w;
721 } MMA845x_PL_BF_ZCOMP_t;
722 
723 
724 /*
725 ** PL_BF_ZCOMP - Bit field mask definitions
726 */
727 #define MMA845x_PL_BF_ZCOMP_ZLOCK_MASK ((uint8_t) 0x07)
728 #define MMA845x_PL_BF_ZCOMP_ZLOCK_SHIFT ((uint8_t) 0)
729 
730 #define MMA845x_PL_BF_ZCOMP_BKFR_MASK ((uint8_t) 0xC0)
731 #define MMA845x_PL_BF_ZCOMP_BKFR_SHIFT ((uint8_t) 6)
732 
733 
734 /*
735 ** PL_BF_ZCOMP - Bit field value definitions
736 */
737 #define MMA845x_PL_BF_ZCOMP_ZLOCK_THR ((uint8_t) 0x64) /* Z-Lock angle compensation is set to 29°. */
738 #define MMA845x_PL_BF_ZCOMP_BKFR_THR ((uint8_t) 0x40) /* Back to Front trip angle is set to ±75°. */
739 /*------------------------------*/
740 
741 
742 
743 /*--------------------------------
744 ** Register: PL_THS_REG
745 ** Enum: MMA845x_PL_THS_REG
746 ** --
747 ** Offset : 0x14 - Portrait/Landscape Threshold and Hysteresis Register.
748 ** ------------------------------*/
749 typedef union {
750  struct {
751  uint8_t hys : 3; /* - Hysteresis, This is a fixed angle added to the threshold angle for a */
752  /* smoother transition from Portrait to Landscape and Landscape to Portrait. */
753 
754  uint8_t pl_ths : 5; /* - Portrait/Landscape Fixed Threshold angle. */
755 
756  } b;
757  uint8_t w;
758 } MMA845x_PL_THS_REG_t;
759 
760 
761 /*
762 ** PL_THS_REG - Bit field mask definitions
763 */
764 #define MMA845x_PL_THS_REG_HYS_MASK ((uint8_t) 0x07)
765 #define MMA845x_PL_THS_REG_HYS_SHIFT ((uint8_t) 0)
766 
767 #define MMA845x_PL_THS_REG_PL_THS_MASK ((uint8_t) 0xF8)
768 #define MMA845x_PL_THS_REG_PL_THS_SHIFT ((uint8_t) 3)
769 
770 
771 /*
772 ** PL_THS_REG - Bit field value definitions
773 */
774 #define MMA845x_PL_THS_REG_HYS_THR ((uint8_t) 0x64) /* Hysteresis angle is fixed at ±14°, which is 100. */
775 #define MMA845x_PL_THS_REG_PL_THS_THR ((uint8_t) 0x80) /* Portrait/Landscape Fixed Threshold angle = 1_0000 */
776  /* (45°). */
777 /*------------------------------*/
778 
779 
780 
781 /*--------------------------------
782 ** Register: FF_MT_CFG
783 ** Enum: MMA845x_FF_MT_CFG
784 ** --
785 ** Offset : 0x15 - Freefall/Motion Configuration Register.
786 ** ------------------------------*/
787 typedef union {
788  struct {
789  uint8_t reserved : 3; /* - Bits 2-0 are reserved, will always read 0. */
790 
791  uint8_t xefe : 1; /* - Event flag enable on X event. */
792 
793  uint8_t yefe : 1; /* - Event flag enable on Y event. */
794 
795  uint8_t zefe : 1; /* - Event flag enable on Z event. */
796 
797  uint8_t oae : 1; /* - Motion detect / Freefall detect flag selection. */
798 
799  uint8_t ele : 1; /* - Event Latch Enable. */
800 
801  } b;
802  uint8_t w;
803 } MMA845x_FF_MT_CFG_t;
804 
805 
806 /*
807 ** FF_MT_CFG - Bit field mask definitions
808 */
809 #define MMA845x_FF_MT_CFG_RESERVED_MASK ((uint8_t) 0x07)
810 #define MMA845x_FF_MT_CFG_RESERVED_SHIFT ((uint8_t) 0)
811 
812 #define MMA845x_FF_MT_CFG_XEFE_MASK ((uint8_t) 0x08)
813 #define MMA845x_FF_MT_CFG_XEFE_SHIFT ((uint8_t) 3)
814 
815 #define MMA845x_FF_MT_CFG_YEFE_MASK ((uint8_t) 0x10)
816 #define MMA845x_FF_MT_CFG_YEFE_SHIFT ((uint8_t) 4)
817 
818 #define MMA845x_FF_MT_CFG_ZEFE_MASK ((uint8_t) 0x20)
819 #define MMA845x_FF_MT_CFG_ZEFE_SHIFT ((uint8_t) 5)
820 
821 #define MMA845x_FF_MT_CFG_OAE_MASK ((uint8_t) 0x40)
822 #define MMA845x_FF_MT_CFG_OAE_SHIFT ((uint8_t) 6)
823 
824 #define MMA845x_FF_MT_CFG_ELE_MASK ((uint8_t) 0x80)
825 #define MMA845x_FF_MT_CFG_ELE_SHIFT ((uint8_t) 7)
826 
827 
828 /*
829 ** FF_MT_CFG - Bit field value definitions
830 */
831 #define MMA845x_FF_MT_CFG_XEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
832 #define MMA845x_FF_MT_CFG_XEFE_ENABLED ((uint8_t) 0x08) /* Raise event flag on measured acceleration value */
833  /* beyond preset threshold. */
834 #define MMA845x_FF_MT_CFG_YEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
835 #define MMA845x_FF_MT_CFG_YEFE_ENABLED ((uint8_t) 0x10) /* Raise event flag on measured acceleration value */
836  /* beyond preset threshold. */
837 #define MMA845x_FF_MT_CFG_ZEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
838 #define MMA845x_FF_MT_CFG_ZEFE_ENABLED ((uint8_t) 0x20) /* Raise event flag on measured acceleration value */
839  /* beyond preset threshold. */
840 #define MMA845x_FF_MT_CFG_OAE_FREEFALL ((uint8_t) 0x00) /* Freefall Flag. */
841 #define MMA845x_FF_MT_CFG_OAE_MOTION ((uint8_t) 0x00) /* Motion Flag. */
842 #define MMA845x_FF_MT_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */
843 #define MMA845x_FF_MT_CFG_ELE_ENABLED ((uint8_t) 0x80) /* Event flag latch enabled. */
844 /*------------------------------*/
845 
846 
847 
848 /*--------------------------------
849 ** Register: FF_MT_SRC
850 ** Enum: MMA845x_FF_MT_SRC
851 ** --
852 ** Offset : 0x16 - Freefall/Motion Source Register.
853 ** ------------------------------*/
854 typedef union {
855  struct {
856  uint8_t xhp : 1; /* - Event flag enable on X event. */
857 
858  uint8_t xhe : 1; /* - Event flag enable on Y event. */
859 
860  uint8_t yhp : 1; /* - Event flag enable on Z event. */
861 
862  uint8_t yhe : 1; /* - Motion detect / Freefall detect flag selection. */
863 
864  uint8_t zhp : 1; /* - Event Latch Enable. */
865 
866  uint8_t zhe : 1; /* - Event Latch Enable. */
867 
868  uint8_t _reserved_ : 1;
869  uint8_t ea : 1; /* - Event Latch Enable. */
870 
871  } b;
872  uint8_t w;
873 } MMA845x_FF_MT_SRC_t;
874 
875 
876 /*
877 ** FF_MT_SRC - Bit field mask definitions
878 */
879 #define MMA845x_FF_MT_SRC_XHP_MASK ((uint8_t) 0x01)
880 #define MMA845x_FF_MT_SRC_XHP_SHIFT ((uint8_t) 0)
881 
882 #define MMA845x_FF_MT_SRC_XHE_MASK ((uint8_t) 0x02)
883 #define MMA845x_FF_MT_SRC_XHE_SHIFT ((uint8_t) 1)
884 
885 #define MMA845x_FF_MT_SRC_YHP_MASK ((uint8_t) 0x04)
886 #define MMA845x_FF_MT_SRC_YHP_SHIFT ((uint8_t) 2)
887 
888 #define MMA845x_FF_MT_SRC_YHE_MASK ((uint8_t) 0x08)
889 #define MMA845x_FF_MT_SRC_YHE_SHIFT ((uint8_t) 3)
890 
891 #define MMA845x_FF_MT_SRC_ZHP_MASK ((uint8_t) 0x10)
892 #define MMA845x_FF_MT_SRC_ZHP_SHIFT ((uint8_t) 4)
893 
894 #define MMA845x_FF_MT_SRC_ZHE_MASK ((uint8_t) 0x20)
895 #define MMA845x_FF_MT_SRC_ZHE_SHIFT ((uint8_t) 5)
896 
897 #define MMA845x_FF_MT_SRC_EA_MASK ((uint8_t) 0x80)
898 #define MMA845x_FF_MT_SRC_EA_SHIFT ((uint8_t) 7)
899 
900 
901 /*
902 ** FF_MT_SRC - Bit field value definitions
903 */
904 #define MMA845x_FF_MT_SRC_XHP_POSITIVE ((uint8_t) 0x00) /* X event was Positive. */
905 #define MMA845x_FF_MT_SRC_XHP_NEGATIVE ((uint8_t) 0x01) /* X event was Negative. */
906 #define MMA845x_FF_MT_SRC_XHE_NOTDETECTED ((uint8_t) 0x00) /* No X Motion event detected. */
907 #define MMA845x_FF_MT_SRC_XHE_DETECTED ((uint8_t) 0x02) /* X Motion has been detected. */
908 #define MMA845x_FF_MT_SRC_YHP_POSITIVE ((uint8_t) 0x00) /* Y event was Positive. */
909 #define MMA845x_FF_MT_SRC_YHP_NEGATIVE ((uint8_t) 0x04) /* Y event was Negative. */
910 #define MMA845x_FF_MT_SRC_YHE_NOTDETECTED ((uint8_t) 0x00) /* No Y Motion event detected. */
911 #define MMA845x_FF_MT_SRC_YHE_DETECTED ((uint8_t) 0x08) /* Y Motion has been detected. */
912 #define MMA845x_FF_MT_SRC_ZHP_POSITIVE ((uint8_t) 0x00) /* Z event was Positive. */
913 #define MMA845x_FF_MT_SRC_ZHP_NEGATIVE ((uint8_t) 0x10) /* Z event was Negative. */
914 #define MMA845x_FF_MT_SRC_ZHE_NOTDETECTED ((uint8_t) 0x00) /* No Z Motion event detected. */
915 #define MMA845x_FF_MT_SRC_ZHE_DETECTED ((uint8_t) 0x20) /* Z Motion has been detected. */
916 #define MMA845x_FF_MT_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No event flag has been asserted. */
917 #define MMA845x_FF_MT_SRC_EA_DETECTED ((uint8_t) 0x80) /* one or more event flag has been asserted. */
918 /*------------------------------*/
919 
920 
921 
922 /*--------------------------------
923 ** Register: FF_MT_THS
924 ** Enum: MMA845x_FF_MT_THS
925 ** --
926 ** Offset : 0x17 - Freefall and Motion Threshold Register.
927 ** ------------------------------*/
928 typedef union {
929  struct {
930  uint8_t ths : 7; /* - Freefall /Motion Threshold. */
931 
932  uint8_t dbcntm : 1; /* - Debounce counter mode selection. */
933 
934  } b;
935  uint8_t w;
936 } MMA845x_FF_MT_THS_t;
937 
938 
939 /*
940 ** FF_MT_THS - Bit field mask definitions
941 */
942 #define MMA845x_FF_MT_THS_THS_MASK ((uint8_t) 0x7F)
943 #define MMA845x_FF_MT_THS_THS_SHIFT ((uint8_t) 0)
944 
945 #define MMA845x_FF_MT_THS_DBCNTM_MASK ((uint8_t) 0x80)
946 #define MMA845x_FF_MT_THS_DBCNTM_SHIFT ((uint8_t) 7)
947 
948 
949 /*
950 ** FF_MT_THS - Bit field value definitions
951 */
952 #define MMA845x_FF_MT_THS_DBCNTM_DEC ((uint8_t) 0x00) /* Increments or decrements debounce. */
953 #define MMA845x_FF_MT_THS_DBCNTM_CLR ((uint8_t) 0x80) /* Increments or clears counter. */
954 /*------------------------------*/
955 
956 
957 
958 /*--------------------------------
959 ** Register: FF_MT_COUNT
960 ** Enum: MMA845x_FF_MT_COUNT
961 ** --
962 ** Offset : 0x18 - Debounce Register.
963 ** ------------------------------*/
964 typedef union {
965  struct {
966  uint8_t d; /* - Count value. */
967 
968  } b;
969  uint8_t w;
970 } MMA845x_FF_MT_COUNT_t;
971 
972 
973 /*
974 ** FF_MT_COUNT - Bit field mask definitions
975 */
976 #define MMA845x_FF_MT_COUNT_D_MASK ((uint8_t) 0xFF)
977 #define MMA845x_FF_MT_COUNT_D_SHIFT ((uint8_t) 0)
978 
979 
980 /*------------------------------*/
981 
982 
983 
984 /*--------------------------------
985 ** Register: TRANSIENT_CFG
986 ** Enum: MMA845x_TRANSIENT_CFG
987 ** --
988 ** Offset : 0x1D - Transient_CFG Register.
989 ** ------------------------------*/
990 typedef union {
991  struct {
992  uint8_t hpf_byp : 1; /* - Bypass High-Pass filter. */
993 
994  uint8_t xtefe : 1; /* - Event flag enable on X transient acceleration greater than transient */
995  /* threshold event. */
996 
997  uint8_t ytefe : 1; /* - Event flag enable on Y transient acceleration greater than transient */
998  /* threshold event. */
999 
1000  uint8_t ztefe : 1; /* - Event flag enable on Z transient acceleration greater than transient */
1001  /* threshold event. */
1002 
1003  uint8_t ele : 1; /* - Transient event flags are latched into the TRANSIENT_SRC register. */
1004 
1005  uint8_t reserved : 3; /* - Bits 7-5 are reserved, will always read 0. */
1006 
1007  } b;
1008  uint8_t w;
1009 } MMA845x_TRANSIENT_CFG_t;
1010 
1011 
1012 /*
1013 ** TRANSIENT_CFG - Bit field mask definitions
1014 */
1015 #define MMA845x_TRANSIENT_CFG_HPF_BYP_MASK ((uint8_t) 0x01)
1016 #define MMA845x_TRANSIENT_CFG_HPF_BYP_SHIFT ((uint8_t) 0)
1017 
1018 #define MMA845x_TRANSIENT_CFG_XTEFE_MASK ((uint8_t) 0x02)
1019 #define MMA845x_TRANSIENT_CFG_XTEFE_SHIFT ((uint8_t) 1)
1020 
1021 #define MMA845x_TRANSIENT_CFG_YTEFE_MASK ((uint8_t) 0x04)
1022 #define MMA845x_TRANSIENT_CFG_YTEFE_SHIFT ((uint8_t) 2)
1023 
1024 #define MMA845x_TRANSIENT_CFG_ZTEFE_MASK ((uint8_t) 0x08)
1025 #define MMA845x_TRANSIENT_CFG_ZTEFE_SHIFT ((uint8_t) 3)
1026 
1027 #define MMA845x_TRANSIENT_CFG_ELE_MASK ((uint8_t) 0x10)
1028 #define MMA845x_TRANSIENT_CFG_ELE_SHIFT ((uint8_t) 4)
1029 
1030 #define MMA845x_TRANSIENT_CFG_RESERVED_MASK ((uint8_t) 0xE0)
1031 #define MMA845x_TRANSIENT_CFG_RESERVED_SHIFT ((uint8_t) 5)
1032 
1033 
1034 /*
1035 ** TRANSIENT_CFG - Bit field value definitions
1036 */
1037 #define MMA845x_TRANSIENT_CFG_HPF_BYP_THROUGH ((uint8_t) 0x00) /* Data to transient acceleration detection block */
1038  /* is through HPF. */
1039 #define MMA845x_TRANSIENT_CFG_HPF_BYP_BYPASS ((uint8_t) 0x01) /* Data to transient acceleration detection block */
1040  /* is NOT through HPF. */
1041 #define MMA845x_TRANSIENT_CFG_XTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1042 #define MMA845x_TRANSIENT_CFG_XTEFE_ENABLED ((uint8_t) 0x02) /* Raise event flag on measured acceleration delta */
1043  /* value greater than transient threshold. */
1044 #define MMA845x_TRANSIENT_CFG_YTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1045 #define MMA845x_TRANSIENT_CFG_YTEFE_ENABLED ((uint8_t) 0x04) /* Raise event flag on measured acceleration delta */
1046  /* value greater than transient threshold. */
1047 #define MMA845x_TRANSIENT_CFG_ZTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1048 #define MMA845x_TRANSIENT_CFG_ZTEFE_ENABLED ((uint8_t) 0x08) /* Raise event flag on measured acceleration delta */
1049  /* value greater than transient threshold. */
1050 #define MMA845x_TRANSIENT_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */
1051 #define MMA845x_TRANSIENT_CFG_ELE_ENABLED ((uint8_t) 0x10) /* Event flag latch enabled. */
1052 /*------------------------------*/
1053 
1054 
1055 
1056 /*--------------------------------
1057 ** Register: TRANSIENT_SRC
1058 ** Enum: MMA845x_TRANSIENT_SRC
1059 ** --
1060 ** Offset : 0x1E - Transient_SRC Register.
1061 ** ------------------------------*/
1062 typedef union {
1063  struct {
1064  uint8_t x_trans_pol : 1; /* - Polarity of X Transient Event that triggered interrupt. */
1065 
1066  uint8_t xtrans : 1; /* - X transient event. */
1067 
1068  uint8_t y_trans_pol : 1; /* - Polarity of Y Transient Event that triggered interrupt. */
1069 
1070  uint8_t ytrans : 1; /* - Y transient event. */
1071 
1072  uint8_t z_trans_pol : 1; /* - Polarity of Z Transient Event that triggered interrupt. */
1073 
1074  uint8_t ztrans : 1; /* - Z transient event. */
1075 
1076  uint8_t ea : 1; /* - Event Active Flag. */
1077 
1078  } b;
1079  uint8_t w;
1080 } MMA845x_TRANSIENT_SRC_t;
1081 
1082 
1083 /*
1084 ** TRANSIENT_SRC - Bit field mask definitions
1085 */
1086 #define MMA845x_TRANSIENT_SRC_X_TRANS_POL_MASK ((uint8_t) 0x01)
1087 #define MMA845x_TRANSIENT_SRC_X_TRANS_POL_SHIFT ((uint8_t) 0)
1088 
1089 #define MMA845x_TRANSIENT_SRC_XTRANS_MASK ((uint8_t) 0x02)
1090 #define MMA845x_TRANSIENT_SRC_XTRANS_SHIFT ((uint8_t) 1)
1091 
1092 #define MMA845x_TRANSIENT_SRC_Y_TRANS_POL_MASK ((uint8_t) 0x04)
1093 #define MMA845x_TRANSIENT_SRC_Y_TRANS_POL_SHIFT ((uint8_t) 2)
1094 
1095 #define MMA845x_TRANSIENT_SRC_YTRANS_MASK ((uint8_t) 0x08)
1096 #define MMA845x_TRANSIENT_SRC_YTRANS_SHIFT ((uint8_t) 3)
1097 
1098 #define MMA845x_TRANSIENT_SRC_Z_TRANS_POL_MASK ((uint8_t) 0x10)
1099 #define MMA845x_TRANSIENT_SRC_Z_TRANS_POL_SHIFT ((uint8_t) 4)
1100 
1101 #define MMA845x_TRANSIENT_SRC_ZTRANS_MASK ((uint8_t) 0x20)
1102 #define MMA845x_TRANSIENT_SRC_ZTRANS_SHIFT ((uint8_t) 5)
1103 
1104 #define MMA845x_TRANSIENT_SRC_EA_MASK ((uint8_t) 0x40)
1105 #define MMA845x_TRANSIENT_SRC_EA_SHIFT ((uint8_t) 6)
1106 
1107 
1108 /*
1109 ** TRANSIENT_SRC - Bit field value definitions
1110 */
1111 #define MMA845x_TRANSIENT_SRC_X_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* X event was Positive. */
1112 #define MMA845x_TRANSIENT_SRC_X_TRANS_POL_NEGATIVE ((uint8_t) 0x01) /* X event was Negative. */
1113 #define MMA845x_TRANSIENT_SRC_XTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */
1114 #define MMA845x_TRANSIENT_SRC_XTRANS_DETECTED ((uint8_t) 0x02) /* X Transient acceleration greater than the value */
1115  /* of TRANSIENT_THS event has occurred. */
1116 #define MMA845x_TRANSIENT_SRC_Y_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* Y event was Positive. */
1117 #define MMA845x_TRANSIENT_SRC_Y_TRANS_POL_NEGATIVE ((uint8_t) 0x04) /* Y event was Negative. */
1118 #define MMA845x_TRANSIENT_SRC_YTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */
1119 #define MMA845x_TRANSIENT_SRC_YTRANS_DETECTED ((uint8_t) 0x08) /* Y Transient acceleration greater than the value */
1120  /* of TRANSIENT_THS event has occurred. */
1121 #define MMA845x_TRANSIENT_SRC_Z_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* Z event was Positive. */
1122 #define MMA845x_TRANSIENT_SRC_Z_TRANS_POL_NEGATIVE ((uint8_t) 0x10) /* Z event was Negative. */
1123 #define MMA845x_TRANSIENT_SRC_ZTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */
1124 #define MMA845x_TRANSIENT_SRC_ZTRANS_DETECTED ((uint8_t) 0x20) /* Z Transient acceleration greater than the value */
1125  /* of TRANSIENT_THS event has occurred. */
1126 #define MMA845x_TRANSIENT_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No event flag has been asserted. */
1127 #define MMA845x_TRANSIENT_SRC_EA_DETECTED ((uint8_t) 0x40) /* one or more event flag has been asserted. */
1128 /*------------------------------*/
1129 
1130 
1131 
1132 /*--------------------------------
1133 ** Register: TRANSIENT_THS
1134 ** Enum: MMA845x_TRANSIENT_THS
1135 ** --
1136 ** Offset : 0x1F - TRANSIENT_THS Register.
1137 ** ------------------------------*/
1138 typedef union {
1139  struct {
1140  uint8_t ths : 7; /* - Transient Threshold. */
1141 
1142  uint8_t dbcntm : 1; /* - Debounce counter mode selection. */
1143 
1144  } b;
1145  uint8_t w;
1146 } MMA845x_TRANSIENT_THS_t;
1147 
1148 
1149 /*
1150 ** TRANSIENT_THS - Bit field mask definitions
1151 */
1152 #define MMA845x_TRANSIENT_THS_THS_MASK ((uint8_t) 0x7F)
1153 #define MMA845x_TRANSIENT_THS_THS_SHIFT ((uint8_t) 0)
1154 
1155 #define MMA845x_TRANSIENT_THS_DBCNTM_MASK ((uint8_t) 0x80)
1156 #define MMA845x_TRANSIENT_THS_DBCNTM_SHIFT ((uint8_t) 7)
1157 
1158 
1159 /*
1160 ** TRANSIENT_THS - Bit field value definitions
1161 */
1162 #define MMA845x_TRANSIENT_THS_DBCNTM_DEC ((uint8_t) 0x00) /* Increments or decrements debounce. */
1163 #define MMA845x_TRANSIENT_THS_DBCNTM_CLR ((uint8_t) 0x80) /* Increments or clears counter. */
1164 /*------------------------------*/
1165 
1166 
1167 
1168 /*--------------------------------
1169 ** Register: TRANSIENT_COUNT
1170 ** Enum: MMA845x_TRANSIENT_COUNT
1171 ** --
1172 ** Offset : 0x20 - TRANSIENT_COUNT Register.
1173 ** ------------------------------*/
1174 typedef union {
1175  struct {
1176  uint8_t d; /* - Count value. */
1177 
1178  } b;
1179  uint8_t w;
1180 } MMA845x_TRANSIENT_COUNT_t;
1181 
1182 
1183 /*
1184 ** TRANSIENT_COUNT - Bit field mask definitions
1185 */
1186 #define MMA845x_TRANSIENT_COUNT_D_MASK ((uint8_t) 0xFF)
1187 #define MMA845x_TRANSIENT_COUNT_D_SHIFT ((uint8_t) 0)
1188 
1189 
1190 /*------------------------------*/
1191 
1192 
1193 
1194 /*--------------------------------
1195 ** Register: PULSE_CFG
1196 ** Enum: MMA845x_PULSE_CFG
1197 ** --
1198 ** Offset : 0x21 - Pulse Configuration Register.
1199 ** ------------------------------*/
1200 typedef union {
1201  struct {
1202  uint8_t xspefe : 1; /* - Event flag enable on single pulse event on X-axis. */
1203 
1204  uint8_t xdpefe : 1; /* - Event flag enable on double pulse event on X-axis. */
1205 
1206  uint8_t yspefe : 1; /* - Event flag enable on single pulse event on Y-axis. */
1207 
1208  uint8_t ydpefe : 1; /* - Event flag enable on double pulse event on Y-axis. */
1209 
1210  uint8_t zspefe : 1; /* - Event flag enable on single pulse event on Z-axis. */
1211 
1212  uint8_t zdpefe : 1; /* - Event flag enable on double pulse event on Z-axis. */
1213 
1214  uint8_t ele : 1; /* - Pulse event flags are latched into the PULSE_SRC register. */
1215 
1216  uint8_t dpa : 1; /* - Double Pulse Abort. */
1217 
1218  } b;
1219  uint8_t w;
1220 } MMA845x_PULSE_CFG_t;
1221 
1222 
1223 /*
1224 ** PULSE_CFG - Bit field mask definitions
1225 */
1226 #define MMA845x_PULSE_CFG_XSPEFE_MASK ((uint8_t) 0x01)
1227 #define MMA845x_PULSE_CFG_XSPEFE_SHIFT ((uint8_t) 0)
1228 
1229 #define MMA845x_PULSE_CFG_XDPEFE_MASK ((uint8_t) 0x02)
1230 #define MMA845x_PULSE_CFG_XDPEFE_SHIFT ((uint8_t) 1)
1231 
1232 #define MMA845x_PULSE_CFG_YSPEFE_MASK ((uint8_t) 0x04)
1233 #define MMA845x_PULSE_CFG_YSPEFE_SHIFT ((uint8_t) 2)
1234 
1235 #define MMA845x_PULSE_CFG_YDPEFE_MASK ((uint8_t) 0x08)
1236 #define MMA845x_PULSE_CFG_YDPEFE_SHIFT ((uint8_t) 3)
1237 
1238 #define MMA845x_PULSE_CFG_ZSPEFE_MASK ((uint8_t) 0x10)
1239 #define MMA845x_PULSE_CFG_ZSPEFE_SHIFT ((uint8_t) 4)
1240 
1241 #define MMA845x_PULSE_CFG_ZDPEFE_MASK ((uint8_t) 0x20)
1242 #define MMA845x_PULSE_CFG_ZDPEFE_SHIFT ((uint8_t) 5)
1243 
1244 #define MMA845x_PULSE_CFG_ELE_MASK ((uint8_t) 0x40)
1245 #define MMA845x_PULSE_CFG_ELE_SHIFT ((uint8_t) 6)
1246 
1247 #define MMA845x_PULSE_CFG_DPA_MASK ((uint8_t) 0x80)
1248 #define MMA845x_PULSE_CFG_DPA_SHIFT ((uint8_t) 7)
1249 
1250 
1251 /*
1252 ** PULSE_CFG - Bit field value definitions
1253 */
1254 #define MMA845x_PULSE_CFG_XSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1255 #define MMA845x_PULSE_CFG_XSPEFE_ENABLED ((uint8_t) 0x01) /* Event detection enabled. */
1256 #define MMA845x_PULSE_CFG_XDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1257 #define MMA845x_PULSE_CFG_XDPEFE_ENABLED ((uint8_t) 0x02) /* Event detection enabled. */
1258 #define MMA845x_PULSE_CFG_YSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1259 #define MMA845x_PULSE_CFG_YSPEFE_ENABLED ((uint8_t) 0x04) /* Event detection enabled. */
1260 #define MMA845x_PULSE_CFG_YDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1261 #define MMA845x_PULSE_CFG_YDPEFE_ENABLED ((uint8_t) 0x08) /* Event detection enabled. */
1262 #define MMA845x_PULSE_CFG_ZSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1263 #define MMA845x_PULSE_CFG_ZSPEFE_ENABLED ((uint8_t) 0x10) /* Event detection enabled. */
1264 #define MMA845x_PULSE_CFG_ZDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1265 #define MMA845x_PULSE_CFG_ZDPEFE_ENABLED ((uint8_t) 0x20) /* Event detection enabled. */
1266 #define MMA845x_PULSE_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */
1267 #define MMA845x_PULSE_CFG_ELE_ENABLED ((uint8_t) 0x40) /* Event flag latch enabled. */
1268 #define MMA845x_PULSE_CFG_DPA_DISABLED ((uint8_t) 0x00) /* Double Pulse detection is not aborted if the start */
1269  /* of a pulse is detected. */
1270 #define MMA845x_PULSE_CFG_DPA_ENABLED ((uint8_t) 0x80) /* Double tap detection is aborted if the start of a */
1271  /* pulse is detected. */
1272 /*------------------------------*/
1273 
1274 
1275 
1276 /*--------------------------------
1277 ** Register: PULSE_SRC
1278 ** Enum: MMA845x_PULSE_SRC
1279 ** --
1280 ** Offset : 0x22 - Pulse Source Register.
1281 ** ------------------------------*/
1282 typedef union {
1283  struct {
1284  uint8_t polx : 1; /* - Pulse polarity of X-axis Event. */
1285 
1286  uint8_t poly : 1; /* - Pulse polarity of Y-axis Event. */
1287 
1288  uint8_t polz : 1; /* - Pulse polarity of Z-axis Event. */
1289 
1290  uint8_t dpe : 1; /* - Double pulse on first event. */
1291 
1292  uint8_t axx : 1; /* - X-axis event. */
1293 
1294  uint8_t axy : 1; /* - Y-axis event. */
1295 
1296  uint8_t axz : 1; /* - Z-axis event. */
1297 
1298  uint8_t ea : 1; /* - Event Active Flag. */
1299 
1300  } b;
1301  uint8_t w;
1302 } MMA845x_PULSE_SRC_t;
1303 
1304 
1305 /*
1306 ** PULSE_SRC - Bit field mask definitions
1307 */
1308 #define MMA845x_PULSE_SRC_POLX_MASK ((uint8_t) 0x01)
1309 #define MMA845x_PULSE_SRC_POLX_SHIFT ((uint8_t) 0)
1310 
1311 #define MMA845x_PULSE_SRC_POLY_MASK ((uint8_t) 0x02)
1312 #define MMA845x_PULSE_SRC_POLY_SHIFT ((uint8_t) 1)
1313 
1314 #define MMA845x_PULSE_SRC_POLZ_MASK ((uint8_t) 0x04)
1315 #define MMA845x_PULSE_SRC_POLZ_SHIFT ((uint8_t) 2)
1316 
1317 #define MMA845x_PULSE_SRC_DPE_MASK ((uint8_t) 0x08)
1318 #define MMA845x_PULSE_SRC_DPE_SHIFT ((uint8_t) 3)
1319 
1320 #define MMA845x_PULSE_SRC_AXX_MASK ((uint8_t) 0x10)
1321 #define MMA845x_PULSE_SRC_AXX_SHIFT ((uint8_t) 4)
1322 
1323 #define MMA845x_PULSE_SRC_AXY_MASK ((uint8_t) 0x20)
1324 #define MMA845x_PULSE_SRC_AXY_SHIFT ((uint8_t) 5)
1325 
1326 #define MMA845x_PULSE_SRC_AXZ_MASK ((uint8_t) 0x40)
1327 #define MMA845x_PULSE_SRC_AXZ_SHIFT ((uint8_t) 6)
1328 
1329 #define MMA845x_PULSE_SRC_EA_MASK ((uint8_t) 0x80)
1330 #define MMA845x_PULSE_SRC_EA_SHIFT ((uint8_t) 7)
1331 
1332 
1333 /*
1334 ** PULSE_SRC - Bit field value definitions
1335 */
1336 #define MMA845x_PULSE_SRC_POLX_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was Positive. */
1337 #define MMA845x_PULSE_SRC_POLX_NEGATIVE ((uint8_t) 0x01) /* Pulse Event that triggered interrupt was negative. */
1338 #define MMA845x_PULSE_SRC_POLY_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was Positive. */
1339 #define MMA845x_PULSE_SRC_POLY_NEGATIVE ((uint8_t) 0x02) /* Pulse Event that triggered interrupt was negative. */
1340 #define MMA845x_PULSE_SRC_POLZ_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was Positive. */
1341 #define MMA845x_PULSE_SRC_POLZ_NEGATIVE ((uint8_t) 0x04) /* Pulse Event that triggered interrupt was negative. */
1342 #define MMA845x_PULSE_SRC_DPE_SINGLEPULSE ((uint8_t) 0x00) /* Single Pulse Event triggered interrupt. */
1343 #define MMA845x_PULSE_SRC_DPE_DOUBLEPULSE ((uint8_t) 0x08) /* Double Pulse event triggered interrupt. */
1344 #define MMA845x_PULSE_SRC_AXX_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */
1345 #define MMA845x_PULSE_SRC_AXX_DETECTED ((uint8_t) 0x10) /* X-axis event has occurred. */
1346 #define MMA845x_PULSE_SRC_AXY_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */
1347 #define MMA845x_PULSE_SRC_AXY_DETECTED ((uint8_t) 0x20) /* Y-axis event has occurred. */
1348 #define MMA845x_PULSE_SRC_AXZ_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */
1349 #define MMA845x_PULSE_SRC_AXZ_DETECTED ((uint8_t) 0x40) /* Z-axis event has occurred. */
1350 #define MMA845x_PULSE_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No interrupt has been generated. */
1351 #define MMA845x_PULSE_SRC_EA_DETECTED ((uint8_t) 0x80) /* One or more event flag has been asserted. */
1352 /*------------------------------*/
1353 
1354 
1355 
1356 /*--------------------------------
1357 ** Register: PULSE_THSX
1358 ** Enum: MMA845x_PULSE_THSX
1359 ** --
1360 ** Offset : 0x23 - Pulse Threshold for X.
1361 ** ------------------------------*/
1362 typedef union {
1363  struct {
1364  uint8_t thsx : 7; /* - Pulse Threshold on X-axis. */
1365 
1366  uint8_t reserved : 1; /* - Bit 8 is reserved, will always read 0. */
1367 
1368  } b;
1369  uint8_t w;
1370 } MMA845x_PULSE_THSX_t;
1371 
1372 
1373 /*
1374 ** PULSE_THSX - Bit field mask definitions
1375 */
1376 #define MMA845x_PULSE_THSX_THSX_MASK ((uint8_t) 0x7F)
1377 #define MMA845x_PULSE_THSX_THSX_SHIFT ((uint8_t) 0)
1378 
1379 #define MMA845x_PULSE_THSX_RESERVED_MASK ((uint8_t) 0x80)
1380 #define MMA845x_PULSE_THSX_RESERVED_SHIFT ((uint8_t) 7)
1381 
1382 
1383 /*------------------------------*/
1384 
1385 
1386 
1387 /*--------------------------------
1388 ** Register: PULSE_THSY
1389 ** Enum: MMA845x_PULSE_THSY
1390 ** --
1391 ** Offset : 0x24 - Pulse Threshold for Y.
1392 ** ------------------------------*/
1393 typedef union {
1394  struct {
1395  uint8_t thsy : 7; /* - Pulse Threshold on Y-axis. */
1396 
1397  uint8_t reserved : 1; /* - Bit 8 is reserved, will always read 0. */
1398 
1399  } b;
1400  uint8_t w;
1401 } MMA845x_PULSE_THSY_t;
1402 
1403 
1404 /*
1405 ** PULSE_THSY - Bit field mask definitions
1406 */
1407 #define MMA845x_PULSE_THSY_THSY_MASK ((uint8_t) 0x7F)
1408 #define MMA845x_PULSE_THSY_THSY_SHIFT ((uint8_t) 0)
1409 
1410 #define MMA845x_PULSE_THSY_RESERVED_MASK ((uint8_t) 0x80)
1411 #define MMA845x_PULSE_THSY_RESERVED_SHIFT ((uint8_t) 7)
1412 
1413 
1414 /*------------------------------*/
1415 
1416 
1417 
1418 /*--------------------------------
1419 ** Register: PULSE_THSZ
1420 ** Enum: MMA845x_PULSE_THSZ
1421 ** --
1422 ** Offset : 0x25 - Pulse Threshold for Z.
1423 ** ------------------------------*/
1424 typedef union {
1425  struct {
1426  uint8_t thsz : 7; /* - Pulse Threshold on Z-axis. */
1427 
1428  uint8_t reserved : 1; /* - Bit 8 is reserved, will always read 0. */
1429 
1430  } b;
1431  uint8_t w;
1432 } MMA845x_PULSE_THSZ_t;
1433 
1434 
1435 /*
1436 ** PULSE_THSZ - Bit field mask definitions
1437 */
1438 #define MMA845x_PULSE_THSZ_THSZ_MASK ((uint8_t) 0x7F)
1439 #define MMA845x_PULSE_THSZ_THSZ_SHIFT ((uint8_t) 0)
1440 
1441 #define MMA845x_PULSE_THSZ_RESERVED_MASK ((uint8_t) 0x80)
1442 #define MMA845x_PULSE_THSZ_RESERVED_SHIFT ((uint8_t) 7)
1443 
1444 
1445 /*------------------------------*/
1446 
1447 
1448 
1449 /*--------------------------------
1450 ** Register: PULSE_TMLT
1451 ** Enum: MMA845x_PULSE_TMLT
1452 ** --
1453 ** Offset : 0x26 - Pulse Time Window 1 Register.
1454 ** ------------------------------*/
1455 typedef union {
1456  struct {
1457  uint8_t tmlt; /* - Pulse Time Limit. */
1458 
1459  } b;
1460  uint8_t w;
1461 } MMA845x_PULSE_TMLT_t;
1462 
1463 
1464 /*
1465 ** PULSE_TMLT - Bit field mask definitions
1466 */
1467 #define MMA845x_PULSE_TMLT_TMLT_MASK ((uint8_t) 0xFF)
1468 #define MMA845x_PULSE_TMLT_TMLT_SHIFT ((uint8_t) 0)
1469 
1470 
1471 /*------------------------------*/
1472 
1473 
1474 
1475 /*--------------------------------
1476 ** Register: PULSE_LTCY
1477 ** Enum: MMA845x_PULSE_LTCY
1478 ** --
1479 ** Offset : 0x27 - Pulse Latency Timer Register.
1480 ** ------------------------------*/
1481 typedef union {
1482  struct {
1483  uint8_t ltcy; /* - Latency Time Limit. */
1484 
1485  } b;
1486  uint8_t w;
1487 } MMA845x_PULSE_LTCY_t;
1488 
1489 
1490 /*
1491 ** PULSE_LTCY - Bit field mask definitions
1492 */
1493 #define MMA845x_PULSE_LTCY_LTCY_MASK ((uint8_t) 0xFF)
1494 #define MMA845x_PULSE_LTCY_LTCY_SHIFT ((uint8_t) 0)
1495 
1496 
1497 /*------------------------------*/
1498 
1499 
1500 
1501 /*--------------------------------
1502 ** Register: PULSE_WIND
1503 ** Enum: MMA845x_PULSE_WIND
1504 ** --
1505 ** Offset : 0x28 - Second Pulse Time Window Register.
1506 ** ------------------------------*/
1507 typedef union {
1508  struct {
1509  uint8_t wind; /* - Second Pulse Time Window. */
1510 
1511  } b;
1512  uint8_t w;
1513 } MMA845x_PULSE_WIND_t;
1514 
1515 
1516 /*
1517 ** PULSE_WIND - Bit field mask definitions
1518 */
1519 #define MMA845x_PULSE_WIND_WIND_MASK ((uint8_t) 0xFF)
1520 #define MMA845x_PULSE_WIND_WIND_SHIFT ((uint8_t) 0)
1521 
1522 
1523 /*------------------------------*/
1524 
1525 
1526 
1527 /*--------------------------------
1528 ** Register: ASLP_COUNT
1529 ** Enum: MMA845x_ASLP_COUNT
1530 ** --
1531 ** Offset : 0x29 - Auto-WAKE/SLEEP count Register.
1532 ** ------------------------------*/
1533 typedef union {
1534  struct {
1535  uint8_t d; /* - Duration value. */
1536 
1537  } b;
1538  uint8_t w;
1539 } MMA845x_ASLP_COUNT_t;
1540 
1541 
1542 /*
1543 ** ASLP_COUNT - Bit field mask definitions
1544 */
1545 #define MMA845x_ASLP_COUNT_D_MASK ((uint8_t) 0xFF)
1546 #define MMA845x_ASLP_COUNT_D_SHIFT ((uint8_t) 0)
1547 
1548 
1549 /*------------------------------*/
1550 
1551 
1552 
1553 /*--------------------------------
1554 ** Register: CTRL_REG1
1555 ** Enum: MMA845x_CTRL_REG1
1556 ** --
1557 ** Offset : 0x2A - System Control 1 Register.
1558 ** ------------------------------*/
1559 typedef union {
1560  struct {
1561  uint8_t mode : 1; /* - Full Scale selection. */
1562 
1563  uint8_t f_read : 1; /* - Fast Read mode. */
1564 
1565  uint8_t lnoise : 1; /* - Reduced noise reduced Maximum range mode. */
1566 
1567  uint8_t dr : 3; /* - Data rate selection. */
1568 
1569  uint8_t aslp_rate : 2; /* - Configures the Auto-WAKE sample frequency when the device is in SLEEP */
1570  /* Mode. */
1571 
1572  } b;
1573  uint8_t w;
1574 } MMA845x_CTRL_REG1_t;
1575 
1576 
1577 /*
1578 ** CTRL_REG1 - Bit field mask definitions
1579 */
1580 #define MMA845x_CTRL_REG1_MODE_MASK ((uint8_t) 0x01)
1581 #define MMA845x_CTRL_REG1_MODE_SHIFT ((uint8_t) 0)
1582 
1583 #define MMA845x_CTRL_REG1_F_READ_MASK ((uint8_t) 0x02)
1584 #define MMA845x_CTRL_REG1_F_READ_SHIFT ((uint8_t) 1)
1585 
1586 #define MMA845x_CTRL_REG1_LNOISE_MASK ((uint8_t) 0x04)
1587 #define MMA845x_CTRL_REG1_LNOISE_SHIFT ((uint8_t) 2)
1588 
1589 #define MMA845x_CTRL_REG1_DR_MASK ((uint8_t) 0x38)
1590 #define MMA845x_CTRL_REG1_DR_SHIFT ((uint8_t) 3)
1591 
1592 #define MMA845x_CTRL_REG1_ASLP_RATE_MASK ((uint8_t) 0xC0)
1593 #define MMA845x_CTRL_REG1_ASLP_RATE_SHIFT ((uint8_t) 6)
1594 
1595 
1596 /*
1597 ** CTRL_REG1 - Bit field value definitions
1598 */
1599 #define MMA845x_CTRL_REG1_MODE_STANDBY ((uint8_t) 0x00) /* STANDBY mode. */
1600 #define MMA845x_CTRL_REG1_MODE_ACTIVE ((uint8_t) 0x01) /* ACTIVE mode. */
1601 #define MMA845x_CTRL_REG1_F_READ_NORMAL ((uint8_t) 0x00) /* Normal mode. */
1602 #define MMA845x_CTRL_REG1_F_READ_FASTREAD ((uint8_t) 0x02) /* Fast Read Mode. */
1603 #define MMA845x_CTRL_REG1_LNOISE_NORMAL ((uint8_t) 0x00) /* Normal mode. */
1604 #define MMA845x_CTRL_REG1_LNOISE_REDUCED ((uint8_t) 0x04) /* Reduced Noise mode. */
1605 #define MMA845x_CTRL_REG1_DR_800HZ ((uint8_t) 0x00) /* 800HZ ODR. */
1606 #define MMA845x_CTRL_REG1_DR_400HZ ((uint8_t) 0x08) /* 400HZ ODR. */
1607 #define MMA845x_CTRL_REG1_DR_200HZ ((uint8_t) 0x10) /* 200HZ ODR. */
1608 #define MMA845x_CTRL_REG1_DR_100HZ ((uint8_t) 0x18) /* 100HZ ODR. */
1609 #define MMA845x_CTRL_REG1_DR_50HZ ((uint8_t) 0x20) /* 50HZ ODR. */
1610 #define MMA845x_CTRL_REG1_DR_12DOT5HZ ((uint8_t) 0x28) /* 12.5HZ ODR. */
1611 #define MMA845x_CTRL_REG1_DR_6DOT25HZ ((uint8_t) 0x30) /* 6.25HZ ODR. */
1612 #define MMA845x_CTRL_REG1_DR_1DOT56HZ ((uint8_t) 0x38) /* 1.56HZ ODR. */
1613 #define MMA845x_CTRL_REG1_ASLP_RATE_50HZ ((uint8_t) 0x00) /* 800HZ. */
1614 #define MMA845x_CTRL_REG1_ASLP_RATE_12DOT5HZ ((uint8_t) 0x40) /* 12.5HZ. */
1615 #define MMA845x_CTRL_REG1_ASLP_RATE_6DOT25HZ ((uint8_t) 0x80) /* 6.25HZ. */
1616 #define MMA845x_CTRL_REG1_ASLP_RATE_1DOT56HZ ((uint8_t) 0xc0) /* 1.56HZ. */
1617 /*------------------------------*/
1618 
1619 
1620 
1621 /*--------------------------------
1622 ** Register: CTRL_REG2
1623 ** Enum: MMA845x_CTRL_REG2
1624 ** --
1625 ** Offset : 0x2B - System Control 2 Register.
1626 ** ------------------------------*/
1627 typedef union {
1628  struct {
1629  uint8_t mods : 2; /* - ACTIVE mode power scheme selection. */
1630 
1631  uint8_t slpe : 1; /* - Auto-SLEEP enable. */
1632 
1633  uint8_t smods : 2; /* - SLEEP mode power scheme selection. */
1634 
1635  uint8_t _reserved_ : 1;
1636  uint8_t rst : 1; /* - Software Reset. */
1637 
1638  uint8_t st : 1; /* - Self-Test Enable. */
1639 
1640  } b;
1641  uint8_t w;
1642 } MMA845x_CTRL_REG2_t;
1643 
1644 
1645 /*
1646 ** CTRL_REG2 - Bit field mask definitions
1647 */
1648 #define MMA845x_CTRL_REG2_MODS_MASK ((uint8_t) 0x03)
1649 #define MMA845x_CTRL_REG2_MODS_SHIFT ((uint8_t) 0)
1650 
1651 #define MMA845x_CTRL_REG2_SLPE_MASK ((uint8_t) 0x04)
1652 #define MMA845x_CTRL_REG2_SLPE_SHIFT ((uint8_t) 2)
1653 
1654 #define MMA845x_CTRL_REG2_SMODS_MASK ((uint8_t) 0x18)
1655 #define MMA845x_CTRL_REG2_SMODS_SHIFT ((uint8_t) 3)
1656 
1657 #define MMA845x_CTRL_REG2_RST_MASK ((uint8_t) 0x40)
1658 #define MMA845x_CTRL_REG2_RST_SHIFT ((uint8_t) 6)
1659 
1660 #define MMA845x_CTRL_REG2_ST_MASK ((uint8_t) 0x80)
1661 #define MMA845x_CTRL_REG2_ST_SHIFT ((uint8_t) 7)
1662 
1663 
1664 /*
1665 ** CTRL_REG2 - Bit field value definitions
1666 */
1667 #define MMA845x_CTRL_REG2_MODS_NORMAL ((uint8_t) 0x00) /* Normal power mode. */
1668 #define MMA845x_CTRL_REG2_MODS_LOWNOISE ((uint8_t) 0x01) /* Low Noise Low Power mode. */
1669 #define MMA845x_CTRL_REG2_MODS_HIGHRES ((uint8_t) 0x02) /* High Resolution mode. */
1670 #define MMA845x_CTRL_REG2_MODS_LOWPOW ((uint8_t) 0x03) /* Low Power mode. */
1671 #define MMA845x_CTRL_REG2_SLPE_DISABLED ((uint8_t) 0x00) /* Auto-SLEEP is not enabled. */
1672 #define MMA845x_CTRL_REG2_SLPE_ENABLED ((uint8_t) 0x04) /* Auto-SLEEP is enabled. */
1673 #define MMA845x_CTRL_REG2_SMODS_NORMAL ((uint8_t) 0x00) /* Normal power mode. */
1674 #define MMA845x_CTRL_REG2_SMODS_LOWNOISE ((uint8_t) 0x08) /* Low Noise Low Power mode. */
1675 #define MMA845x_CTRL_REG2_SMODS_HIGHRES ((uint8_t) 0x10) /* High Resolution mode. */
1676 #define MMA845x_CTRL_REG2_SMODS_LOWPOW ((uint8_t) 0x18) /* Low Power mode. */
1677 #define MMA845x_CTRL_REG2_RST_DISABLED ((uint8_t) 0x00) /* Device reset disabled. */
1678 #define MMA845x_CTRL_REG2_RST_ENABLED ((uint8_t) 0x40) /* Device reset enabled. */
1679 #define MMA845x_CTRL_REG2_ST_DISABLED ((uint8_t) 0x00) /* Self-Test disabled;. */
1680 #define MMA845x_CTRL_REG2_ST_ENABLED ((uint8_t) 0x80) /* Self-Test enabled. */
1681 /*------------------------------*/
1682 
1683 
1684 
1685 /*--------------------------------
1686 ** Register: CTRL_REG3
1687 ** Enum: MMA845x_CTRL_REG3
1688 ** --
1689 ** Offset : 0x2C - Interrupt Control Register.
1690 ** ------------------------------*/
1691 typedef union {
1692  struct {
1693  uint8_t pp_od : 1; /* - Push-Pull/Open Drain selection on interrupt pad. */
1694 
1695  uint8_t ipol : 1; /* - Interrupt polarity ACTIVE high, or ACTIVE low. */
1696 
1697  uint8_t _reserved_ : 1;
1698  uint8_t wake_ff_mt : 1; /* - Freefall/Motion wake up interrupt. */
1699 
1700  uint8_t wake_pulse : 1; /* - Pulse wake up interrupt. */
1701 
1702  uint8_t wake_lndprt : 1; /* - Orientation wake up interrupt. */
1703 
1704  uint8_t wake_trans : 1; /* - Transient wake up interrupt. */
1705 
1706  uint8_t fifo_gate : 1; /* - FIFO Gate wake up interrupt. */
1707 
1708  } b;
1709  uint8_t w;
1710 } MMA845x_CTRL_REG3_t;
1711 
1712 
1713 /*
1714 ** CTRL_REG3 - Bit field mask definitions
1715 */
1716 #define MMA845x_CTRL_REG3_PP_OD_MASK ((uint8_t) 0x01)
1717 #define MMA845x_CTRL_REG3_PP_OD_SHIFT ((uint8_t) 0)
1718 
1719 #define MMA845x_CTRL_REG3_IPOL_MASK ((uint8_t) 0x02)
1720 #define MMA845x_CTRL_REG3_IPOL_SHIFT ((uint8_t) 1)
1721 
1722 #define MMA845x_CTRL_REG3_WAKE_FF_MT_MASK ((uint8_t) 0x08)
1723 #define MMA845x_CTRL_REG3_WAKE_FF_MT_SHIFT ((uint8_t) 3)
1724 
1725 #define MMA845x_CTRL_REG3_WAKE_PULSE_MASK ((uint8_t) 0x10)
1726 #define MMA845x_CTRL_REG3_WAKE_PULSE_SHIFT ((uint8_t) 4)
1727 
1728 #define MMA845x_CTRL_REG3_WAKE_LNDPRT_MASK ((uint8_t) 0x20)
1729 #define MMA845x_CTRL_REG3_WAKE_LNDPRT_SHIFT ((uint8_t) 5)
1730 
1731 #define MMA845x_CTRL_REG3_WAKE_TRANS_MASK ((uint8_t) 0x40)
1732 #define MMA845x_CTRL_REG3_WAKE_TRANS_SHIFT ((uint8_t) 6)
1733 
1734 #define MMA845x_CTRL_REG3_FIFO_GATE_MASK ((uint8_t) 0x80)
1735 #define MMA845x_CTRL_REG3_FIFO_GATE_SHIFT ((uint8_t) 7)
1736 
1737 
1738 /*
1739 ** CTRL_REG3 - Bit field value definitions
1740 */
1741 #define MMA845x_CTRL_REG3_PP_OD_PUSHPULL ((uint8_t) 0x00) /* Push-Pull. */
1742 #define MMA845x_CTRL_REG3_PP_OD_OPENDRAIN ((uint8_t) 0x01) /* Open Drain. */
1743 #define MMA845x_CTRL_REG3_IPOL_LOW ((uint8_t) 0x00) /* ACTIVE low. */
1744 #define MMA845x_CTRL_REG3_IPOL_HIGH ((uint8_t) 0x02) /* ACTIVE high. */
1745 #define MMA845x_CTRL_REG3_WAKE_FF_MT_BYPASS ((uint8_t) 0x00) /* Freefall/Motion function is bypassed in SLEEP mode. */
1746 #define MMA845x_CTRL_REG3_WAKE_FF_MT_WAKEUP ((uint8_t) 0x08) /* Freefall/Motion function interrupt can wake up. */
1747 #define MMA845x_CTRL_REG3_WAKE_PULSE_BYPASS ((uint8_t) 0x00) /* Pulse function is bypassed in SLEEP mode. */
1748 #define MMA845x_CTRL_REG3_WAKE_PULSE_WAKEUP ((uint8_t) 0x10) /* Pulse function interrupt can wake up. */
1749 #define MMA845x_CTRL_REG3_WAKE_LNDPRT_BYPASS ((uint8_t) 0x00) /* Orientation function is bypassed in SLEEP mode. */
1750 #define MMA845x_CTRL_REG3_WAKE_LNDPRT_WAKEUP ((uint8_t) 0x20) /* Orientation function interrupt can wake up. */
1751 #define MMA845x_CTRL_REG3_WAKE_TRANS_BYPASS ((uint8_t) 0x00) /* Transient function is bypassed in SLEEP mode. */
1752 #define MMA845x_CTRL_REG3_WAKE_TRANS_WAKEUP ((uint8_t) 0x40) /* Transient function interrupt can wake up. */
1753 #define MMA845x_CTRL_REG3_FIFO_GATE_BYPASS ((uint8_t) 0x00) /* FIFO gate is bypassed. FIFO is flushed upon the */
1754  /* system mode transitioning from WAKE to SLEEP mode */
1755  /* or from SLEEP to WAKE mode. */
1756 #define MMA845x_CTRL_REG3_FIFO_GATE_WAKEUP ((uint8_t) 0x80) /* The FIFO input buffer is blocked when transitioning */
1757  /* from WAKE to SLEEP mode or from SLEEP to WAKE mode */
1758  /* until the FIFO is flushed. */
1759 /*------------------------------*/
1760 
1761 
1762 
1763 /*--------------------------------
1764 ** Register: CTRL_REG4
1765 ** Enum: MMA845x_CTRL_REG4
1766 ** --
1767 ** Offset : 0x2D - Interrupt Enable register (Read/Write).
1768 ** ------------------------------*/
1769 typedef union {
1770  struct {
1771  uint8_t int_en_drdy : 1; /* - Interrupt Enable. */
1772 
1773  uint8_t _reserved_ : 1;
1774  uint8_t int_en_ff_mt : 1; /* - Interrupt Enable. */
1775 
1776  uint8_t int_en_pulse : 1; /* - Interrupt Enable. */
1777 
1778  uint8_t int_en_lndprt : 1; /* - Interrupt Enable. */
1779 
1780  uint8_t int_en_trans : 1; /* - Interrupt Enable. */
1781 
1782  uint8_t int_en_fifo : 1; /* - Interrupt Enable. */
1783 
1784  uint8_t int_en_aslp : 1; /* - Interrupt Enable. */
1785 
1786  } b;
1787  uint8_t w;
1788 } MMA845x_CTRL_REG4_t;
1789 
1790 
1791 /*
1792 ** CTRL_REG4 - Bit field mask definitions
1793 */
1794 #define MMA845x_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x01)
1795 #define MMA845x_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 0)
1796 
1797 #define MMA845x_CTRL_REG4_INT_EN_FF_MT_MASK ((uint8_t) 0x04)
1798 #define MMA845x_CTRL_REG4_INT_EN_FF_MT_SHIFT ((uint8_t) 2)
1799 
1800 #define MMA845x_CTRL_REG4_INT_EN_PULSE_MASK ((uint8_t) 0x08)
1801 #define MMA845x_CTRL_REG4_INT_EN_PULSE_SHIFT ((uint8_t) 3)
1802 
1803 #define MMA845x_CTRL_REG4_INT_EN_LNDPRT_MASK ((uint8_t) 0x10)
1804 #define MMA845x_CTRL_REG4_INT_EN_LNDPRT_SHIFT ((uint8_t) 4)
1805 
1806 #define MMA845x_CTRL_REG4_INT_EN_TRANS_MASK ((uint8_t) 0x20)
1807 #define MMA845x_CTRL_REG4_INT_EN_TRANS_SHIFT ((uint8_t) 5)
1808 
1809 #define MMA845x_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40)
1810 #define MMA845x_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6)
1811 
1812 #define MMA845x_CTRL_REG4_INT_EN_ASLP_MASK ((uint8_t) 0x80)
1813 #define MMA845x_CTRL_REG4_INT_EN_ASLP_SHIFT ((uint8_t) 7)
1814 
1815 
1816 /*
1817 ** CTRL_REG4 - Bit field value definitions
1818 */
1819 #define MMA845x_CTRL_REG4_INT_EN_DRDY_DISABLED ((uint8_t) 0x00) /* Data Ready interrupt disabled. */
1820 #define MMA845x_CTRL_REG4_INT_EN_DRDY_ENABLED ((uint8_t) 0x01) /* Data Ready interrupt enabled. */
1821 #define MMA845x_CTRL_REG4_INT_EN_FF_MT_DISABLED ((uint8_t) 0x00) /* Freefall/Motion interrupt disabled. */
1822 #define MMA845x_CTRL_REG4_INT_EN_FF_MT_ENABLED ((uint8_t) 0x04) /* Freefall/Motion interrupt enabled. */
1823 #define MMA845x_CTRL_REG4_INT_EN_PULSE_DISABLED ((uint8_t) 0x00) /* Pulse Detection interrupt disabled. */
1824 #define MMA845x_CTRL_REG4_INT_EN_PULSE_ENABLED ((uint8_t) 0x08) /* Pulse Detection interrupt enabled. */
1825 #define MMA845x_CTRL_REG4_INT_EN_LNDPRT_DISABLED ((uint8_t) 0x00) /* Orientation (Landscape/Portrait) interrupt */
1826  /* disabled. */
1827 #define MMA845x_CTRL_REG4_INT_EN_LNDPRT_ENABLED ((uint8_t) 0x10) /* Orientation (Landscape/Portrait) interrupt enabled. */
1828 #define MMA845x_CTRL_REG4_INT_EN_TRANS_DISABLED ((uint8_t) 0x00) /* Transient interrupt disabled. */
1829 #define MMA845x_CTRL_REG4_INT_EN_TRANS_ENABLED ((uint8_t) 0x20) /* Transient interrupt enabled. */
1830 #define MMA845x_CTRL_REG4_INT_EN_FIFO_DISABLED ((uint8_t) 0x00) /* FIFO interrupt disabled. */
1831 #define MMA845x_CTRL_REG4_INT_EN_FIFO_ENABLED ((uint8_t) 0x40) /* FIFO interrupt enabled. */
1832 #define MMA845x_CTRL_REG4_INT_EN_ASLP_DISABLED ((uint8_t) 0x00) /* Auto-SLEEP/WAKE interrupt disabled. */
1833 #define MMA845x_CTRL_REG4_INT_EN_ASLP_ENABLED ((uint8_t) 0x80) /* Auto-SLEEP/WAKE interrupt enabled. */
1834 /*------------------------------*/
1835 
1836 
1837 
1838 /*--------------------------------
1839 ** Register: CTRL_REG5
1840 ** Enum: MMA845x_CTRL_REG5
1841 ** --
1842 ** Offset : 0x2E - Interrupt Configuration Register.
1843 ** ------------------------------*/
1844 typedef union {
1845  struct {
1846  uint8_t int_cfg_drdy : 1; /* - INT1/INT2 Configuration. */
1847 
1848  uint8_t _reserved_ : 1;
1849  uint8_t int_cfg_ff_mt : 1; /* - INT1/INT2 Configuration. */
1850 
1851  uint8_t int_cfg_pulse : 1; /* - INT1/INT2 Configuration. */
1852 
1853  uint8_t int_cfg_lndprt : 1; /* - INT1/INT2 Configuration. */
1854 
1855  uint8_t int_cfg_trans : 1; /* - INT1/INT2 Configuration. */
1856 
1857  uint8_t int_cfg_fifo : 1; /* - INT1/INT2 Configuration. */
1858 
1859  uint8_t int_cfg_aslp : 1; /* - INT1/INT2 Configuration. */
1860 
1861  } b;
1862  uint8_t w;
1863 } MMA845x_CTRL_REG5_t;
1864 
1865 
1866 /*
1867 ** CTRL_REG5 - Bit field mask definitions
1868 */
1869 #define MMA845x_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x01)
1870 #define MMA845x_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 0)
1871 
1872 #define MMA845x_CTRL_REG5_INT_CFG_FF_MT_MASK ((uint8_t) 0x04)
1873 #define MMA845x_CTRL_REG5_INT_CFG_FF_MT_SHIFT ((uint8_t) 2)
1874 
1875 #define MMA845x_CTRL_REG5_INT_CFG_PULSE_MASK ((uint8_t) 0x08)
1876 #define MMA845x_CTRL_REG5_INT_CFG_PULSE_SHIFT ((uint8_t) 3)
1877 
1878 #define MMA845x_CTRL_REG5_INT_CFG_LNDPRT_MASK ((uint8_t) 0x10)
1879 #define MMA845x_CTRL_REG5_INT_CFG_LNDPRT_SHIFT ((uint8_t) 4)
1880 
1881 #define MMA845x_CTRL_REG5_INT_CFG_TRANS_MASK ((uint8_t) 0x20)
1882 #define MMA845x_CTRL_REG5_INT_CFG_TRANS_SHIFT ((uint8_t) 5)
1883 
1884 #define MMA845x_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40)
1885 #define MMA845x_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6)
1886 
1887 #define MMA845x_CTRL_REG5_INT_CFG_ASLP_MASK ((uint8_t) 0x80)
1888 #define MMA845x_CTRL_REG5_INT_CFG_ASLP_SHIFT ((uint8_t) 7)
1889 
1890 
1891 /*
1892 ** CTRL_REG5 - Bit field value definitions
1893 */
1894 #define MMA845x_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1895 #define MMA845x_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 pin. */
1896 #define MMA845x_CTRL_REG5_INT_CFG_FF_MT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1897 #define MMA845x_CTRL_REG5_INT_CFG_FF_MT_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 pin. */
1898 #define MMA845x_CTRL_REG5_INT_CFG_PULSE_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1899 #define MMA845x_CTRL_REG5_INT_CFG_PULSE_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 pin. */
1900 #define MMA845x_CTRL_REG5_INT_CFG_LNDPRT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1901 #define MMA845x_CTRL_REG5_INT_CFG_LNDPRT_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 pin. */
1902 #define MMA845x_CTRL_REG5_INT_CFG_TRANS_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1903 #define MMA845x_CTRL_REG5_INT_CFG_TRANS_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 pin. */
1904 #define MMA845x_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1905 #define MMA845x_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 pin. */
1906 #define MMA845x_CTRL_REG5_INT_CFG_ASLP_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1907 #define MMA845x_CTRL_REG5_INT_CFG_ASLP_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 pin. */
1908 /*------------------------------*/
1909 
1910 
1911 
1912 /*--------------------------------
1913 ** Register: OFF_X
1914 ** Enum: MMA845x_OFF_X
1915 ** --
1916 ** Offset : 0x2F - Offset Correction X Register.
1917 ** ------------------------------*/
1918 typedef union {
1919  struct {
1920  uint8_t d; /* - X-axis offset value. */
1921 
1922  } b;
1923  uint8_t w;
1924 } MMA845x_OFF_X_t;
1925 
1926 
1927 /*
1928 ** OFF_X - Bit field mask definitions
1929 */
1930 #define MMA845x_OFF_X_D_MASK ((uint8_t) 0xFF)
1931 #define MMA845x_OFF_X_D_SHIFT ((uint8_t) 0)
1932 
1933 
1934 /*------------------------------*/
1935 
1936 
1937 
1938 /*--------------------------------
1939 ** Register: OFF_Y
1940 ** Enum: MMA845x_OFF_Y
1941 ** --
1942 ** Offset : 0x30 - Offset Correction Y Register.
1943 ** ------------------------------*/
1944 typedef union {
1945  struct {
1946  uint8_t d; /* - Y-axis offset value. */
1947 
1948  } b;
1949  uint8_t w;
1950 } MMA845x_OFF_Y_t;
1951 
1952 
1953 /*
1954 ** OFF_Y - Bit field mask definitions
1955 */
1956 #define MMA845x_OFF_Y_D_MASK ((uint8_t) 0xFF)
1957 #define MMA845x_OFF_Y_D_SHIFT ((uint8_t) 0)
1958 
1959 
1960 /*------------------------------*/
1961 
1962 
1963 
1964 /*--------------------------------
1965 ** Register: OFF_Z
1966 ** Enum: MMA845x_OFF_Z
1967 ** --
1968 ** Offset : 0x31 - Offset Correction Z Register.
1969 ** ------------------------------*/
1970 typedef union {
1971  struct {
1972  uint8_t d; /* - Z-axis offset value. */
1973 
1974  } b;
1975  uint8_t w;
1976 } MMA845x_OFF_Z_t;
1977 
1978 
1979 /*
1980 ** OFF_Z - Bit field mask definitions
1981 */
1982 #define MMA845x_OFF_Z_D_MASK ((uint8_t) 0xFF)
1983 #define MMA845x_OFF_Z_D_SHIFT ((uint8_t) 0)
1984 
1985 
1986 /*------------------------------*/
1987 
1988 
1989 #endif /* _MMA845x_H_ */
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