ISSDK  1.8
IoT Sensing Software Development Kit
fxls8471q.h
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 /**
10  * @file fxls8471q.h
11  * @brief The fxls8471q.h file contains the register definitions for fxls8471q sensor driver.
12  */
13 
14 #ifndef FXLS8471Q_H_
15 #define FXLS8471Q_H_
16 
17 /**
18  ** FXLS8471Q I2C Address
19  */
20 #define FXLS8471Q_I2C_ADDRESS_SA0_0_SA1_0 0x1E /*fxls8471q Address - SA0 = 0 and SA1 = 0*/
21 #define FXLS8471Q_I2C_ADDRESS_SA0_1_SA1_0 0x1D /*fxls8471q Address - SA0 = 1 and SA1 = 0*/
22 #define FXLS8471Q_I2C_ADDRESS_SA0_0_SA1_1 0x1C /*fxls8471q Address - SA0 = 0 and SA1 = 1*/
23 #define FXLS8471Q_I2C_ADDRESS_SA0_1_SA1_1 0x1F /*fxls8471q Address - SA0 = 1 and SA1 = 1*/
24 
25 /**
26  **
27  ** fxls8471q Sensor Internal Registers
28  */
29 enum {
30  FXLS8471Q_STATUS = 0x00, /* FMODE = 0, real time status */
31  FXLS8471Q_F_STATUS = 0x00, /* FMODE > 0, FIFO status */
32  FXLS8471Q_OUT_X_MSB = 0x01, /* data registers */
33  FXLS8471Q_OUT_X_LSB = 0x02, /* data registers */
34  FXLS8471Q_OUT_Y_MSB = 0x03, /* data registers */
35  FXLS8471Q_OUT_Y_LSB = 0x04, /* data registers */
36  FXLS8471Q_OUT_Z_MSB = 0x05, /* data registers */
37  FXLS8471Q_OUT_Z_LSB = 0x06, /* data registers */
38  FXLS8471Q_F_SETUP = 0x09, /* FIFO setup */
39  FXLS8471Q_TRIG_CFG = 0x0A, /* Map of FIFO data capture events */
40  FXLS8471Q_SYSMOD = 0x0B, /* SYSMOD System Mode register */
41  FXLS8471Q_INT_SOURCE = 0x0C, /* INT_SOURCE System Interrupt Status register */
42  FXLS8471Q_WHO_AM_I = 0x0D, /* WHO_AM_I Device ID register */
43  FXLS8471Q_XYZ_DATA_CFG = 0x0E, /* XYZ_DATA_CFG register */
44  FXLS8471Q_HP_FILTER_CUTOFF = 0x0F, /* FXLS8471Q only */
45  FXLS8471Q_PL_STATUS = 0x10, /* PL_STATUS Portrait/Landscape Status register */
46  FXLS8471Q_PL_CFG = 0x11, /* Portrait/Landscape Configuration register */
47  FXLS8471Q_PL_COUNT = 0x12, /* Portrait/Landscape Debounce register */
48  FXLS8471Q_PL_BF_ZCOMP = 0x13, /* PL_BF_ZCOMP Back/Front and Z Compensation register */
49  FXLS8471Q_PL_THS_REG = 0x14, /* P_L_THS_REG Portrait/Landscape Threshold and Hysteresis register */
50  FXLS8471Q_A_FFMT_CFG = 0x15, /* A_FFMT_CFG Freefall/Motion Configuration register */
51  FXLS8471Q_A_FFMT_SRC = 0x16, /* A_FFMT_SRC Freefall/Motion Source register */
52  FXLS8471Q_A_FFMT_THS = 0x17, /* A_FFMT_THS Freefall and Motion Threshold register */
53  FXLS8471Q_A_FFMT_COUNT = 0x18, /* A_FFMT_COUNT Debounce register */
54  FXLS8471Q_TRANSIENT_CFG = 0x1D, /* Transient_CFG register */
55  FXLS8471Q_TRANSIENT_SRC = 0x1E, /* TRANSIENT_SRC register */
56  FXLS8471Q_TRANSIENT_THS = 0x1F, /* TRANSIENT_THS register */
57  FXLS8471Q_TRANSIENT_COUNT = 0x20, /* TRANSIENT_COUNT register */
58  FXLS8471Q_PULSE_CFG = 0x21, /* PULSE_CFG Pulse Configuration register */
59  FXLS8471Q_PULSE_SRC = 0x22, /* PULSE_SRC Pulse Source register */
60  FXLS8471Q_PULSE_THSX = 0x23, /* PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers */
61  FXLS8471Q_PULSE_THSY = 0x24, /* PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers */
62  FXLS8471Q_PULSE_THSZ = 0x25, /* PULSE_THSX, Y, Z Pulse Threshold for X, Y and Z registers */
63  FXLS8471Q_PULSE_TMLT = 0x26, /* PULSE_TMLT Pulse Time Window 1 register */
64  FXLS8471Q_PULSE_LTCY = 0x27, /* PULSE_LTCY Pulse Latency Timer register */
65  FXLS8471Q_PULSE_WIND = 0x28, /* PULSE_WIND register (Read/Write) */
66  FXLS8471Q_ASLP_COUNT = 0x29, /* ASLP_COUNT, Auto-WAKE/SLEEP Detection register (Read/Write) */
67  FXLS8471Q_CTRL_REG1 = 0x2A, /* CTRL_REG1 System Control 1 register */
68  FXLS8471Q_CTRL_REG2 = 0x2B, /* CTRL_REG2 System Control 1 register */
69  FXLS8471Q_CTRL_REG3 = 0x2C, /* CTRL_REG3 Interrupt Control register */
70  FXLS8471Q_CTRL_REG4 = 0x2D, /* CTRL_REG4 Interrupt Enable register (Read/Write) */
71  FXLS8471Q_CTRL_REG5 = 0x2E, /* CTRL_REG5 Interrupt Configuration register (Read/Write) */
72  FXLS8471Q_OFF_X = 0x2F, /* OFF_X Offset Correction X register */
73  FXLS8471Q_OFF_Y = 0x30, /* OFF_Y Offset Correction Y register */
74  FXLS8471Q_OFF_Z = 0x31, /* OFF_Z Offset Correction Z register */
75  FXLS8471Q_A_VECM_CFG = 0x5F, /* A_VECM_CFG Acceleration vectormagnitude configuration register */
76  FXLS8471Q_A_VECM_THS_MSB = 0x60, /* A_VECM_THS_MSB Acceleration vectormagnitude threshold MSB */
77  FXLS8471Q_A_VECM_THS_LSB = 0x61, /* A_VECM_THS_LSB Acceleration vectormagnitude threshold LSB */
78  FXLS8471Q_A_VECM_CNT = 0x62, /* A_VECM_CNT Acceleration vectormagnitude debounce count */
79  FXLS8471Q_A_VECM_INITX_MSB = 0x63, /* A_VECM_INITX_MSB Acceleration vectormagnitude X-axis reference value MSB */
80  FXLS8471Q_A_VECM_INITX_LSB = 0x64, /* A_VECM_INITX_LSB Acceleration vectormagnitude X-axis reference value LSB */
81  FXLS8471Q_A_VECM_INITY_MSB = 0x65, /* A_VECM_INITY_MSB Acceleration vectormagnitude Y-axis reference value MSB */
82  FXLS8471Q_A_VECM_INITY_LSB = 0x66, /* A_VECM_INITY_LSB Acceleration vectormagnitude y-axis reference value LSB */
83  FXLS8471Q_A_VECM_INITZ_MSB = 0x67, /* A_VECM_INITZ_MSB Acceleration vectormagnitude Y-axis reference value MSB */
84  FXLS8471Q_A_VECM_INITZ_LSB = 0x68, /* A_VECM_INITZ_LSB Acceleration vectormagnitude Z-axis reference value LSB */
85  FXLS8471Q_A_FFMT_THS_X_MSB = 0x73, /* A_FFMT_THS_X_MSB X-axis FMT threshold MSB */
86  FXLS8471Q_A_FFMT_THS_X_LSB = 0x74, /* A_FFMT_THS_X_LSB X-axis FMT threshold LSB */
87  FXLS8471Q_A_FFMT_THS_Y_MSB = 0x75, /* A_FFMT_THS_Y_MSB Y-axis FMT threshold MSB */
88  FXLS8471Q_A_FFMT_THS_Y_LSB = 0x76, /* A_FFMT_THS_Y_LSB Y-axis FMT threshold LSB */
89  FXLS8471Q_A_FFMT_THS_Z_MSB = 0x77, /* A_FFMT_THS_Z_MSB Z-axis FMT threshold MSB */
90  FXLS8471Q_A_FFMT_THS_Z_LSB = 0x78, /* A_FFMT_THS_Z_LSB Z-axis FMT threshold LSB */
91 };
92 
93 
94 /*--------------------------------
95 ** Register: STATUS
96 ** Enum: FXLS8471Q_STATUS
97 ** --
98 ** Offset : 0x00 - Real time status.
99 ** ------------------------------*/
100 typedef union {
101  struct {
102  uint8_t xdr : 1; /* - X-axis new Data Available. */
103 
104  uint8_t ydr : 1; /* - Y-axis new Data Available. */
105 
106  uint8_t zdr : 1; /* - Z-axis new Data Available. */
107 
108  uint8_t zyxdr : 1; /* - X, Y, Z-axis new Data Ready. */
109 
110  uint8_t xow : 1; /* - X-axis Data Overwrite. */
111 
112  uint8_t yow : 1; /* - Y-axis Data Overwrite. */
113 
114  uint8_t zow : 1; /* - Z-axis Data Overwrite */
115 
116  uint8_t zyxow : 1; /* - X, Y, Z-axis Data Overwrite. */
117 
118  } b;
119  uint8_t w;
120 } FXLS8471Q_STATUS_t;
121 
122 
123 /*
124 ** STATUS - Bit field mask definitions
125 */
126 #define FXLS8471Q_STATUS_XDR_MASK ((uint8_t) 0x01)
127 #define FXLS8471Q_STATUS_XDR_SHIFT ((uint8_t) 0)
128 
129 #define FXLS8471Q_STATUS_YDR_MASK ((uint8_t) 0x02)
130 #define FXLS8471Q_STATUS_YDR_SHIFT ((uint8_t) 1)
131 
132 #define FXLS8471Q_STATUS_ZDR_MASK ((uint8_t) 0x04)
133 #define FXLS8471Q_STATUS_ZDR_SHIFT ((uint8_t) 2)
134 
135 #define FXLS8471Q_STATUS_ZYXDR_MASK ((uint8_t) 0x08)
136 #define FXLS8471Q_STATUS_ZYXDR_SHIFT ((uint8_t) 3)
137 
138 #define FXLS8471Q_STATUS_XOW_MASK ((uint8_t) 0x10)
139 #define FXLS8471Q_STATUS_XOW_SHIFT ((uint8_t) 4)
140 
141 #define FXLS8471Q_STATUS_YOW_MASK ((uint8_t) 0x20)
142 #define FXLS8471Q_STATUS_YOW_SHIFT ((uint8_t) 5)
143 
144 #define FXLS8471Q_STATUS_ZOW_MASK ((uint8_t) 0x40)
145 #define FXLS8471Q_STATUS_ZOW_SHIFT ((uint8_t) 6)
146 
147 #define FXLS8471Q_STATUS_ZYXOW_MASK ((uint8_t) 0x80)
148 #define FXLS8471Q_STATUS_ZYXOW_SHIFT ((uint8_t) 7)
149 
150 
151 /*
152 ** STATUS - Bit field value definitions
153 */
154 #define FXLS8471Q_STATUS_XDR_XDATAREADY ((uint8_t) 0x01) /* A new X-axis data is ready. */
155 #define FXLS8471Q_STATUS_YDR_YDATAREADY ((uint8_t) 0x02) /* A new Y-axis data is ready. */
156 #define FXLS8471Q_STATUS_ZDR_ZDATAREADY ((uint8_t) 0x04) /* A new Z-axis data is ready. */
157 #define FXLS8471Q_STATUS_ZYXDR_ZYXDATAREADY ((uint8_t) 0x08) /* A new set of XYZ data is ready. */
158 #define FXLS8471Q_STATUS_XOW_XDATAOW ((uint8_t) 0x10) /* Previous X-axis data was overwritten by new X-axis */
159  /* data before it was read. */
160 #define FXLS8471Q_STATUS_YOW_YDATAOW ((uint8_t) 0x20) /* Previous Y-axis data was overwritten by new X-axis */
161  /* data before it was read. */
162 #define FXLS8471Q_STATUS_ZOW_ZDATAOW ((uint8_t) 0x40) /* Previous Z-axis data was overwritten by new X-axis */
163  /* data before it was read. */
164 #define FXLS8471Q_STATUS_ZYXOW_XYZDATAOW ((uint8_t) 0x80) /* Previous X, Y, or Z data was overwritten by new X, */
165  /* Y, or Z data before it was read. */
166 /*------------------------------*/
167 
168 
169 
170 /*--------------------------------
171 ** Register: F_STATUS
172 ** Enum: FXLS8471Q_F_STATUS
173 ** --
174 ** Offset : 0x00 - FIFO STATUS Register.
175 ** ------------------------------*/
176 typedef union {
177  struct {
178  uint8_t f_cnt : 6; /* - FIFO sample counter. 00_0001 to 10_0000 indicates 1 to 32 samples stored */
179  /* in FIFO. */
180 
181  uint8_t f_wmrk_flag : 1; /* - FIFO watermark flag. */
182 
183  uint8_t f_ovf : 1; /* - FIFO overflow flag. */
184 
185  } b;
186  uint8_t w;
187 } FXLS8471Q_F_STATUS_t;
188 
189 
190 /*
191 ** F_STATUS - Bit field mask definitions
192 */
193 #define FXLS8471Q_F_STATUS_F_CNT_MASK ((uint8_t) 0x3F)
194 #define FXLS8471Q_F_STATUS_F_CNT_SHIFT ((uint8_t) 0)
195 
196 #define FXLS8471Q_F_STATUS_F_WMRK_FLAG_MASK ((uint8_t) 0x40)
197 #define FXLS8471Q_F_STATUS_F_WMRK_FLAG_SHIFT ((uint8_t) 6)
198 
199 #define FXLS8471Q_F_STATUS_F_OVF_MASK ((uint8_t) 0x80)
200 #define FXLS8471Q_F_STATUS_F_OVF_SHIFT ((uint8_t) 7)
201 
202 
203 /*
204 ** F_STATUS - Bit field value definitions
205 */
206 #define FXLS8471Q_F_STATUS_F_WMRK_FLAG_NOTDETECTED ((uint8_t) 0x00) /* No FIFO watermark events detected. */
207 #define FXLS8471Q_F_STATUS_F_WMRK_FLAG_DETECTED ((uint8_t) 0x40) /* FIFO Watermark event detected. FIFO sample count */
208  /* is greater than watermark value. */
209 #define FXLS8471Q_F_STATUS_F_OVF_NOTDETECTED ((uint8_t) 0x00) /* No FIFO overflow events detected. */
210 #define FXLS8471Q_F_STATUS_F_OVF_DETECTED ((uint8_t) 0x80) /* FIFO event detected; FIFO has overflowed. */
211 /*------------------------------*/
212 
213 
214 
215 /*--------------------------------
216 ** Register: OUT_X_MSB
217 ** Enum: FXLS8471Q_OUT_X_MSB
218 ** --
219 ** Offset : 0x01 - Bits 4-11 of 12-bit X Axis current sample data.
220 ** ------------------------------*/
221 typedef uint8_t FXLS8471Q_OUT_X_MSB_t;
222 
223 
224 /*--------------------------------
225 ** Register: OUT_X_LSB
226 ** Enum: FXLS8471Q_OUT_X_LSB
227 ** --
228 ** Offset : 0x02 - Bits 0-3 of 12-bit X Axis current sample data.
229 ** ------------------------------*/
230 typedef uint8_t FXLS8471Q_OUT_X_LSB_t;
231 
232 
233 
234 /*--------------------------------
235 ** Register: OUT_Y_MSB
236 ** Enum: FXLS8471Q_OUT_Y_MSB
237 ** --
238 ** Offset : 0x03 - Bits 4-11 of 12-bit Y Axis current sample data.
239 ** ------------------------------*/
240 typedef uint8_t FXLS8471Q_OUT_Y_MSB_t;
241 
242 
243 /*--------------------------------
244 ** Register: OUT_Y_LSB
245 ** Enum: FXLS8471Q_OUT_Y_LSB
246 ** --
247 ** Offset : 0x04 - Bits 0-3 of 12-bit Y Axis current sample data.
248 ** ------------------------------*/
249 typedef uint8_t FXLS8471Q_OUT_Y_LSB_t;
250 
251 
252 
253 /*--------------------------------
254 ** Register: OUT_Z_MSB
255 ** Enum: FXLS8471Q_OUT_Z_MSB
256 ** --
257 ** Offset : 0x05 - Bits 4-11 of 12-bit Z Axis current sample data.
258 ** ------------------------------*/
259 typedef uint8_t FXLS8471Q_OUT_Z_MSB_t;
260 
261 
262 /*--------------------------------
263 ** Register: OUT_Z_LSB
264 ** Enum: FXLS8471Q_OUT_Z_LSB
265 ** --
266 ** Offset : 0x06 - Bits 0-3 of 12-bit Z Axis current sample data.
267 ** ------------------------------*/
268 typedef uint8_t FXLS8471Q_OUT_Z_LSB_t;
269 
270 
271 
272 /*--------------------------------
273 ** Register: F_SETUP
274 ** Enum: FXLS8471Q_F_SETUP
275 ** --
276 ** Offset : 0x09 - FIFO Setup Register.
277 ** ------------------------------*/
278 typedef union {
279  struct {
280  uint8_t f_wmrk : 6; /* - FIFO Event Sample Count Watermark. These bits set the number of FIFO */
281  /* samples required to trigger a watermark interrupt. */
282 
283  uint8_t f_mode : 2; /* - FIFO buffer overflow mode. */
284 
285  } b;
286  uint8_t w;
287 } FXLS8471Q_F_SETUP_t;
288 
289 
290 /*
291 ** F_SETUP - Bit field mask definitions
292 */
293 #define FXLS8471Q_F_SETUP_F_WMRK_MASK ((uint8_t) 0x3F)
294 #define FXLS8471Q_F_SETUP_F_WMRK_SHIFT ((uint8_t) 0)
295 
296 #define FXLS8471Q_F_SETUP_F_MODE_MASK ((uint8_t) 0xC0)
297 #define FXLS8471Q_F_SETUP_F_MODE_SHIFT ((uint8_t) 6)
298 
299 
300 /*
301 ** F_SETUP - Bit field value definitions
302 */
303 #define FXLS8471Q_F_SETUP_F_MODE_FIFODISABLED ((uint8_t) 0x00) /* FIFO is disabled. */
304 #define FXLS8471Q_F_SETUP_F_MODE_FIFOMOSTRECENT ((uint8_t) 0x40) /* FIFO contains the Most Recent samples when */
305  /* overflowed (circular buffer). */
306 #define FXLS8471Q_F_SETUP_F_MODE_FIFOSTOP ((uint8_t) 0x80) /* FIFO stops accepting new samples when overflowed. */
307 #define FXLS8471Q_F_SETUP_F_MODE_TRIGGERMODE ((uint8_t) 0xc0) /* The FIFO will be in a circular mode up to the */
308  /* number of samples in the watermark. The FIFO will */
309  /* be in a circular mode until the trigger event */
310  /* occurs. */
311 /*------------------------------*/
312 
313 
314 
315 /*--------------------------------
316 ** Register: TRIG_CFG
317 ** Enum: FXLS8471Q_TRIG_CFG
318 ** --
319 ** Offset : 0x0A - Trigger Configuration Register.
320 ** ------------------------------*/
321 typedef union {
322  struct {
323  uint8_t _reserved_ : 1;
324  uint8_t trig_a_vecm : 1;
325  uint8_t trig_ff_mt : 1; /* - Freefall/Motion trigger bit. */
326 
327  uint8_t trig_pulse : 1; /* - Pulse interrupt trigger bit. */
328 
329  uint8_t trig_lndprt : 1; /* - Landscape/Portrait Orientation interrupt trigger bit. */
330 
331  uint8_t trig_trans : 1; /* - Transient interrupt trigger bit. */
332 
333  } b;
334  uint8_t w;
335 } FXLS8471Q_TRIG_CFG_t;
336 
337 
338 /*
339 ** TRIG_CFG - Bit field mask definitions
340 */
341 #define FXLS8471Q_TRIG_CFG_TRIG_A_VECM_MASK ((uint8_t) 0x02)
342 #define FXLS8471Q_TRIG_CFG_TRIG_A_VECM_SHIFT ((uint8_t) 1)
343 
344 #define FXLS8471Q_TRIG_CFG_TRIG_FF_MT_MASK ((uint8_t) 0x04)
345 #define FXLS8471Q_TRIG_CFG_TRIG_FF_MT_SHIFT ((uint8_t) 2)
346 
347 #define FXLS8471Q_TRIG_CFG_TRIG_PULSE_MASK ((uint8_t) 0x08)
348 #define FXLS8471Q_TRIG_CFG_TRIG_PULSE_SHIFT ((uint8_t) 3)
349 
350 #define FXLS8471Q_TRIG_CFG_TRIG_LNDPRT_MASK ((uint8_t) 0x10)
351 #define FXLS8471Q_TRIG_CFG_TRIG_LNDPRT_SHIFT ((uint8_t) 4)
352 
353 #define FXLS8471Q_TRIG_CFG_TRIG_TRANS_MASK ((uint8_t) 0x20)
354 #define FXLS8471Q_TRIG_CFG_TRIG_TRANS_SHIFT ((uint8_t) 5)
355 
356 
357 /*
358 ** TRIG_CFG - Bit field value definitions
359 */
360 #define FXLS8471Q_TRIG_CFG_TRIG_A_VECM_EN ((uint8_t) 0x02) /* Enable the vector-magnitude FIFO trigger */
361 #define FXLS8471Q_TRIG_CFG_TRIG_A_VECM_DIS ((uint8_t) 0x00) /* Disable the vector-magnitude FIFO trigger */
362 #define FXLS8471Q_TRIG_CFG_TRIG_FF_MT_CLEARED ((uint8_t) 0x00) /* Freefall/Motion trigger bit is cleared. */
363 #define FXLS8471Q_TRIG_CFG_TRIG_FF_MT_SET ((uint8_t) 0x04) /* Pulse interrupt trigger bit bit is set. */
364 #define FXLS8471Q_TRIG_CFG_TRIG_PULSE_CLEARED ((uint8_t) 0x00) /* Pulse interrupt trigger bit is cleared. */
365 #define FXLS8471Q_TRIG_CFG_TRIG_PULSE_SET ((uint8_t) 0x08) /* Pulse interrupt trigger bit is set. */
366 #define FXLS8471Q_TRIG_CFG_TRIG_LNDPRT_CLEARED ((uint8_t) 0x00) /* Landscape/Portrait Orientation interrupt trigger */
367  /* bit is cleared. */
368 #define FXLS8471Q_TRIG_CFG_TRIG_LNDPRT_SET ((uint8_t) 0x10) /* Landscape/Portrait Orientation interrupt trigger */
369  /* bit is set. */
370 #define FXLS8471Q_TRIG_CFG_TRIG_TRANS_CLEARED ((uint8_t) 0x00) /* Transient interrupt trigger bit is cleared. */
371 #define FXLS8471Q_TRIG_CFG_TRIG_TRANS_SET ((uint8_t) 0x20) /* Transient interrupt trigger bit is set. */
372 /*------------------------------*/
373 
374 
375 
376 /*--------------------------------
377 ** Register: SYSMOD
378 ** Enum: FXLS8471Q_SYSMOD
379 ** --
380 ** Offset : 0x0B - System Mode Register indicates the current device operating mode.
381 ** ------------------------------*/
382 typedef union {
383  struct {
384  uint8_t sysmod : 2; /* - System mode data bits. */
385 
386  uint8_t fgt : 5; /* - Number of ODR time units since FGERR was asserted. Reset when FGERR */
387  /* Cleared. */
388 
389  uint8_t fgerr : 1; /* - FIFO Gate Error. */
390 
391  } b;
392  uint8_t w;
393 } FXLS8471Q_SYSMOD_t;
394 
395 
396 /*
397 ** SYSMOD - Bit field mask definitions
398 */
399 #define FXLS8471Q_SYSMOD_SYSMOD_MASK ((uint8_t) 0x03)
400 #define FXLS8471Q_SYSMOD_SYSMOD_SHIFT ((uint8_t) 0)
401 
402 #define FXLS8471Q_SYSMOD_FGT_MASK ((uint8_t) 0x7C)
403 #define FXLS8471Q_SYSMOD_FGT_SHIFT ((uint8_t) 2)
404 
405 #define FXLS8471Q_SYSMOD_FGERR_MASK ((uint8_t) 0x80)
406 #define FXLS8471Q_SYSMOD_FGERR_SHIFT ((uint8_t) 7)
407 
408 
409 /*
410 ** SYSMOD - Bit field value definitions
411 */
412 #define FXLS8471Q_SYSMOD_SYSMOD_STANDBY ((uint8_t) 0x00) /* STANDBY Mode. */
413 #define FXLS8471Q_SYSMOD_SYSMOD_WAKE ((uint8_t) 0x01) /* ACTIVE Mode. */
414 #define FXLS8471Q_SYSMOD_SYSMOD_SLEEP ((uint8_t) 0x02) /* SLEEP Mode. */
415 #define FXLS8471Q_SYSMOD_FGERR_NTDETECTED ((uint8_t) 0x00) /* No FIFO Gate Error detected. */
416 #define FXLS8471Q_SYSMOD_FGERR_DETECTED ((uint8_t) 0x80) /* FIFO Gate Error was detected. */
417 /*------------------------------*/
418 
419 
420 
421 /*--------------------------------
422 ** Register: INT_SOURCE
423 ** Enum: FXLS8471Q_INT_SOURCE
424 ** --
425 ** Offset : 0x0C - System Interrupt Status Register. The bits that are set (logic ‘1’) indicate which function has asserted its interrupt and conversely, bits that are cleared (logic ‘0’) indicate which function has not asserted its interrupt.
426 ** ------------------------------*/
427 typedef union {
428  struct {
429  uint8_t src_drdy : 1; /* Data Ready Interrupt bit status. */
430 
431  uint8_t src_a_vecm : 1; /* Accelerometer vector-magnitude interrupt status bit */
432 
433  uint8_t src_ff_mt : 1; /* Freefall/Motion interrupt status bit. */
434 
435  uint8_t src_pulse : 1; /* Pulse interrupt status bit. */
436 
437  uint8_t src_lndprt : 1; /* Landscape/Portrait Orientation interrupt status bit. */
438 
439  uint8_t src_trans : 1; /* Transient interrupt status bit. */
440 
441  uint8_t src_fifo : 1; /* FIFO interrupt status bit. */
442 
443  uint8_t src_aslp : 1; /* Auto-SLEEP/WAKE interrupt status bit. */
444 
445  } b;
446  uint8_t w;
447 } FXLS8471Q_INT_SOURCE_t;
448 
449 
450 /*
451 ** INT_SOURCE - Bit field mask definitions
452 */
453 #define FXLS8471Q_INT_SOURCE_SRC_DRDY_MASK ((uint8_t) 0x01)
454 #define FXLS8471Q_INT_SOURCE_SRC_DRDY_SHIFT ((uint8_t) 0)
455 
456 #define FXLS8471Q_INT_SOURCE_SRC_A_VECM_MASK ((uint8_t) 0x02)
457 #define FXLS8471Q_INT_SOURCE_SRC_A_VECM_SHIFT ((uint8_t) 1)
458 
459 #define FXLS8471Q_INT_SOURCE_SRC_FF_MT_MASK ((uint8_t) 0x04)
460 #define FXLS8471Q_INT_SOURCE_SRC_FF_MT_SHIFT ((uint8_t) 2)
461 
462 #define FXLS8471Q_INT_SOURCE_SRC_PULSE_MASK ((uint8_t) 0x08)
463 #define FXLS8471Q_INT_SOURCE_SRC_PULSE_SHIFT ((uint8_t) 3)
464 
465 #define FXLS8471Q_INT_SOURCE_SRC_LNDPRT_MASK ((uint8_t) 0x10)
466 #define FXLS8471Q_INT_SOURCE_SRC_LNDPRT_SHIFT ((uint8_t) 4)
467 
468 #define FXLS8471Q_INT_SOURCE_SRC_TRANS_MASK ((uint8_t) 0x20)
469 #define FXLS8471Q_INT_SOURCE_SRC_TRANS_SHIFT ((uint8_t) 5)
470 
471 #define FXLS8471Q_INT_SOURCE_SRC_FIFO_MASK ((uint8_t) 0x40)
472 #define FXLS8471Q_INT_SOURCE_SRC_FIFO_SHIFT ((uint8_t) 6)
473 
474 #define FXLS8471Q_INT_SOURCE_SRC_ASLP_MASK ((uint8_t) 0x80)
475 #define FXLS8471Q_INT_SOURCE_SRC_ASLP_SHIFT ((uint8_t) 7)
476 
477 
478 /*------------------------------*/
479 
480 
481 
482 /*--------------------------------
483 ** Register: WHO_AM_I
484 ** Enum: FXLS8471Q_WHO_AM_I
485 ** --
486 ** Offset : 0x0D - Fixed Device ID Number.
487 ** ------------------------------*/
488 typedef union {
489  struct {
490  uint8_t whoami; /* The WHO_AM_I register contains the device identifier which is factory */
491  /* programmed. */
492 
493  } b;
494  uint8_t w;
495 } FXLS8471Q_WHO_AM_I_t;
496 
497 
498 /*
499 ** WHO_AM_I - Bit field mask definitions
500 */
501 #define FXLS8471Q_WHO_AM_I_WHOAMI_MASK ((uint8_t) 0xFF)
502 #define FXLS8471Q_WHO_AM_I_WHOAMI_SHIFT ((uint8_t) 0)
503 
504 
505 /*------------------------------*/
506 
507 
508 /*
509 ** WHO_AM_I - Bit field value definitions
510 */
511 
512 #define FXLS8471Q_WHO_AM_I_WHOAMI_VALUE ((uint8_t) 0x6a) /* Device identifier for FXLS8471 */
513 
514 
515 /*--------------------------------
516 ** Register: XYZ_DATA_CFG
517 ** Enum: FXLS8471Q_XYZ_DATA_CFG
518 ** --
519 ** Offset : 0x0E - XYZ Data Configuration Register. sets the dynamic range and sets the high-pass filter for the output data.
520 ** ------------------------------*/
521 typedef union {
522  struct {
523  uint8_t fs : 2; /* Output buffer data format full scale. */
524 
525  uint8_t _reserved_ : 2;
526  uint8_t hpf_out : 1; /* Enable High-Pass output data. */
527 
528  } b;
529  uint8_t w;
530 } FXLS8471Q_XYZ_DATA_CFG_t;
531 
532 
533 /*
534 ** XYZ_DATA_CFG - Bit field mask definitions
535 */
536 #define FXLS8471Q_XYZ_DATA_CFG_FS_MASK ((uint8_t) 0x03)
537 #define FXLS8471Q_XYZ_DATA_CFG_FS_SHIFT ((uint8_t) 0)
538 
539 #define FXLS8471Q_XYZ_DATA_CFG_HPF_OUT_MASK ((uint8_t) 0x10)
540 #define FXLS8471Q_XYZ_DATA_CFG_HPF_OUT_SHIFT ((uint8_t) 4)
541 
542 
543 /*
544 ** XYZ_DATA_CFG - Bit field value definitions
545 */
546 #define FXLS8471Q_XYZ_DATA_CFG_FS_FS_RANGE_2G ((uint8_t) 0x00) /* Output buffer data full scale range is 2g. */
547 #define FXLS8471Q_XYZ_DATA_CFG_FS_FS_RANGE_4G ((uint8_t) 0x01) /* Output buffer data full scale range is 4g. */
548 #define FXLS8471Q_XYZ_DATA_CFG_FS_FS_RANGE_8G ((uint8_t) 0x02) /* Output buffer data full scale range is 8g. */
549 #define FXLS8471Q_XYZ_DATA_CFG_HPF_OUT_DISABLED ((uint8_t) 0x00) /* High-Pass output data disabled. */
550 #define FXLS8471Q_XYZ_DATA_CFG_HPF_OUT_ENABLED ((uint8_t) 0x10) /* High-Pass output data enabled. */
551 /*------------------------------*/
552 
553 
554 
555 /*--------------------------------
556 ** Register: HP_FILTER_CUTOFF
557 ** Enum: FXLS8471Q_HP_FILTER_CUTOFF
558 ** --
559 ** Offset : 0x0F - HP_FILTER_CUTOFF High-Pass Filter Register. This register sets the high-pass filter cutoff frequency for removal of the offset and slower changing acceleration data.
560 ** ------------------------------*/
561 typedef union {
562  struct {
563  uint8_t sel : 2; /* HPF Cutoff frequency selection. */
564 
565  uint8_t _reserved_ : 2;
566  uint8_t pulse_lpf_en : 1; /* Enable Low-Pass Filter for Pulse Processing Function. */
567 
568  uint8_t pulse_hpf_byp : 1; /* Bypass High-Pass Filter for Pulse Processing Function. */
569 
570  } b;
571  uint8_t w;
572 } FXLS8471Q_HP_FILTER_CUTOFF_t;
573 
574 
575 /*
576 ** HP_FILTER_CUTOFF - Bit field mask definitions
577 */
578 #define FXLS8471Q_HP_FILTER_CUTOFF_SEL_MASK ((uint8_t) 0x03)
579 #define FXLS8471Q_HP_FILTER_CUTOFF_SEL_SHIFT ((uint8_t) 0)
580 
581 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_LPF_EN_MASK ((uint8_t) 0x10)
582 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_LPF_EN_SHIFT ((uint8_t) 4)
583 
584 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_HPF_BYP_MASK ((uint8_t) 0x20)
585 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_HPF_BYP_SHIFT ((uint8_t) 5)
586 
587 
588 /*
589 ** HP_FILTER_CUTOFF - Bit field value definitions
590 */
591 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_LPF_EN_DISABLED ((uint8_t) 0x00) /* LPF disabled for Pulse Processing. */
592 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_LPF_EN_ENABLED ((uint8_t) 0x10) /* LPF Enabled for Pulse Processing. */
593 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_HPF_BYP_DISABLED ((uint8_t) 0x00) /* HPF enabled for Pulse Processing. */
594 #define FXLS8471Q_HP_FILTER_CUTOFF_PULSE_HPF_BYP_ENABLED ((uint8_t) 0x20) /* HPF Bypassed for Pulse Processing. */
595 /*------------------------------*/
596 
597 
598 
599 /*--------------------------------
600 ** Register: PL_STATUS
601 ** Enum: FXLS8471Q_PL_STATUS
602 ** --
603 ** Offset : 0x10 - Portrait/Landscape Status Register.
604 ** ------------------------------*/
605 typedef union {
606  struct {
607  uint8_t bafro : 1; /* Back or Front orientation. */
608 
609  uint8_t lapo : 2; /* Landscape/Portrait orientation. */
610 
611  uint8_t _reserved_ : 3;
612  uint8_t lo : 1; /* Z-Tilt Angle Lockout. */
613 
614  uint8_t newlp : 1; /* Landscape/Portrait status change flag. */
615 
616  } b;
617  uint8_t w;
618 } FXLS8471Q_PL_STATUS_t;
619 
620 
621 /*
622 ** PL_STATUS - Bit field mask definitions
623 */
624 #define FXLS8471Q_PL_STATUS_BAFRO_MASK ((uint8_t) 0x01)
625 #define FXLS8471Q_PL_STATUS_BAFRO_SHIFT ((uint8_t) 0)
626 
627 #define FXLS8471Q_PL_STATUS_LAPO_MASK ((uint8_t) 0x06)
628 #define FXLS8471Q_PL_STATUS_LAPO_SHIFT ((uint8_t) 1)
629 
630 #define FXLS8471Q_PL_STATUS_LO_MASK ((uint8_t) 0x40)
631 #define FXLS8471Q_PL_STATUS_LO_SHIFT ((uint8_t) 6)
632 
633 #define FXLS8471Q_PL_STATUS_NEWLP_MASK ((uint8_t) 0x80)
634 #define FXLS8471Q_PL_STATUS_NEWLP_SHIFT ((uint8_t) 7)
635 
636 
637 /*
638 ** PL_STATUS - Bit field value definitions
639 */
640 #define FXLS8471Q_PL_STATUS_BAFRO_FRONT ((uint8_t) 0x00) /* Front: Equipment is in the front facing */
641  /* orientation. */
642 #define FXLS8471Q_PL_STATUS_BAFRO_BACK ((uint8_t) 0x01) /* Back: Equipment is in the back facing */
643  /* orientation. */
644 #define FXLS8471Q_PL_STATUS_LAPO_UP ((uint8_t) 0x00) /* Portrait Up: Equipment standing vertically in the */
645  /* normal orientation. */
646 #define FXLS8471Q_PL_STATUS_LAPO_DOWN ((uint8_t) 0x02) /* Portrait Down: Equipment standing vertically in */
647  /* the inverted orientation. */
648 #define FXLS8471Q_PL_STATUS_LAPO_RIGHT ((uint8_t) 0x04) /* Landscape Right: Equipment is in landscape mode */
649  /* to the right. */
650 #define FXLS8471Q_PL_STATUS_LAPO_LEFT ((uint8_t) 0x06) /* Landscape Left: Equipment is in landscape mode to */
651  /* the left. */
652 #define FXLS8471Q_PL_STATUS_LO_NOTDETECTED ((uint8_t) 0x00) /* Lockout condition has not been detected. */
653 #define FXLS8471Q_PL_STATUS_LO_DETECTED ((uint8_t) 0x40) /* Z-Tilt lockout trip angle has been exceeded. */
654  /* Lockout has been detected. */
655 #define FXLS8471Q_PL_STATUS_NEWLP_NOCHANGE ((uint8_t) 0x00) /* No change. */
656 #define FXLS8471Q_PL_STATUS_NEWLP_DETECTED ((uint8_t) 0x80) /* BAFRO and/or LAPO and/or Z-Tilt lockout value has */
657  /* changed. */
658 /*------------------------------*/
659 
660 
661 
662 /*--------------------------------
663 ** Register: PL_CFG
664 ** Enum: FXLS8471Q_PL_CFG
665 ** --
666 ** Offset : 0x11 - Portrait/Landscape Configuration Register.
667 ** ------------------------------*/
668 typedef union {
669  struct {
670  uint8_t reserved : 6; /* - Bits 5-0 are reserved, will always read 0. */
671 
672  uint8_t pl_en : 1; /* - Portrait/Landscape Detection Enable. */
673 
674  uint8_t dbcntm : 1; /* - Debounce counter mode selection. */
675 
676  } b;
677  uint8_t w;
678 } FXLS8471Q_PL_CFG_t;
679 
680 
681 /*
682 ** PL_CFG - Bit field mask definitions
683 */
684 #define FXLS8471Q_PL_CFG_RESERVED_MASK ((uint8_t) 0x3F)
685 #define FXLS8471Q_PL_CFG_RESERVED_SHIFT ((uint8_t) 0)
686 
687 #define FXLS8471Q_PL_CFG_PL_EN_MASK ((uint8_t) 0x40)
688 #define FXLS8471Q_PL_CFG_PL_EN_SHIFT ((uint8_t) 6)
689 
690 #define FXLS8471Q_PL_CFG_DBCNTM_MASK ((uint8_t) 0x80)
691 #define FXLS8471Q_PL_CFG_DBCNTM_SHIFT ((uint8_t) 7)
692 
693 
694 /*
695 ** PL_CFG - Bit field value definitions
696 */
697 #define FXLS8471Q_PL_CFG_PL_EN_DISABLED ((uint8_t) 0x00) /* Portrait/Landscape Detection is Disabled. */
698 #define FXLS8471Q_PL_CFG_PL_EN_ENABLED ((uint8_t) 0x40) /* Portrait/Landscape Detection is Enabled. */
699 #define FXLS8471Q_PL_CFG_DBCNTM_DEC ((uint8_t) 0x00) /* Decrements debounce whenever condition of interest */
700  /* is no longer valid. */
701 #define FXLS8471Q_PL_CFG_DBCNTM_CLR ((uint8_t) 0x80) /* Clears counter whenever condition of interest is no */
702  /* longer valid. */
703 /*------------------------------*/
704 
705 
706 
707 /*--------------------------------
708 ** Register: PL_COUNT
709 ** Enum: FXLS8471Q_PL_COUNT
710 ** --
711 ** Offset : 0x12 - Portrait/Landscape Debounce Counter.
712 ** ------------------------------*/
713 typedef union {
714  struct {
715  uint8_t dbcne; /* - Debounce Count value. */
716 
717  } b;
718  uint8_t w;
719 } FXLS8471Q_PL_COUNT_t;
720 
721 
722 /*
723 ** PL_COUNT - Bit field mask definitions
724 */
725 #define FXLS8471Q_PL_COUNT_DBCNE_MASK ((uint8_t) 0xFF)
726 #define FXLS8471Q_PL_COUNT_DBCNE_SHIFT ((uint8_t) 0)
727 
728 
729 /*------------------------------*/
730 
731 
732 
733 /*--------------------------------
734 ** Register: PL_BF_ZCOMP
735 ** Enum: FXLS8471Q_PL_BF_ZCOMP
736 ** --
737 ** Offset : 0x13 - Back/Front and Z Compensation Register.
738 ** ------------------------------*/
739 typedef union {
740  struct {
741  uint8_t zlock : 3; /* - Z-Lock Angle Fixed Threshold. */
742 
743  uint8_t _reserved_ : 3;
744  uint8_t bkfr : 2; /* - Back Front Trip Angle Fixed Threshold. */
745 
746  } b;
747  uint8_t w;
748 } FXLS8471Q_PL_BF_ZCOMP_t;
749 
750 
751 /*
752 ** PL_BF_ZCOMP - Bit field mask definitions
753 */
754 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MASK ((uint8_t) 0x07)
755 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_SHIFT ((uint8_t) 0)
756 
757 #define FXLS8471Q_PL_BF_ZCOMP_BKFR_MASK ((uint8_t) 0xC0)
758 #define FXLS8471Q_PL_BF_ZCOMP_BKFR_SHIFT ((uint8_t) 6)
759 
760 
761 /*
762 ** PL_BF_ZCOMP - Bit field value definitions
763 */
764 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN13_6_MAX14_5 ((uint8_t) 0x00)
765 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN17_1_MAX18_2 ((uint8_t) 0x01)
766 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN20_7_MAX22_0 ((uint8_t) 0x02)
767 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN24_4_MAX25_9 ((uint8_t) 0x03)
768 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN28_1_MAX30_0 ((uint8_t) 0x04)
769 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN32_0_MAX34_2 ((uint8_t) 0x05)
770 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN36_1_MAX38_7 ((uint8_t) 0x06)
771 #define FXLS8471Q_PL_BF_ZCOMP_ZLOCK_MIN40_4_MAX43_4 ((uint8_t) 0x07)
772 #define FXLS8471Q_PL_BF_ZCOMP_BKFR_80_280 ((uint8_t) 0x00)
773 #define FXLS8471Q_PL_BF_ZCOMP_BKFR_75_285 ((uint8_t) 0x40)
774 #define FXLS8471Q_PL_BF_ZCOMP_BKFR_70_290 ((uint8_t) 0x80)
775 #define FXLS8471Q_PL_BF_ZCOMP_BKFR_65_295 ((uint8_t) 0xc0)
776 /*------------------------------*/
777 
778 
779 
780 /*--------------------------------
781 ** Register: PL_THS_REG
782 ** Enum: FXLS8471Q_PL_THS_REG
783 ** --
784 ** Offset : 0x14 - Portrait/Landscape Threshold and Hysteresis Register.
785 ** ------------------------------*/
786 typedef union {
787  struct {
788  uint8_t hys : 3; /* - Hysteresis, This is a fixed angle added to the threshold angle for a */
789  /* smoother transition from Portrait to Landscape and Landscape to Portrait. */
790 
791  uint8_t pl_ths : 5; /* - Portrait/Landscape Fixed Threshold angle. */
792 
793  } b;
794  uint8_t w;
795 } FXLS8471Q_PL_THS_REG_t;
796 
797 
798 /*
799 ** PL_THS_REG - Bit field mask definitions
800 */
801 #define FXLS8471Q_PL_THS_REG_HYS_MASK ((uint8_t) 0x07)
802 #define FXLS8471Q_PL_THS_REG_HYS_SHIFT ((uint8_t) 0)
803 
804 #define FXLS8471Q_PL_THS_REG_PL_THS_MASK ((uint8_t) 0xF8)
805 #define FXLS8471Q_PL_THS_REG_PL_THS_SHIFT ((uint8_t) 3)
806 
807 
808 /*
809 ** PL_THS_REG - Bit field value definitions
810 */
811 #define FXLS8471Q_PL_THS_REG_HYS_45_45 ((uint8_t) 0x00)
812 #define FXLS8471Q_PL_THS_REG_HYS_49_41 ((uint8_t) 0x01)
813 #define FXLS8471Q_PL_THS_REG_HYS_52_38 ((uint8_t) 0x02)
814 #define FXLS8471Q_PL_THS_REG_HYS_56_34 ((uint8_t) 0x03)
815 #define FXLS8471Q_PL_THS_REG_HYS_59_31 ((uint8_t) 0x04)
816 #define FXLS8471Q_PL_THS_REG_HYS_62_28 ((uint8_t) 0x05)
817 #define FXLS8471Q_PL_THS_REG_HYS_66_24 ((uint8_t) 0x06)
818 #define FXLS8471Q_PL_THS_REG_HYS_69_21 ((uint8_t) 0x07)
819 #define FXLS8471Q_PL_THS_REG_PL_THS_15 ((uint8_t) 0x38)
820 #define FXLS8471Q_PL_THS_REG_PL_THS_20 ((uint8_t) 0x48)
821 #define FXLS8471Q_PL_THS_REG_PL_THS_30 ((uint8_t) 0x60)
822 #define FXLS8471Q_PL_THS_REG_PL_THS_35 ((uint8_t) 0x68)
823 #define FXLS8471Q_PL_THS_REG_PL_THS_40 ((uint8_t) 0x78)
824 #define FXLS8471Q_PL_THS_REG_PL_THS_45 ((uint8_t) 0x80)
825 #define FXLS8471Q_PL_THS_REG_PL_THS_55 ((uint8_t) 0x98)
826 #define FXLS8471Q_PL_THS_REG_PL_THS_60 ((uint8_t) 0xa0)
827 #define FXLS8471Q_PL_THS_REG_PL_THS_70 ((uint8_t) 0xb8)
828 #define FXLS8471Q_PL_THS_REG_PL_THS_75 ((uint8_t) 0xc8)
829 /*------------------------------*/
830 
831 
832 
833 
834 /*--------------------------------
835 ** Register: A_FFMT_CFG
836 ** Enum: FXLS8471Q_A_FFMT_CFG
837 ** --
838 ** Offset : 0x15 - Freefall/Motion Configuration Register.
839 ** ------------------------------*/
840 typedef union {
841  struct {
842  uint8_t reserved : 3; /* - Bits 2-0 are reserved, will always read 0. */
843 
844  uint8_t xefe : 1; /* - Event flag enable on X event. */
845 
846  uint8_t yefe : 1; /* - Event flag enable on Y event. */
847 
848  uint8_t zefe : 1; /* - Event flag enable on Z event. */
849 
850  uint8_t oae : 1; /* - Motion detect / Freefall detect flag selection. */
851 
852  uint8_t ele : 1; /* - Event Latch Enable. */
853 
854  } b;
855  uint8_t w;
856 } FXLS8471Q_A_FFMT_CFG_t;
857 
858 
859 /*
860 ** A_FFMT_CFG - Bit field mask definitions
861 */
862 #define FXLS8471Q_A_FFMT_CFG_RESERVED_MASK ((uint8_t) 0x07)
863 #define FXLS8471Q_A_FFMT_CFG_RESERVED_SHIFT ((uint8_t) 0)
864 
865 #define FXLS8471Q_A_FFMT_CFG_XEFE_MASK ((uint8_t) 0x08)
866 #define FXLS8471Q_A_FFMT_CFG_XEFE_SHIFT ((uint8_t) 3)
867 
868 #define FXLS8471Q_A_FFMT_CFG_YEFE_MASK ((uint8_t) 0x10)
869 #define FXLS8471Q_A_FFMT_CFG_YEFE_SHIFT ((uint8_t) 4)
870 
871 #define FXLS8471Q_A_FFMT_CFG_ZEFE_MASK ((uint8_t) 0x20)
872 #define FXLS8471Q_A_FFMT_CFG_ZEFE_SHIFT ((uint8_t) 5)
873 
874 #define FXLS8471Q_A_FFMT_CFG_OAE_MASK ((uint8_t) 0x40)
875 #define FXLS8471Q_A_FFMT_CFG_OAE_SHIFT ((uint8_t) 6)
876 
877 #define FXLS8471Q_A_FFMT_CFG_ELE_MASK ((uint8_t) 0x80)
878 #define FXLS8471Q_A_FFMT_CFG_ELE_SHIFT ((uint8_t) 7)
879 
880 
881 /*
882 ** A_FFMT_CFG - Bit field value definitions
883 */
884 #define FXLS8471Q_A_FFMT_CFG_XEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
885 #define FXLS8471Q_A_FFMT_CFG_XEFE_ENABLED ((uint8_t) 0x08) /* Raise event flag on measured acceleration value */
886  /* beyond preset threshold. */
887 #define FXLS8471Q_A_FFMT_CFG_YEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
888 #define FXLS8471Q_A_FFMT_CFG_YEFE_ENABLED ((uint8_t) 0x10) /* Raise event flag on measured acceleration value */
889  /* beyond preset threshold. */
890 #define FXLS8471Q_A_FFMT_CFG_ZEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
891 #define FXLS8471Q_A_FFMT_CFG_ZEFE_ENABLED ((uint8_t) 0x20) /* Raise event flag on measured acceleration value */
892  /* beyond preset threshold. */
893 #define FXLS8471Q_A_FFMT_CFG_OAE_FREEFALL ((uint8_t) 0x00) /* Freefall Flag. */
894 #define FXLS8471Q_A_FFMT_CFG_OAE_MOTION ((uint8_t) 0x00) /* Motion Flag. */
895 #define FXLS8471Q_A_FFMT_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */
896 #define FXLS8471Q_A_FFMT_CFG_ELE_ENABLED ((uint8_t) 0x80) /* Event flag latch enabled. */
897 /*------------------------------*/
898 
899 
900 
901 /*--------------------------------
902 ** Register: A_FFMT_SRC
903 ** Enum: FXLS8471Q_A_FFMT_SRC
904 ** --
905 ** Offset : 0x16 - Freefall/Motion Source Register.
906 ** ------------------------------*/
907 typedef union {
908  struct {
909  uint8_t xhp : 1; /* - Event flag enable on X event. */
910 
911  uint8_t xhe : 1; /* - Event flag enable on Y event. */
912 
913  uint8_t yhp : 1; /* - Event flag enable on Z event. */
914 
915  uint8_t yhe : 1; /* - Motion detect / Freefall detect flag selection. */
916 
917  uint8_t zhp : 1; /* - Event Latch Enable. */
918 
919  uint8_t zhe : 1; /* - Event Latch Enable. */
920 
921  uint8_t _reserved_ : 1;
922  uint8_t ea : 1; /* - Event Latch Enable. */
923 
924  } b;
925  uint8_t w;
926 } FXLS8471Q_A_FFMT_SRC_t;
927 
928 
929 /*
930 ** A_FFMT_SRC - Bit field mask definitions
931 */
932 #define FXLS8471Q_A_FFMT_SRC_XHP_MASK ((uint8_t) 0x01)
933 #define FXLS8471Q_A_FFMT_SRC_XHP_SHIFT ((uint8_t) 0)
934 
935 #define FXLS8471Q_A_FFMT_SRC_XHE_MASK ((uint8_t) 0x02)
936 #define FXLS8471Q_A_FFMT_SRC_XHE_SHIFT ((uint8_t) 1)
937 
938 #define FXLS8471Q_A_FFMT_SRC_YHP_MASK ((uint8_t) 0x04)
939 #define FXLS8471Q_A_FFMT_SRC_YHP_SHIFT ((uint8_t) 2)
940 
941 #define FXLS8471Q_A_FFMT_SRC_YHE_MASK ((uint8_t) 0x08)
942 #define FXLS8471Q_A_FFMT_SRC_YHE_SHIFT ((uint8_t) 3)
943 
944 #define FXLS8471Q_A_FFMT_SRC_ZHP_MASK ((uint8_t) 0x10)
945 #define FXLS8471Q_A_FFMT_SRC_ZHP_SHIFT ((uint8_t) 4)
946 
947 #define FXLS8471Q_A_FFMT_SRC_ZHE_MASK ((uint8_t) 0x20)
948 #define FXLS8471Q_A_FFMT_SRC_ZHE_SHIFT ((uint8_t) 5)
949 
950 #define FXLS8471Q_A_FFMT_SRC_EA_MASK ((uint8_t) 0x80)
951 #define FXLS8471Q_A_FFMT_SRC_EA_SHIFT ((uint8_t) 7)
952 
953 
954 /*
955 ** A_FFMT_SRC - Bit field value definitions
956 */
957 #define FXLS8471Q_A_FFMT_SRC_XHP_POSITIVE ((uint8_t) 0x00) /* X event was Positive. */
958 #define FXLS8471Q_A_FFMT_SRC_XHP_NEGATIVE ((uint8_t) 0x01) /* X event was Negative. */
959 #define FXLS8471Q_A_FFMT_SRC_XHE_NOTDETECTED ((uint8_t) 0x00) /* No X Motion event detected. */
960 #define FXLS8471Q_A_FFMT_SRC_XHE_DETECTED ((uint8_t) 0x02) /* X Motion has been detected. */
961 #define FXLS8471Q_A_FFMT_SRC_YHP_POSITIVE ((uint8_t) 0x00) /* Y event was Positive. */
962 #define FXLS8471Q_A_FFMT_SRC_YHP_NEGATIVE ((uint8_t) 0x04) /* Y event was Negative. */
963 #define FXLS8471Q_A_FFMT_SRC_YHE_NOTDETECTED ((uint8_t) 0x00) /* No Y Motion event detected. */
964 #define FXLS8471Q_A_FFMT_SRC_YHE_DETECTED ((uint8_t) 0x08) /* Y Motion has been detected. */
965 #define FXLS8471Q_A_FFMT_SRC_ZHP_POSITIVE ((uint8_t) 0x00) /* Z event was Positive. */
966 #define FXLS8471Q_A_FFMT_SRC_ZHP_NEGATIVE ((uint8_t) 0x10) /* Z event was Negative. */
967 #define FXLS8471Q_A_FFMT_SRC_ZHE_NOTDETECTED ((uint8_t) 0x00) /* No Z Motion event detected. */
968 #define FXLS8471Q_A_FFMT_SRC_ZHE_DETECTED ((uint8_t) 0x20) /* Z Motion has been detected. */
969 #define FXLS8471Q_A_FFMT_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No event flag has been asserted. */
970 #define FXLS8471Q_A_FFMT_SRC_EA_DETECTED ((uint8_t) 0x80) /* one or more event flag has been asserted. */
971 /*------------------------------*/
972 
973 
974 
975 /*--------------------------------
976 ** Register: A_FFMT_THS
977 ** Enum: FXLS8471Q_A_FFMT_THS
978 ** --
979 ** Offset : 0x17 - Freefall and Motion Threshold Register.
980 ** ------------------------------*/
981 typedef union {
982  struct {
983  uint8_t ths : 7; /* - Freefall /Motion Threshold. */
984 
985  uint8_t dbcntm : 1; /* - Debounce counter mode selection. */
986 
987  } b;
988  uint8_t w;
989 } FXLS8471Q_A_FFMT_THS_t;
990 
991 
992 /*
993 ** A_FFMT_THS - Bit field mask definitions
994 */
995 #define FXLS8471Q_A_FFMT_THS_THS_MASK ((uint8_t) 0x7F)
996 #define FXLS8471Q_A_FFMT_THS_THS_SHIFT ((uint8_t) 0)
997 
998 #define FXLS8471Q_A_FFMT_THS_DBCNTM_MASK ((uint8_t) 0x80)
999 #define FXLS8471Q_A_FFMT_THS_DBCNTM_SHIFT ((uint8_t) 7)
1000 
1001 
1002 /*
1003 ** A_FFMT_THS - Bit field value definitions
1004 */
1005 #define FXLS8471Q_A_FFMT_THS_DBCNTM_DEC ((uint8_t) 0x00) /* Increments or decrements debounce. */
1006 #define FXLS8471Q_A_FFMT_THS_DBCNTM_CLR ((uint8_t) 0x80) /* Increments or clears counter. */
1007 /*------------------------------*/
1008 
1009 
1010 
1011 /*--------------------------------
1012 ** Register: A_FFMT_COUNT
1013 ** Enum: FXLS8471Q_A_FFMT_COUNT
1014 ** --
1015 ** Offset : 0x18 - Debounce Register.
1016 ** ------------------------------*/
1017 typedef union {
1018  struct {
1019  uint8_t d; /* - Count value. */
1020 
1021  } b;
1022  uint8_t w;
1023 } FXLS8471Q_A_FFMT_COUNT_t;
1024 
1025 
1026 /*
1027 ** A_FFMT_COUNT - Bit field mask definitions
1028 */
1029 #define FXLS8471Q_A_FFMT_COUNT_D_MASK ((uint8_t) 0xFF)
1030 #define FXLS8471Q_A_FFMT_COUNT_D_SHIFT ((uint8_t) 0)
1031 
1032 
1033 /*------------------------------*/
1034 
1035 
1036 
1037 /*--------------------------------
1038 ** Register: TRANSIENT_CFG
1039 ** Enum: FXLS8471Q_TRANSIENT_CFG
1040 ** --
1041 ** Offset : 0x1D - Transient_CFG Register.
1042 ** ------------------------------*/
1043 typedef union {
1044  struct {
1045  uint8_t hpf_byp : 1; /* - Bypass High-Pass filter. */
1046 
1047  uint8_t xtefe : 1; /* - Event flag enable on X transient acceleration greater than transient */
1048  /* threshold event. */
1049 
1050  uint8_t ytefe : 1; /* - Event flag enable on Y transient acceleration greater than transient */
1051  /* threshold event. */
1052 
1053  uint8_t ztefe : 1; /* - Event flag enable on Z transient acceleration greater than transient */
1054  /* threshold event. */
1055 
1056  uint8_t ele : 1; /* - Transient event flags are latched into the TRANSIENT_SRC register. */
1057 
1058  uint8_t reserved : 3; /* - Bits 7-5 are reserved, will always read 0. */
1059 
1060  } b;
1061  uint8_t w;
1062 } FXLS8471Q_TRANSIENT_CFG_t;
1063 
1064 
1065 /*
1066 ** TRANSIENT_CFG - Bit field mask definitions
1067 */
1068 #define FXLS8471Q_TRANSIENT_CFG_HPF_BYP_MASK ((uint8_t) 0x01)
1069 #define FXLS8471Q_TRANSIENT_CFG_HPF_BYP_SHIFT ((uint8_t) 0)
1070 
1071 #define FXLS8471Q_TRANSIENT_CFG_XTEFE_MASK ((uint8_t) 0x02)
1072 #define FXLS8471Q_TRANSIENT_CFG_XTEFE_SHIFT ((uint8_t) 1)
1073 
1074 #define FXLS8471Q_TRANSIENT_CFG_YTEFE_MASK ((uint8_t) 0x04)
1075 #define FXLS8471Q_TRANSIENT_CFG_YTEFE_SHIFT ((uint8_t) 2)
1076 
1077 #define FXLS8471Q_TRANSIENT_CFG_ZTEFE_MASK ((uint8_t) 0x08)
1078 #define FXLS8471Q_TRANSIENT_CFG_ZTEFE_SHIFT ((uint8_t) 3)
1079 
1080 #define FXLS8471Q_TRANSIENT_CFG_ELE_MASK ((uint8_t) 0x10)
1081 #define FXLS8471Q_TRANSIENT_CFG_ELE_SHIFT ((uint8_t) 4)
1082 
1083 #define FXLS8471Q_TRANSIENT_CFG_RESERVED_MASK ((uint8_t) 0xE0)
1084 #define FXLS8471Q_TRANSIENT_CFG_RESERVED_SHIFT ((uint8_t) 5)
1085 
1086 
1087 /*
1088 ** TRANSIENT_CFG - Bit field value definitions
1089 */
1090 #define FXLS8471Q_TRANSIENT_CFG_HPF_BYP_THROUGH ((uint8_t) 0x00) /* Data to transient acceleration detection */
1091  /* block is through HPF. */
1092 #define FXLS8471Q_TRANSIENT_CFG_HPF_BYP_BYPASS ((uint8_t) 0x01) /* Data to transient acceleration detection */
1093  /* block is NOT through HPF. */
1094 #define FXLS8471Q_TRANSIENT_CFG_XTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1095 #define FXLS8471Q_TRANSIENT_CFG_XTEFE_ENABLED ((uint8_t) 0x02) /* Raise event flag on measured acceleration */
1096  /* delta value greater than transient threshold. */
1097 #define FXLS8471Q_TRANSIENT_CFG_YTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1098 #define FXLS8471Q_TRANSIENT_CFG_YTEFE_ENABLED ((uint8_t) 0x04) /* Raise event flag on measured acceleration */
1099  /* delta value greater than transient threshold. */
1100 #define FXLS8471Q_TRANSIENT_CFG_ZTEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1101 #define FXLS8471Q_TRANSIENT_CFG_ZTEFE_ENABLED ((uint8_t) 0x08) /* Raise event flag on measured acceleration */
1102  /* delta value greater than transient threshold. */
1103 #define FXLS8471Q_TRANSIENT_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */
1104 #define FXLS8471Q_TRANSIENT_CFG_ELE_ENABLED ((uint8_t) 0x10) /* Event flag latch enabled. */
1105 /*------------------------------*/
1106 
1107 
1108 
1109 /*--------------------------------
1110 ** Register: TRANSIENT_SRC
1111 ** Enum: FXLS8471Q_TRANSIENT_SRC
1112 ** --
1113 ** Offset : 0x1E - Transient_SRC Register.
1114 ** ------------------------------*/
1115 typedef union {
1116  struct {
1117  uint8_t x_trans_pol : 1; /* - Polarity of X Transient Event that triggered interrupt. */
1118 
1119  uint8_t xtrans : 1; /* - X transient event. */
1120 
1121  uint8_t y_trans_pol : 1; /* - Polarity of Y Transient Event that triggered interrupt. */
1122 
1123  uint8_t ytrans : 1; /* - Y transient event. */
1124 
1125  uint8_t z_trans_pol : 1; /* - Polarity of Z Transient Event that triggered interrupt. */
1126 
1127  uint8_t ztrans : 1; /* - Z transient event. */
1128 
1129  uint8_t ea : 1; /* - Event Active Flag. */
1130 
1131  } b;
1132  uint8_t w;
1133 } FXLS8471Q_TRANSIENT_SRC_t;
1134 
1135 
1136 /*
1137 ** TRANSIENT_SRC - Bit field mask definitions
1138 */
1139 #define FXLS8471Q_TRANSIENT_SRC_X_TRANS_POL_MASK ((uint8_t) 0x01)
1140 #define FXLS8471Q_TRANSIENT_SRC_X_TRANS_POL_SHIFT ((uint8_t) 0)
1141 
1142 #define FXLS8471Q_TRANSIENT_SRC_XTRANS_MASK ((uint8_t) 0x02)
1143 #define FXLS8471Q_TRANSIENT_SRC_XTRANS_SHIFT ((uint8_t) 1)
1144 
1145 #define FXLS8471Q_TRANSIENT_SRC_Y_TRANS_POL_MASK ((uint8_t) 0x04)
1146 #define FXLS8471Q_TRANSIENT_SRC_Y_TRANS_POL_SHIFT ((uint8_t) 2)
1147 
1148 #define FXLS8471Q_TRANSIENT_SRC_YTRANS_MASK ((uint8_t) 0x08)
1149 #define FXLS8471Q_TRANSIENT_SRC_YTRANS_SHIFT ((uint8_t) 3)
1150 
1151 #define FXLS8471Q_TRANSIENT_SRC_Z_TRANS_POL_MASK ((uint8_t) 0x10)
1152 #define FXLS8471Q_TRANSIENT_SRC_Z_TRANS_POL_SHIFT ((uint8_t) 4)
1153 
1154 #define FXLS8471Q_TRANSIENT_SRC_ZTRANS_MASK ((uint8_t) 0x20)
1155 #define FXLS8471Q_TRANSIENT_SRC_ZTRANS_SHIFT ((uint8_t) 5)
1156 
1157 #define FXLS8471Q_TRANSIENT_SRC_EA_MASK ((uint8_t) 0x40)
1158 #define FXLS8471Q_TRANSIENT_SRC_EA_SHIFT ((uint8_t) 6)
1159 
1160 
1161 /*
1162 ** TRANSIENT_SRC - Bit field value definitions
1163 */
1164 #define FXLS8471Q_TRANSIENT_SRC_X_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* X event was Positive. */
1165 #define FXLS8471Q_TRANSIENT_SRC_X_TRANS_POL_NEGATIVE ((uint8_t) 0x01) /* X event was Negative. */
1166 #define FXLS8471Q_TRANSIENT_SRC_XTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */
1167 #define FXLS8471Q_TRANSIENT_SRC_XTRANS_DETECTED ((uint8_t) 0x02) /* X Transient acceleration greater than the */
1168  /* value of TRANSIENT_THS event has occurred. */
1169 #define FXLS8471Q_TRANSIENT_SRC_Y_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* Y event was Positive. */
1170 #define FXLS8471Q_TRANSIENT_SRC_Y_TRANS_POL_NEGATIVE ((uint8_t) 0x04) /* Y event was Negative. */
1171 #define FXLS8471Q_TRANSIENT_SRC_YTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */
1172 #define FXLS8471Q_TRANSIENT_SRC_YTRANS_DETECTED ((uint8_t) 0x08) /* Y Transient acceleration greater than the */
1173  /* value of TRANSIENT_THS event has occurred. */
1174 #define FXLS8471Q_TRANSIENT_SRC_Z_TRANS_POL_POSITIVE ((uint8_t) 0x00) /* Z event was Positive. */
1175 #define FXLS8471Q_TRANSIENT_SRC_Z_TRANS_POL_NEGATIVE ((uint8_t) 0x10) /* Z event was Negative. */
1176 #define FXLS8471Q_TRANSIENT_SRC_ZTRANS_NOTDETECTED ((uint8_t) 0x00) /* no interrupt. */
1177 #define FXLS8471Q_TRANSIENT_SRC_ZTRANS_DETECTED ((uint8_t) 0x20) /* Z Transient acceleration greater than the */
1178  /* value of TRANSIENT_THS event has occurred. */
1179 #define FXLS8471Q_TRANSIENT_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No event flag has been asserted. */
1180 #define FXLS8471Q_TRANSIENT_SRC_EA_DETECTED ((uint8_t) 0x40) /* one or more event flag has been asserted. */
1181 /*------------------------------*/
1182 
1183 
1184 
1185 /*--------------------------------
1186 ** Register: TRANSIENT_THS
1187 ** Enum: FXLS8471Q_TRANSIENT_THS
1188 ** --
1189 ** Offset : 0x1F - TRANSIENT_THS Register.
1190 ** ------------------------------*/
1191 typedef union {
1192  struct {
1193  uint8_t ths : 7; /* - Transient Threshold. */
1194 
1195  uint8_t dbcntm : 1; /* - Debounce counter mode selection. */
1196 
1197  } b;
1198  uint8_t w;
1199 } FXLS8471Q_TRANSIENT_THS_t;
1200 
1201 
1202 /*
1203 ** TRANSIENT_THS - Bit field mask definitions
1204 */
1205 #define FXLS8471Q_TRANSIENT_THS_THS_MASK ((uint8_t) 0x7F)
1206 #define FXLS8471Q_TRANSIENT_THS_THS_SHIFT ((uint8_t) 0)
1207 
1208 #define FXLS8471Q_TRANSIENT_THS_DBCNTM_MASK ((uint8_t) 0x80)
1209 #define FXLS8471Q_TRANSIENT_THS_DBCNTM_SHIFT ((uint8_t) 7)
1210 
1211 
1212 /*
1213 ** TRANSIENT_THS - Bit field value definitions
1214 */
1215 #define FXLS8471Q_TRANSIENT_THS_DBCNTM_DEC ((uint8_t) 0x00) /* Increments or decrements debounce. */
1216 #define FXLS8471Q_TRANSIENT_THS_DBCNTM_CLR ((uint8_t) 0x80) /* Increments or clears counter. */
1217 /*------------------------------*/
1218 
1219 
1220 
1221 /*--------------------------------
1222 ** Register: TRANSIENT_COUNT
1223 ** Enum: FXLS8471Q_TRANSIENT_COUNT
1224 ** --
1225 ** Offset : 0x20 - TRANSIENT_COUNT Register.
1226 ** ------------------------------*/
1227 typedef union {
1228  struct {
1229  uint8_t d; /* - Count value. */
1230 
1231  } b;
1232  uint8_t w;
1233 } FXLS8471Q_TRANSIENT_COUNT_t;
1234 
1235 
1236 /*
1237 ** TRANSIENT_COUNT - Bit field mask definitions
1238 */
1239 #define FXLS8471Q_TRANSIENT_COUNT_D_MASK ((uint8_t) 0xFF)
1240 #define FXLS8471Q_TRANSIENT_COUNT_D_SHIFT ((uint8_t) 0)
1241 
1242 
1243 /*------------------------------*/
1244 
1245 
1246 
1247 /*--------------------------------
1248 ** Register: PULSE_CFG
1249 ** Enum: FXLS8471Q_PULSE_CFG
1250 ** --
1251 ** Offset : 0x21 - Pulse Configuration Register.
1252 ** ------------------------------*/
1253 typedef union {
1254  struct {
1255  uint8_t xspefe : 1; /* - Event flag enable on single pulse event on X-axis. */
1256 
1257  uint8_t xdpefe : 1; /* - Event flag enable on double pulse event on X-axis. */
1258 
1259  uint8_t yspefe : 1; /* - Event flag enable on single pulse event on Y-axis. */
1260 
1261  uint8_t ydpefe : 1; /* - Event flag enable on double pulse event on Y-axis. */
1262 
1263  uint8_t zspefe : 1; /* - Event flag enable on single pulse event on Z-axis. */
1264 
1265  uint8_t zdpefe : 1; /* - Event flag enable on double pulse event on Z-axis. */
1266 
1267  uint8_t ele : 1; /* - Pulse event flags are latched into the PULSE_SRC register. */
1268 
1269  uint8_t dpa : 1; /* - Double Pulse Abort. */
1270 
1271  } b;
1272  uint8_t w;
1273 } FXLS8471Q_PULSE_CFG_t;
1274 
1275 
1276 /*
1277 ** PULSE_CFG - Bit field mask definitions
1278 */
1279 #define FXLS8471Q_PULSE_CFG_XSPEFE_MASK ((uint8_t) 0x01)
1280 #define FXLS8471Q_PULSE_CFG_XSPEFE_SHIFT ((uint8_t) 0)
1281 
1282 #define FXLS8471Q_PULSE_CFG_XDPEFE_MASK ((uint8_t) 0x02)
1283 #define FXLS8471Q_PULSE_CFG_XDPEFE_SHIFT ((uint8_t) 1)
1284 
1285 #define FXLS8471Q_PULSE_CFG_YSPEFE_MASK ((uint8_t) 0x04)
1286 #define FXLS8471Q_PULSE_CFG_YSPEFE_SHIFT ((uint8_t) 2)
1287 
1288 #define FXLS8471Q_PULSE_CFG_YDPEFE_MASK ((uint8_t) 0x08)
1289 #define FXLS8471Q_PULSE_CFG_YDPEFE_SHIFT ((uint8_t) 3)
1290 
1291 #define FXLS8471Q_PULSE_CFG_ZSPEFE_MASK ((uint8_t) 0x10)
1292 #define FXLS8471Q_PULSE_CFG_ZSPEFE_SHIFT ((uint8_t) 4)
1293 
1294 #define FXLS8471Q_PULSE_CFG_ZDPEFE_MASK ((uint8_t) 0x20)
1295 #define FXLS8471Q_PULSE_CFG_ZDPEFE_SHIFT ((uint8_t) 5)
1296 
1297 #define FXLS8471Q_PULSE_CFG_ELE_MASK ((uint8_t) 0x40)
1298 #define FXLS8471Q_PULSE_CFG_ELE_SHIFT ((uint8_t) 6)
1299 
1300 #define FXLS8471Q_PULSE_CFG_DPA_MASK ((uint8_t) 0x80)
1301 #define FXLS8471Q_PULSE_CFG_DPA_SHIFT ((uint8_t) 7)
1302 
1303 
1304 /*
1305 ** PULSE_CFG - Bit field value definitions
1306 */
1307 #define FXLS8471Q_PULSE_CFG_XSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1308 #define FXLS8471Q_PULSE_CFG_XSPEFE_ENABLED ((uint8_t) 0x01) /* Event detection enabled. */
1309 #define FXLS8471Q_PULSE_CFG_XDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1310 #define FXLS8471Q_PULSE_CFG_XDPEFE_ENABLED ((uint8_t) 0x02) /* Event detection enabled. */
1311 #define FXLS8471Q_PULSE_CFG_YSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1312 #define FXLS8471Q_PULSE_CFG_YSPEFE_ENABLED ((uint8_t) 0x04) /* Event detection enabled. */
1313 #define FXLS8471Q_PULSE_CFG_YDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1314 #define FXLS8471Q_PULSE_CFG_YDPEFE_ENABLED ((uint8_t) 0x08) /* Event detection enabled. */
1315 #define FXLS8471Q_PULSE_CFG_ZSPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1316 #define FXLS8471Q_PULSE_CFG_ZSPEFE_ENABLED ((uint8_t) 0x10) /* Event detection enabled. */
1317 #define FXLS8471Q_PULSE_CFG_ZDPEFE_DISABLED ((uint8_t) 0x00) /* Event detection disabled. */
1318 #define FXLS8471Q_PULSE_CFG_ZDPEFE_ENABLED ((uint8_t) 0x20) /* Event detection enabled. */
1319 #define FXLS8471Q_PULSE_CFG_ELE_DISABLED ((uint8_t) 0x00) /* Event flag latch disabled. */
1320 #define FXLS8471Q_PULSE_CFG_ELE_ENABLED ((uint8_t) 0x40) /* Event flag latch enabled. */
1321 #define FXLS8471Q_PULSE_CFG_DPA_DISABLED ((uint8_t) 0x00) /* Double Pulse detection is not aborted if the */
1322  /* start of a pulse is detected. */
1323 #define FXLS8471Q_PULSE_CFG_DPA_ENABLED ((uint8_t) 0x80) /* Double tap detection is aborted if the start of a */
1324  /* pulse is detected. */
1325 /*------------------------------*/
1326 
1327 
1328 
1329 /*--------------------------------
1330 ** Register: PULSE_SRC
1331 ** Enum: FXLS8471Q_PULSE_SRC
1332 ** --
1333 ** Offset : 0x22 - Pulse Source Register.
1334 ** ------------------------------*/
1335 typedef union {
1336  struct {
1337  uint8_t polx : 1; /* - Pulse polarity of X-axis Event. */
1338 
1339  uint8_t poly : 1; /* - Pulse polarity of Y-axis Event. */
1340 
1341  uint8_t polz : 1; /* - Pulse polarity of Z-axis Event. */
1342 
1343  uint8_t dpe : 1; /* - Double pulse on first event. */
1344 
1345  uint8_t axx : 1; /* - X-axis event. */
1346 
1347  uint8_t axy : 1; /* - Y-axis event. */
1348 
1349  uint8_t axz : 1; /* - Z-axis event. */
1350 
1351  uint8_t ea : 1; /* - Event Active Flag. */
1352 
1353  } b;
1354  uint8_t w;
1355 } FXLS8471Q_PULSE_SRC_t;
1356 
1357 
1358 /*
1359 ** PULSE_SRC - Bit field mask definitions
1360 */
1361 #define FXLS8471Q_PULSE_SRC_POLX_MASK ((uint8_t) 0x01)
1362 #define FXLS8471Q_PULSE_SRC_POLX_SHIFT ((uint8_t) 0)
1363 
1364 #define FXLS8471Q_PULSE_SRC_POLY_MASK ((uint8_t) 0x02)
1365 #define FXLS8471Q_PULSE_SRC_POLY_SHIFT ((uint8_t) 1)
1366 
1367 #define FXLS8471Q_PULSE_SRC_POLZ_MASK ((uint8_t) 0x04)
1368 #define FXLS8471Q_PULSE_SRC_POLZ_SHIFT ((uint8_t) 2)
1369 
1370 #define FXLS8471Q_PULSE_SRC_DPE_MASK ((uint8_t) 0x08)
1371 #define FXLS8471Q_PULSE_SRC_DPE_SHIFT ((uint8_t) 3)
1372 
1373 #define FXLS8471Q_PULSE_SRC_AXX_MASK ((uint8_t) 0x10)
1374 #define FXLS8471Q_PULSE_SRC_AXX_SHIFT ((uint8_t) 4)
1375 
1376 #define FXLS8471Q_PULSE_SRC_AXY_MASK ((uint8_t) 0x20)
1377 #define FXLS8471Q_PULSE_SRC_AXY_SHIFT ((uint8_t) 5)
1378 
1379 #define FXLS8471Q_PULSE_SRC_AXZ_MASK ((uint8_t) 0x40)
1380 #define FXLS8471Q_PULSE_SRC_AXZ_SHIFT ((uint8_t) 6)
1381 
1382 #define FXLS8471Q_PULSE_SRC_EA_MASK ((uint8_t) 0x80)
1383 #define FXLS8471Q_PULSE_SRC_EA_SHIFT ((uint8_t) 7)
1384 
1385 
1386 /*
1387 ** PULSE_SRC - Bit field value definitions
1388 */
1389 #define FXLS8471Q_PULSE_SRC_POLX_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was */
1390  /* Positive. */
1391 #define FXLS8471Q_PULSE_SRC_POLX_NEGATIVE ((uint8_t) 0x01) /* Pulse Event that triggered interrupt was */
1392  /* negative. */
1393 #define FXLS8471Q_PULSE_SRC_POLY_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was */
1394  /* Positive. */
1395 #define FXLS8471Q_PULSE_SRC_POLY_NEGATIVE ((uint8_t) 0x02) /* Pulse Event that triggered interrupt was */
1396  /* negative. */
1397 #define FXLS8471Q_PULSE_SRC_POLZ_POSITIVE ((uint8_t) 0x00) /* Pulse Event that triggered interrupt was */
1398  /* Positive. */
1399 #define FXLS8471Q_PULSE_SRC_POLZ_NEGATIVE ((uint8_t) 0x04) /* Pulse Event that triggered interrupt was */
1400  /* negative. */
1401 #define FXLS8471Q_PULSE_SRC_DPE_SINGLEPULSE ((uint8_t) 0x00) /* Single Pulse Event triggered interrupt. */
1402 #define FXLS8471Q_PULSE_SRC_DPE_DOUBLEPULSE ((uint8_t) 0x08) /* Double Pulse event triggered interrupt. */
1403 #define FXLS8471Q_PULSE_SRC_AXX_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */
1404 #define FXLS8471Q_PULSE_SRC_AXX_DETECTED ((uint8_t) 0x10) /* X-axis event has occurred. */
1405 #define FXLS8471Q_PULSE_SRC_AXY_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */
1406 #define FXLS8471Q_PULSE_SRC_AXY_DETECTED ((uint8_t) 0x20) /* Y-axis event has occurred. */
1407 #define FXLS8471Q_PULSE_SRC_AXZ_NOTDETECTED ((uint8_t) 0x00) /* No interrupt. */
1408 #define FXLS8471Q_PULSE_SRC_AXZ_DETECTED ((uint8_t) 0x40) /* Z-axis event has occurred. */
1409 #define FXLS8471Q_PULSE_SRC_EA_NOTDETECTED ((uint8_t) 0x00) /* No interrupt has been generated. */
1410 #define FXLS8471Q_PULSE_SRC_EA_DETECTED ((uint8_t) 0x80) /* One or more event flag has been asserted. */
1411 /*------------------------------*/
1412 
1413 
1414 
1415 /*--------------------------------
1416 ** Register: PULSE_THSX
1417 ** Enum: FXLS8471Q_PULSE_THSX
1418 ** --
1419 ** Offset : 0x23 - Pulse Threshold for X.
1420 ** ------------------------------*/
1421 typedef union {
1422  struct {
1423  uint8_t thsx : 7; /* - Pulse Threshold on X-axis. */
1424 
1425  uint8_t reserved : 1; /* - Bit 8 is reserved, will always read 0. */
1426 
1427  } b;
1428  uint8_t w;
1429 } FXLS8471Q_PULSE_THSX_t;
1430 
1431 
1432 /*
1433 ** PULSE_THSX - Bit field mask definitions
1434 */
1435 #define FXLS8471Q_PULSE_THSX_THSX_MASK ((uint8_t) 0x7F)
1436 #define FXLS8471Q_PULSE_THSX_THSX_SHIFT ((uint8_t) 0)
1437 
1438 #define FXLS8471Q_PULSE_THSX_RESERVED_MASK ((uint8_t) 0x80)
1439 #define FXLS8471Q_PULSE_THSX_RESERVED_SHIFT ((uint8_t) 7)
1440 
1441 
1442 /*------------------------------*/
1443 
1444 
1445 
1446 /*--------------------------------
1447 ** Register: PULSE_THSY
1448 ** Enum: FXLS8471Q_PULSE_THSY
1449 ** --
1450 ** Offset : 0x24 - Pulse Threshold for Y.
1451 ** ------------------------------*/
1452 typedef union {
1453  struct {
1454  uint8_t thsy : 7; /* - Pulse Threshold on Y-axis. */
1455 
1456  uint8_t reserved : 1; /* - Bit 8 is reserved, will always read 0. */
1457 
1458  } b;
1459  uint8_t w;
1460 } FXLS8471Q_PULSE_THSY_t;
1461 
1462 
1463 /*
1464 ** PULSE_THSY - Bit field mask definitions
1465 */
1466 #define FXLS8471Q_PULSE_THSY_THSY_MASK ((uint8_t) 0x7F)
1467 #define FXLS8471Q_PULSE_THSY_THSY_SHIFT ((uint8_t) 0)
1468 
1469 #define FXLS8471Q_PULSE_THSY_RESERVED_MASK ((uint8_t) 0x80)
1470 #define FXLS8471Q_PULSE_THSY_RESERVED_SHIFT ((uint8_t) 7)
1471 
1472 
1473 /*------------------------------*/
1474 
1475 
1476 
1477 /*--------------------------------
1478 ** Register: PULSE_THSZ
1479 ** Enum: FXLS8471Q_PULSE_THSZ
1480 ** --
1481 ** Offset : 0x25 - Pulse Threshold for Z.
1482 ** ------------------------------*/
1483 typedef union {
1484  struct {
1485  uint8_t thsz : 7; /* - Pulse Threshold on Z-axis. */
1486 
1487  uint8_t reserved : 1; /* - Bit 8 is reserved, will always read 0. */
1488 
1489  } b;
1490  uint8_t w;
1491 } FXLS8471Q_PULSE_THSZ_t;
1492 
1493 
1494 /*
1495 ** PULSE_THSZ - Bit field mask definitions
1496 */
1497 #define FXLS8471Q_PULSE_THSZ_THSZ_MASK ((uint8_t) 0x7F)
1498 #define FXLS8471Q_PULSE_THSZ_THSZ_SHIFT ((uint8_t) 0)
1499 
1500 #define FXLS8471Q_PULSE_THSZ_RESERVED_MASK ((uint8_t) 0x80)
1501 #define FXLS8471Q_PULSE_THSZ_RESERVED_SHIFT ((uint8_t) 7)
1502 
1503 
1504 /*------------------------------*/
1505 
1506 
1507 
1508 /*--------------------------------
1509 ** Register: PULSE_TMLT
1510 ** Enum: FXLS8471Q_PULSE_TMLT
1511 ** --
1512 ** Offset : 0x26 - Pulse Time Window 1 Register.
1513 ** ------------------------------*/
1514 typedef union {
1515  struct {
1516  uint8_t tmlt; /* - Pulse Time Limit. */
1517 
1518  } b;
1519  uint8_t w;
1520 } FXLS8471Q_PULSE_TMLT_t;
1521 
1522 
1523 /*
1524 ** PULSE_TMLT - Bit field mask definitions
1525 */
1526 #define FXLS8471Q_PULSE_TMLT_TMLT_MASK ((uint8_t) 0xFF)
1527 #define FXLS8471Q_PULSE_TMLT_TMLT_SHIFT ((uint8_t) 0)
1528 
1529 
1530 /*------------------------------*/
1531 
1532 
1533 
1534 /*--------------------------------
1535 ** Register: PULSE_LTCY
1536 ** Enum: FXLS8471Q_PULSE_LTCY
1537 ** --
1538 ** Offset : 0x27 - Pulse Latency Timer Register.
1539 ** ------------------------------*/
1540 typedef union {
1541  struct {
1542  uint8_t ltcy; /* - Latency Time Limit. */
1543 
1544  } b;
1545  uint8_t w;
1546 } FXLS8471Q_PULSE_LTCY_t;
1547 
1548 
1549 /*
1550 ** PULSE_LTCY - Bit field mask definitions
1551 */
1552 #define FXLS8471Q_PULSE_LTCY_LTCY_MASK ((uint8_t) 0xFF)
1553 #define FXLS8471Q_PULSE_LTCY_LTCY_SHIFT ((uint8_t) 0)
1554 
1555 
1556 /*------------------------------*/
1557 
1558 
1559 
1560 /*--------------------------------
1561 ** Register: PULSE_WIND
1562 ** Enum: FXLS8471Q_PULSE_WIND
1563 ** --
1564 ** Offset : 0x28 - Second Pulse Time Window Register.
1565 ** ------------------------------*/
1566 typedef union {
1567  struct {
1568  uint8_t wind; /* - Second Pulse Time Window. */
1569 
1570  } b;
1571  uint8_t w;
1572 } FXLS8471Q_PULSE_WIND_t;
1573 
1574 
1575 /*
1576 ** PULSE_WIND - Bit field mask definitions
1577 */
1578 #define FXLS8471Q_PULSE_WIND_WIND_MASK ((uint8_t) 0xFF)
1579 #define FXLS8471Q_PULSE_WIND_WIND_SHIFT ((uint8_t) 0)
1580 
1581 
1582 /*------------------------------*/
1583 
1584 
1585 
1586 /*--------------------------------
1587 ** Register: ASLP_COUNT
1588 ** Enum: FXLS8471Q_ASLP_COUNT
1589 ** --
1590 ** Offset : 0x29 - Auto-WAKE/SLEEP count Register.
1591 ** ------------------------------*/
1592 typedef union {
1593  struct {
1594  uint8_t d; /* - Duration value. */
1595 
1596  } b;
1597  uint8_t w;
1598 } FXLS8471Q_ASLP_COUNT_t;
1599 
1600 
1601 /*
1602 ** ASLP_COUNT - Bit field mask definitions
1603 */
1604 #define FXLS8471Q_ASLP_COUNT_D_MASK ((uint8_t) 0xFF)
1605 #define FXLS8471Q_ASLP_COUNT_D_SHIFT ((uint8_t) 0)
1606 
1607 
1608 /*------------------------------*/
1609 
1610 
1611 
1612 /*--------------------------------
1613 ** Register: CTRL_REG1
1614 ** Enum: FXLS8471Q_CTRL_REG1
1615 ** --
1616 ** Offset : 0x2A - System Control 1 Register.
1617 ** ------------------------------*/
1618 typedef union {
1619  struct {
1620  uint8_t mode : 1; /* - Full Scale selection. */
1621 
1622  uint8_t f_read : 1; /* - Fast Read mode. */
1623 
1624  uint8_t lnoise : 1; /* - Reduced noise reduced Maximum range mode. */
1625 
1626  uint8_t dr : 3; /* - Data rate selection. */
1627 
1628  uint8_t aslp_rate : 2; /* - Configures the Auto-WAKE sample frequency when the device is in SLEEP */
1629  /* Mode. */
1630 
1631  } b;
1632  uint8_t w;
1633 } FXLS8471Q_CTRL_REG1_t;
1634 
1635 
1636 /*
1637 ** CTRL_REG1 - Bit field mask definitions
1638 */
1639 #define FXLS8471Q_CTRL_REG1_MODE_MASK ((uint8_t) 0x01)
1640 #define FXLS8471Q_CTRL_REG1_MODE_SHIFT ((uint8_t) 0)
1641 
1642 #define FXLS8471Q_CTRL_REG1_F_READ_MASK ((uint8_t) 0x02)
1643 #define FXLS8471Q_CTRL_REG1_F_READ_SHIFT ((uint8_t) 1)
1644 
1645 #define FXLS8471Q_CTRL_REG1_LNOISE_MASK ((uint8_t) 0x04)
1646 #define FXLS8471Q_CTRL_REG1_LNOISE_SHIFT ((uint8_t) 2)
1647 
1648 #define FXLS8471Q_CTRL_REG1_DR_MASK ((uint8_t) 0x38)
1649 #define FXLS8471Q_CTRL_REG1_DR_SHIFT ((uint8_t) 3)
1650 
1651 #define FXLS8471Q_CTRL_REG1_ASLP_RATE_MASK ((uint8_t) 0xC0)
1652 #define FXLS8471Q_CTRL_REG1_ASLP_RATE_SHIFT ((uint8_t) 6)
1653 
1654 
1655 /*
1656 ** CTRL_REG1 - Bit field value definitions
1657 */
1658 #define FXLS8471Q_CTRL_REG1_MODE_STANDBY ((uint8_t) 0x00) /* STANDBY mode. */
1659 #define FXLS8471Q_CTRL_REG1_MODE_ACTIVE ((uint8_t) 0x01) /* ACTIVE mode. */
1660 #define FXLS8471Q_CTRL_REG1_F_READ_NORMAL ((uint8_t) 0x00) /* Normal mode. */
1661 #define FXLS8471Q_CTRL_REG1_F_READ_FASTREAD ((uint8_t) 0x02) /* Fast Read Mode. */
1662 #define FXLS8471Q_CTRL_REG1_LNOISE_NORMAL ((uint8_t) 0x00) /* Normal mode. */
1663 #define FXLS8471Q_CTRL_REG1_LNOISE_REDUCED ((uint8_t) 0x04) /* Reduced Noise mode. */
1664 #define FXLS8471Q_CTRL_REG1_DR_800HZ ((uint8_t) 0x00) /* 800HZ ODR. */
1665 #define FXLS8471Q_CTRL_REG1_DR_400HZ ((uint8_t) 0x08) /* 400HZ ODR. */
1666 #define FXLS8471Q_CTRL_REG1_DR_200HZ ((uint8_t) 0x10) /* 200HZ ODR. */
1667 #define FXLS8471Q_CTRL_REG1_DR_100HZ ((uint8_t) 0x18) /* 100HZ ODR. */
1668 #define FXLS8471Q_CTRL_REG1_DR_50HZ ((uint8_t) 0x20) /* 50HZ ODR. */
1669 #define FXLS8471Q_CTRL_REG1_DR_12DOT5HZ ((uint8_t) 0x28) /* 12.5HZ ODR. */
1670 #define FXLS8471Q_CTRL_REG1_DR_6DOT25HZ ((uint8_t) 0x30) /* 6.25HZ ODR. */
1671 #define FXLS8471Q_CTRL_REG1_DR_1DOT56HZ ((uint8_t) 0x38) /* 1.56HZ ODR. */
1672 #define FXLS8471Q_CTRL_REG1_ASLP_RATE_50HZ ((uint8_t) 0x00) /* 800HZ. */
1673 #define FXLS8471Q_CTRL_REG1_ASLP_RATE_12DOT5HZ ((uint8_t) 0x40) /* 12.5HZ. */
1674 #define FXLS8471Q_CTRL_REG1_ASLP_RATE_6DOT25HZ ((uint8_t) 0x80) /* 6.25HZ. */
1675 #define FXLS8471Q_CTRL_REG1_ASLP_RATE_1DOT56HZ ((uint8_t) 0xc0) /* 1.56HZ. */
1676 /*------------------------------*/
1677 
1678 
1679 
1680 /*--------------------------------
1681 ** Register: CTRL_REG2
1682 ** Enum: FXLS8471Q_CTRL_REG2
1683 ** --
1684 ** Offset : 0x2B - System Control 2 Register.
1685 ** ------------------------------*/
1686 typedef union {
1687  struct {
1688  uint8_t mods : 2; /* - ACTIVE mode power scheme selection. */
1689 
1690  uint8_t slpe : 1; /* - Auto-SLEEP enable. */
1691 
1692  uint8_t smods : 2; /* - SLEEP mode power scheme selection. */
1693 
1694  uint8_t _reserved_ : 1;
1695  uint8_t rst : 1; /* - Software Reset. */
1696 
1697  uint8_t st : 1; /* - Self-Test Enable. */
1698 
1699  } b;
1700  uint8_t w;
1701 } FXLS8471Q_CTRL_REG2_t;
1702 
1703 
1704 /*
1705 ** CTRL_REG2 - Bit field mask definitions
1706 */
1707 #define FXLS8471Q_CTRL_REG2_MODS_MASK ((uint8_t) 0x03)
1708 #define FXLS8471Q_CTRL_REG2_MODS_SHIFT ((uint8_t) 0)
1709 
1710 #define FXLS8471Q_CTRL_REG2_SLPE_MASK ((uint8_t) 0x04)
1711 #define FXLS8471Q_CTRL_REG2_SLPE_SHIFT ((uint8_t) 2)
1712 
1713 #define FXLS8471Q_CTRL_REG2_SMODS_MASK ((uint8_t) 0x18)
1714 #define FXLS8471Q_CTRL_REG2_SMODS_SHIFT ((uint8_t) 3)
1715 
1716 #define FXLS8471Q_CTRL_REG2_RST_MASK ((uint8_t) 0x40)
1717 #define FXLS8471Q_CTRL_REG2_RST_SHIFT ((uint8_t) 6)
1718 
1719 #define FXLS8471Q_CTRL_REG2_ST_MASK ((uint8_t) 0x80)
1720 #define FXLS8471Q_CTRL_REG2_ST_SHIFT ((uint8_t) 7)
1721 
1722 
1723 /*
1724 ** CTRL_REG2 - Bit field value definitions
1725 */
1726 #define FXLS8471Q_CTRL_REG2_MODS_NORMAL ((uint8_t) 0x00) /* Normal power mode. */
1727 #define FXLS8471Q_CTRL_REG2_MODS_LOWNOISE ((uint8_t) 0x01) /* Low Noise Low Power mode. */
1728 #define FXLS8471Q_CTRL_REG2_MODS_HIGHRES ((uint8_t) 0x02) /* High Resolution mode. */
1729 #define FXLS8471Q_CTRL_REG2_MODS_LOWPOW ((uint8_t) 0x03) /* Low Power mode. */
1730 #define FXLS8471Q_CTRL_REG2_SLPE_DISABLED ((uint8_t) 0x00) /* Auto-SLEEP is not enabled. */
1731 #define FXLS8471Q_CTRL_REG2_SLPE_ENABLED ((uint8_t) 0x04) /* Auto-SLEEP is enabled. */
1732 #define FXLS8471Q_CTRL_REG2_SMODS_NORMAL ((uint8_t) 0x00) /* Normal power mode. */
1733 #define FXLS8471Q_CTRL_REG2_SMODS_LOWNOISE ((uint8_t) 0x08) /* Low Noise Low Power mode. */
1734 #define FXLS8471Q_CTRL_REG2_SMODS_HIGHRES ((uint8_t) 0x10) /* High Resolution mode. */
1735 #define FXLS8471Q_CTRL_REG2_SMODS_LOWPOW ((uint8_t) 0x18) /* Low Power mode. */
1736 #define FXLS8471Q_CTRL_REG2_RST_DISABLED ((uint8_t) 0x00) /* Device reset disabled. */
1737 #define FXLS8471Q_CTRL_REG2_RST_ENABLED ((uint8_t) 0x40) /* Device reset enabled. */
1738 #define FXLS8471Q_CTRL_REG2_ST_DISABLED ((uint8_t) 0x00) /* Self-Test disabled;. */
1739 #define FXLS8471Q_CTRL_REG2_ST_ENABLED ((uint8_t) 0x80) /* Self-Test enabled. */
1740 /*------------------------------*/
1741 
1742 
1743 
1744 /*--------------------------------
1745 ** Register: CTRL_REG3
1746 ** Enum: FXLS8471Q_CTRL_REG3
1747 ** --
1748 ** Offset : 0x2C - Interrupt Control Register.
1749 ** ------------------------------*/
1750 typedef union {
1751  struct {
1752  uint8_t pp_od : 1; /* - Push-Pull/Open Drain selection on interrupt pad. */
1753 
1754  uint8_t ipol : 1; /* - Interrupt polarity ACTIVE high, or ACTIVE low. */
1755 
1756  uint8_t wake_en_a_vecm : 1; /* vector magnitude wake mode en/dis */
1757 
1758  uint8_t wake_ff_mt : 1; /* - Freefall/Motion wake up interrupt. */
1759 
1760  uint8_t wake_pulse : 1; /* - Pulse wake up interrupt. */
1761 
1762  uint8_t wake_lndprt : 1; /* - Orientation wake up interrupt. */
1763 
1764  uint8_t wake_trans : 1; /* - Transient wake up interrupt. */
1765 
1766  uint8_t fifo_gate : 1; /* - FIFO Gate wake up interrupt. */
1767 
1768  } b;
1769  uint8_t w;
1770 } FXLS8471Q_CTRL_REG3_t;
1771 
1772 
1773 /*
1774 ** CTRL_REG3 - Bit field mask definitions
1775 */
1776 #define FXLS8471Q_CTRL_REG3_PP_OD_MASK ((uint8_t) 0x01)
1777 #define FXLS8471Q_CTRL_REG3_PP_OD_SHIFT ((uint8_t) 0)
1778 
1779 #define FXLS8471Q_CTRL_REG3_IPOL_MASK ((uint8_t) 0x02)
1780 #define FXLS8471Q_CTRL_REG3_IPOL_SHIFT ((uint8_t) 1)
1781 
1782 #define FXLS8471Q_CTRL_REG3_WAKE_EN_A_VECM_MASK ((uint8_t) 0x04)
1783 #define FXLS8471Q_CTRL_REG3_WAKE_EN_A_VECM_SHIFT ((uint8_t) 2)
1784 
1785 #define FXLS8471Q_CTRL_REG3_WAKE_FF_MT_MASK ((uint8_t) 0x08)
1786 #define FXLS8471Q_CTRL_REG3_WAKE_FF_MT_SHIFT ((uint8_t) 3)
1787 
1788 #define FXLS8471Q_CTRL_REG3_WAKE_PULSE_MASK ((uint8_t) 0x10)
1789 #define FXLS8471Q_CTRL_REG3_WAKE_PULSE_SHIFT ((uint8_t) 4)
1790 
1791 #define FXLS8471Q_CTRL_REG3_WAKE_LNDPRT_MASK ((uint8_t) 0x20)
1792 #define FXLS8471Q_CTRL_REG3_WAKE_LNDPRT_SHIFT ((uint8_t) 5)
1793 
1794 #define FXLS8471Q_CTRL_REG3_WAKE_TRANS_MASK ((uint8_t) 0x40)
1795 #define FXLS8471Q_CTRL_REG3_WAKE_TRANS_SHIFT ((uint8_t) 6)
1796 
1797 #define FXLS8471Q_CTRL_REG3_FIFO_GATE_MASK ((uint8_t) 0x80)
1798 #define FXLS8471Q_CTRL_REG3_FIFO_GATE_SHIFT ((uint8_t) 7)
1799 
1800 
1801 /*
1802 ** CTRL_REG3 - Bit field value definitions
1803 */
1804 #define FXLS8471Q_CTRL_REG3_PP_OD_PUSHPULL ((uint8_t) 0x00) /* Push-Pull. */
1805 #define FXLS8471Q_CTRL_REG3_PP_OD_OPENDRAIN ((uint8_t) 0x01) /* Open Drain. */
1806 #define FXLS8471Q_CTRL_REG3_IPOL_LOW ((uint8_t) 0x00) /* ACTIVE low. */
1807 #define FXLS8471Q_CTRL_REG3_IPOL_HIGH ((uint8_t) 0x02) /* ACTIVE high. */
1808 #define FXLS8471Q_CTRL_REG3_WAKE_EN_A_VECM_EN ((uint8_t) 0x04) /* Acceleration vector-magnitude function is enabled */
1809  /* in Sleep mode and can generate an interrupt to */
1810  /* wake the system */
1811 #define FXLS8471Q_CTRL_REG3_WAKE_EN_A_VECM_DIS ((uint8_t) 0x00) /* Acceleration vector-magnitude function is */
1812  /* disabled in Sleep mode */
1813 #define FXLS8471Q_CTRL_REG3_WAKE_FF_MT_BYPASS ((uint8_t) 0x00) /* Freefall/Motion function is bypassed in SLEEP */
1814  /* mode. */
1815 #define FXLS8471Q_CTRL_REG3_WAKE_FF_MT_WAKEUP ((uint8_t) 0x08) /* Freefall/Motion function interrupt can wake up. */
1816 #define FXLS8471Q_CTRL_REG3_WAKE_PULSE_BYPASS ((uint8_t) 0x00) /* Pulse function is bypassed in SLEEP mode. */
1817 #define FXLS8471Q_CTRL_REG3_WAKE_PULSE_WAKEUP ((uint8_t) 0x10) /* Pulse function interrupt can wake up. */
1818 #define FXLS8471Q_CTRL_REG3_WAKE_LNDPRT_BYPASS ((uint8_t) 0x00) /* Orientation function is bypassed in SLEEP mode. */
1819 #define FXLS8471Q_CTRL_REG3_WAKE_LNDPRT_WAKEUP ((uint8_t) 0x20) /* Orientation function interrupt can wake up. */
1820 #define FXLS8471Q_CTRL_REG3_WAKE_TRANS_BYPASS ((uint8_t) 0x00) /* Transient function is bypassed in SLEEP mode. */
1821 #define FXLS8471Q_CTRL_REG3_WAKE_TRANS_WAKEUP ((uint8_t) 0x40) /* Transient function interrupt can wake up. */
1822 #define FXLS8471Q_CTRL_REG3_FIFO_GATE_BYPASS ((uint8_t) 0x00) /* FIFO gate is bypassed. FIFO is flushed upon the */
1823  /* system mode transitioning from WAKE to SLEEP mode */
1824  /* or from SLEEP to WAKE mode. */
1825 #define FXLS8471Q_CTRL_REG3_FIFO_GATE_WAKEUP ((uint8_t) 0x80) /* The FIFO input buffer is blocked when */
1826  /* transitioning from WAKE to SLEEP mode or from */
1827  /* SLEEP to WAKE mode until the FIFO is flushed. */
1828 /*------------------------------*/
1829 
1830 
1831 
1832 /*--------------------------------
1833 ** Register: CTRL_REG4
1834 ** Enum: FXLS8471Q_CTRL_REG4
1835 ** --
1836 ** Offset : 0x2D - Interrupt Enable register (Read/Write).
1837 ** ------------------------------*/
1838 typedef union {
1839  struct {
1840  uint8_t int_en_drdy : 1; /* - Interrupt Enable. */
1841 
1842  uint8_t int_en_a_vecm : 1; /* Vector magnitude interrupt */
1843 
1844  uint8_t int_en_ff_mt : 1; /* - Interrupt Enable. */
1845 
1846  uint8_t int_en_pulse : 1; /* - Interrupt Enable. */
1847 
1848  uint8_t int_en_lndprt : 1; /* - Interrupt Enable. */
1849 
1850  uint8_t int_en_trans : 1; /* - Interrupt Enable. */
1851 
1852  uint8_t int_en_fifo : 1; /* - Interrupt Enable. */
1853 
1854  uint8_t int_en_aslp : 1; /* - Interrupt Enable. */
1855 
1856  } b;
1857  uint8_t w;
1858 } FXLS8471Q_CTRL_REG4_t;
1859 
1860 
1861 /*
1862 ** CTRL_REG4 - Bit field mask definitions
1863 */
1864 #define FXLS8471Q_CTRL_REG4_INT_EN_DRDY_MASK ((uint8_t) 0x01)
1865 #define FXLS8471Q_CTRL_REG4_INT_EN_DRDY_SHIFT ((uint8_t) 0)
1866 
1867 #define FXLS8471Q_CTRL_REG4_INT_EN_A_VECM_MASK ((uint8_t) 0x02)
1868 #define FXLS8471Q_CTRL_REG4_INT_EN_A_VECM_SHIFT ((uint8_t) 1)
1869 
1870 #define FXLS8471Q_CTRL_REG4_INT_EN_FF_MT_MASK ((uint8_t) 0x04)
1871 #define FXLS8471Q_CTRL_REG4_INT_EN_FF_MT_SHIFT ((uint8_t) 2)
1872 
1873 #define FXLS8471Q_CTRL_REG4_INT_EN_PULSE_MASK ((uint8_t) 0x08)
1874 #define FXLS8471Q_CTRL_REG4_INT_EN_PULSE_SHIFT ((uint8_t) 3)
1875 
1876 #define FXLS8471Q_CTRL_REG4_INT_EN_LNDPRT_MASK ((uint8_t) 0x10)
1877 #define FXLS8471Q_CTRL_REG4_INT_EN_LNDPRT_SHIFT ((uint8_t) 4)
1878 
1879 #define FXLS8471Q_CTRL_REG4_INT_EN_TRANS_MASK ((uint8_t) 0x20)
1880 #define FXLS8471Q_CTRL_REG4_INT_EN_TRANS_SHIFT ((uint8_t) 5)
1881 
1882 #define FXLS8471Q_CTRL_REG4_INT_EN_FIFO_MASK ((uint8_t) 0x40)
1883 #define FXLS8471Q_CTRL_REG4_INT_EN_FIFO_SHIFT ((uint8_t) 6)
1884 
1885 #define FXLS8471Q_CTRL_REG4_INT_EN_ASLP_MASK ((uint8_t) 0x80)
1886 #define FXLS8471Q_CTRL_REG4_INT_EN_ASLP_SHIFT ((uint8_t) 7)
1887 
1888 
1889 /*
1890 ** CTRL_REG4 - Bit field value definitions
1891 */
1892 #define FXLS8471Q_CTRL_REG4_INT_EN_DRDY_DISABLED ((uint8_t) 0x00) /* Data Ready interrupt disabled. */
1893 #define FXLS8471Q_CTRL_REG4_INT_EN_DRDY_ENABLED ((uint8_t) 0x01) /* Data Ready interrupt enabled. */
1894 #define FXLS8471Q_CTRL_REG4_INT_EN_A_VECM_DISABLED ((uint8_t) 0x00) /* Vector magnitude interrupt disabled. */
1895 #define FXLS8471Q_CTRL_REG4_INT_EN_A_VECM_ENABLED ((uint8_t) 0x02) /* Vector magnitude interrupt enabled. */
1896 #define FXLS8471Q_CTRL_REG4_INT_EN_FF_MT_DISABLED ((uint8_t) 0x00) /* Freefall/Motion interrupt disabled. */
1897 #define FXLS8471Q_CTRL_REG4_INT_EN_FF_MT_ENABLED ((uint8_t) 0x04) /* Freefall/Motion interrupt enabled. */
1898 #define FXLS8471Q_CTRL_REG4_INT_EN_PULSE_DISABLED ((uint8_t) 0x00) /* Pulse Detection interrupt disabled. */
1899 #define FXLS8471Q_CTRL_REG4_INT_EN_PULSE_ENABLED ((uint8_t) 0x08) /* Pulse Detection interrupt enabled. */
1900 #define FXLS8471Q_CTRL_REG4_INT_EN_LNDPRT_DISABLED ((uint8_t) 0x00) /* Orientation (Landscape/Portrait) interrupt */
1901  /* disabled. */
1902 #define FXLS8471Q_CTRL_REG4_INT_EN_LNDPRT_ENABLED ((uint8_t) 0x10) /* Orientation (Landscape/Portrait) interrupt */
1903  /* enabled. */
1904 #define FXLS8471Q_CTRL_REG4_INT_EN_TRANS_DISABLED ((uint8_t) 0x00) /* Transient interrupt disabled. */
1905 #define FXLS8471Q_CTRL_REG4_INT_EN_TRANS_ENABLED ((uint8_t) 0x20) /* Transient interrupt enabled. */
1906 #define FXLS8471Q_CTRL_REG4_INT_EN_FIFO_DISABLED ((uint8_t) 0x00) /* FIFO interrupt disabled. */
1907 #define FXLS8471Q_CTRL_REG4_INT_EN_FIFO_ENABLED ((uint8_t) 0x40) /* FIFO interrupt enabled. */
1908 #define FXLS8471Q_CTRL_REG4_INT_EN_ASLP_DISABLED ((uint8_t) 0x00) /* Auto-SLEEP/WAKE interrupt disabled. */
1909 #define FXLS8471Q_CTRL_REG4_INT_EN_ASLP_ENABLED ((uint8_t) 0x80) /* Auto-SLEEP/WAKE interrupt enabled. */
1910 /*------------------------------*/
1911 
1912 
1913 
1914 /*--------------------------------
1915 ** Register: CTRL_REG5
1916 ** Enum: FXLS8471Q_CTRL_REG5
1917 ** --
1918 ** Offset : 0x2E - Interrupt Configuration Register.
1919 ** ------------------------------*/
1920 typedef union {
1921  struct {
1922  uint8_t int_cfg_drdy : 1; /* - INT1/INT2 Configuration. */
1923 
1924  uint8_t int_cfg_a_vecm : 1; /* Acceleration vector-magnitude interrupt routing */
1925 
1926  uint8_t int_cfg_ff_mt : 1; /* - INT1/INT2 Configuration. */
1927 
1928  uint8_t int_cfg_pulse : 1; /* - INT1/INT2 Configuration. */
1929 
1930  uint8_t int_cfg_lndprt : 1; /* - INT1/INT2 Configuration. */
1931 
1932  uint8_t int_cfg_trans : 1; /* - INT1/INT2 Configuration. */
1933 
1934  uint8_t int_cfg_fifo : 1; /* - INT1/INT2 Configuration. */
1935 
1936  uint8_t int_cfg_aslp : 1; /* - INT1/INT2 Configuration. */
1937 
1938  } b;
1939  uint8_t w;
1940 } FXLS8471Q_CTRL_REG5_t;
1941 
1942 
1943 /*
1944 ** CTRL_REG5 - Bit field mask definitions
1945 */
1946 #define FXLS8471Q_CTRL_REG5_INT_CFG_DRDY_MASK ((uint8_t) 0x01)
1947 #define FXLS8471Q_CTRL_REG5_INT_CFG_DRDY_SHIFT ((uint8_t) 0)
1948 
1949 #define FXLS8471Q_CTRL_REG5_INT_CFG_A_VECM_MASK ((uint8_t) 0x02)
1950 #define FXLS8471Q_CTRL_REG5_INT_CFG_A_VECM_SHIFT ((uint8_t) 1)
1951 
1952 #define FXLS8471Q_CTRL_REG5_INT_CFG_FF_MT_MASK ((uint8_t) 0x04)
1953 #define FXLS8471Q_CTRL_REG5_INT_CFG_FF_MT_SHIFT ((uint8_t) 2)
1954 
1955 #define FXLS8471Q_CTRL_REG5_INT_CFG_PULSE_MASK ((uint8_t) 0x08)
1956 #define FXLS8471Q_CTRL_REG5_INT_CFG_PULSE_SHIFT ((uint8_t) 3)
1957 
1958 #define FXLS8471Q_CTRL_REG5_INT_CFG_LNDPRT_MASK ((uint8_t) 0x10)
1959 #define FXLS8471Q_CTRL_REG5_INT_CFG_LNDPRT_SHIFT ((uint8_t) 4)
1960 
1961 #define FXLS8471Q_CTRL_REG5_INT_CFG_TRANS_MASK ((uint8_t) 0x20)
1962 #define FXLS8471Q_CTRL_REG5_INT_CFG_TRANS_SHIFT ((uint8_t) 5)
1963 
1964 #define FXLS8471Q_CTRL_REG5_INT_CFG_FIFO_MASK ((uint8_t) 0x40)
1965 #define FXLS8471Q_CTRL_REG5_INT_CFG_FIFO_SHIFT ((uint8_t) 6)
1966 
1967 #define FXLS8471Q_CTRL_REG5_INT_CFG_ASLP_MASK ((uint8_t) 0x80)
1968 #define FXLS8471Q_CTRL_REG5_INT_CFG_ASLP_SHIFT ((uint8_t) 7)
1969 
1970 
1971 /*
1972 ** CTRL_REG5 - Bit field value definitions
1973 */
1974 #define FXLS8471Q_CTRL_REG5_INT_CFG_DRDY_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1975 #define FXLS8471Q_CTRL_REG5_INT_CFG_DRDY_INT1 ((uint8_t) 0x01) /* Interrupt is routed to INT1 pin. */
1976 #define FXLS8471Q_CTRL_REG5_INT_CFG_A_VECM_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1977 #define FXLS8471Q_CTRL_REG5_INT_CFG_A_VECM_INT1 ((uint8_t) 0x02) /* Interrupt is routed to INT1 pin. */
1978 #define FXLS8471Q_CTRL_REG5_INT_CFG_FF_MT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1979 #define FXLS8471Q_CTRL_REG5_INT_CFG_FF_MT_INT1 ((uint8_t) 0x04) /* Interrupt is routed to INT1 pin. */
1980 #define FXLS8471Q_CTRL_REG5_INT_CFG_PULSE_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1981 #define FXLS8471Q_CTRL_REG5_INT_CFG_PULSE_INT1 ((uint8_t) 0x08) /* Interrupt is routed to INT1 pin. */
1982 #define FXLS8471Q_CTRL_REG5_INT_CFG_LNDPRT_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1983 #define FXLS8471Q_CTRL_REG5_INT_CFG_LNDPRT_INT1 ((uint8_t) 0x10) /* Interrupt is routed to INT1 pin. */
1984 #define FXLS8471Q_CTRL_REG5_INT_CFG_TRANS_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1985 #define FXLS8471Q_CTRL_REG5_INT_CFG_TRANS_INT1 ((uint8_t) 0x20) /* Interrupt is routed to INT1 pin. */
1986 #define FXLS8471Q_CTRL_REG5_INT_CFG_FIFO_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1987 #define FXLS8471Q_CTRL_REG5_INT_CFG_FIFO_INT1 ((uint8_t) 0x40) /* Interrupt is routed to INT1 pin. */
1988 #define FXLS8471Q_CTRL_REG5_INT_CFG_ASLP_INT2 ((uint8_t) 0x00) /* Interrupt is routed to INT2 pin. */
1989 #define FXLS8471Q_CTRL_REG5_INT_CFG_ASLP_INT1 ((uint8_t) 0x80) /* Interrupt is routed to INT1 pin. */
1990 /*------------------------------*/
1991 
1992 
1993 
1994 /*--------------------------------
1995 ** Register: OFF_X
1996 ** Enum: FXLS8471Q_OFF_X
1997 ** --
1998 ** Offset : 0x2F - Offset Correction X Register.
1999 ** ------------------------------*/
2000 typedef union {
2001  struct {
2002  uint8_t d; /* - X-axis offset value. */
2003 
2004  } b;
2005  uint8_t w;
2006 } FXLS8471Q_OFF_X_t;
2007 
2008 
2009 /*
2010 ** OFF_X - Bit field mask definitions
2011 */
2012 #define FXLS8471Q_OFF_X_D_MASK ((uint8_t) 0xFF)
2013 #define FXLS8471Q_OFF_X_D_SHIFT ((uint8_t) 0)
2014 
2015 
2016 /*------------------------------*/
2017 
2018 
2019 
2020 /*--------------------------------
2021 ** Register: OFF_Y
2022 ** Enum: FXLS8471Q_OFF_Y
2023 ** --
2024 ** Offset : 0x30 - Offset Correction Y Register.
2025 ** ------------------------------*/
2026 typedef union {
2027  struct {
2028  uint8_t d; /* - Y-axis offset value. */
2029 
2030  } b;
2031  uint8_t w;
2032 } FXLS8471Q_OFF_Y_t;
2033 
2034 
2035 /*
2036 ** OFF_Y - Bit field mask definitions
2037 */
2038 #define FXLS8471Q_OFF_Y_D_MASK ((uint8_t) 0xFF)
2039 #define FXLS8471Q_OFF_Y_D_SHIFT ((uint8_t) 0)
2040 
2041 
2042 /*------------------------------*/
2043 
2044 
2045 
2046 /*--------------------------------
2047 ** Register: OFF_Z
2048 ** Enum: FXLS8471Q_OFF_Z
2049 ** --
2050 ** Offset : 0x31 - Offset Correction Z Register.
2051 ** ------------------------------*/
2052 typedef union {
2053  struct {
2054  uint8_t d; /* - Z-axis offset value. */
2055 
2056  } b;
2057  uint8_t w;
2058 } FXLS8471Q_OFF_Z_t;
2059 
2060 
2061 /*
2062 ** OFF_Z - Bit field mask definitions
2063 */
2064 #define FXLS8471Q_OFF_Z_D_MASK ((uint8_t) 0xFF)
2065 #define FXLS8471Q_OFF_Z_D_SHIFT ((uint8_t) 0)
2066 
2067 
2068 /*------------------------------*/
2069 
2070 
2071 
2072 /*--------------------------------
2073 ** Register: A_VECM_CFG
2074 ** Enum: FXLS8471Q_A_VECM_CFG
2075 ** --
2076 ** Offset : 0x5F - Acceleration vectormagnitude configuration register
2077 ** ------------------------------*/
2078 typedef union {
2079  struct {
2080  uint8_t _reserved_ : 3;
2081  uint8_t a_vecm_ele : 1; /* - Control bit a_vecm_ele defines the event latch enable mode. */
2082 
2083  uint8_t a_vecm_initm : 1; /* - Control bit a_vecm_initm defines how the initial reference values */
2084  /* (x_ref, y_ref, and z_ref) are chosen */
2085 
2086  uint8_t a_vecm_updm : 1; /* - How the reference values are updated once the vector-magnitude function */
2087  /* has been triggered. */
2088 
2089  uint8_t a_vecm_en : 1; /* - The accelerometer vector-magnitude function enable/disable */
2090 
2091  } b;
2092  uint8_t w;
2093 } FXLS8471Q_A_VECM_CFG_t;
2094 
2095 
2096 /*
2097 ** A_VECM_CFG - Bit field mask definitions
2098 */
2099 #define FXLS8471Q_A_VECM_CFG_A_VECM_ELE_MASK ((uint8_t) 0x08)
2100 #define FXLS8471Q_A_VECM_CFG_A_VECM_ELE_SHIFT ((uint8_t) 3)
2101 
2102 #define FXLS8471Q_A_VECM_CFG_A_VECM_INITM_MASK ((uint8_t) 0x10)
2103 #define FXLS8471Q_A_VECM_CFG_A_VECM_INITM_SHIFT ((uint8_t) 4)
2104 
2105 #define FXLS8471Q_A_VECM_CFG_A_VECM_UPDM_MASK ((uint8_t) 0x20)
2106 #define FXLS8471Q_A_VECM_CFG_A_VECM_UPDM_SHIFT ((uint8_t) 5)
2107 
2108 #define FXLS8471Q_A_VECM_CFG_A_VECM_EN_MASK ((uint8_t) 0x40)
2109 #define FXLS8471Q_A_VECM_CFG_A_VECM_EN_SHIFT ((uint8_t) 6)
2110 
2111 
2112 /*
2113 ** A_VECM_CFG - Bit field value definitions
2114 */
2115 #define FXLS8471Q_A_VECM_CFG_A_VECM_ELE_EN ((uint8_t) 0x08) /* The interrupt flag is latched in and held until */
2116  /* the host application reads the INT_SOURCE */
2117  /* register(0x0C) */
2118 #define FXLS8471Q_A_VECM_CFG_A_VECM_ELE_DIS ((uint8_t) 0x00) /* Event latching is disabled */
2119 #define FXLS8471Q_A_VECM_CFG_A_VECM_INITM_EN ((uint8_t) 0x10) /* The function uses the data from */
2120  /* A_VECM_INIT_X/Y/Z registers as the initial */
2121  /* reference values */
2122 #define FXLS8471Q_A_VECM_CFG_A_VECM_INITM_DIS ((uint8_t) 0x00) /* The function uses the current x/y/z */
2123  /* accelerometer output data at the time when the */
2124  /* vector magnitude function is enabled */
2125 #define FXLS8471Q_A_VECM_CFG_A_VECM_UPDM_EN ((uint8_t) 0x20) /* The function does not update the reference */
2126  /* values when the interrupt is triggered. */
2127 #define FXLS8471Q_A_VECM_CFG_A_VECM_UPDM_DIS ((uint8_t) 0x00) /* The function updates the reference value with */
2128  /* the current x, y, and z accelerometer output */
2129  /* data values. */
2130 #define FXLS8471Q_A_VECM_CFG_A_VECM_EN_EN ((uint8_t) 0x40) /* The accelerometer vector-magnitude function is */
2131  /* enabled. */
2132 #define FXLS8471Q_A_VECM_CFG_A_VECM_EN_DIS ((uint8_t) 0x00) /* The accelerometer vector-magnitude function is */
2133  /* disabled. */
2134 /*------------------------------*/
2135 
2136 
2137 
2138 /*--------------------------------
2139 ** Register: A_VECM_THS_MSB
2140 ** Enum: FXLS8471Q_A_VECM_THS_MSB
2141 ** --
2142 ** Offset : 0x60 - Acceleration vectormagnitude threshold MSB
2143 ** ------------------------------*/
2144 typedef union {
2145  struct {
2146  uint8_t a_vecm_ths : 5; /* Five MSBs of the 13-bit unsigned A_VECM_THS value */
2147 
2148  uint8_t _reserved_ : 2;
2149  uint8_t a_vecm_dbcntm : 1; /* How the debounce timer is reset when the condition for triggering the */
2150  /* interrupt is no longer true */
2151 
2152  } b;
2153  uint8_t w;
2154 } FXLS8471Q_A_VECM_THS_MSB_t;
2155 
2156 
2157 /*
2158 ** A_VECM_THS_MSB - Bit field mask definitions
2159 */
2160 #define FXLS8471Q_A_VECM_THS_MSB_A_VECM_THS_MASK ((uint8_t) 0x1F)
2161 #define FXLS8471Q_A_VECM_THS_MSB_A_VECM_THS_SHIFT ((uint8_t) 0)
2162 
2163 #define FXLS8471Q_A_VECM_THS_MSB_A_VECM_DBCNTM_MASK ((uint8_t) 0x80)
2164 #define FXLS8471Q_A_VECM_THS_MSB_A_VECM_DBCNTM_SHIFT ((uint8_t) 7)
2165 
2166 
2167 /*------------------------------*/
2168 
2169 
2170 
2171 /*--------------------------------
2172 ** Register: A_VECM_THS_LSB
2173 ** Enum: FXLS8471Q_A_VECM_THS_LSB
2174 ** --
2175 ** Offset : 0x61 - Acceleration vectormagnitude threshold LSB
2176 ** ------------------------------*/
2177 typedef uint8_t FXLS8471Q_A_VECM_THS_LSB_t;
2178 
2179 
2180 
2181 /*--------------------------------
2182 ** Register: A_VECM_CNT
2183 ** Enum: FXLS8471Q_A_VECM_CNT
2184 ** --
2185 ** Offset : 0x62 - Acceleration vectormagnitude debounce count
2186 ** ------------------------------*/
2187 typedef union {
2188  struct {
2189  uint8_t a_vecm_cnt; /* Vector-magnitude function debounce count value. */
2190 
2191  } b;
2192  uint8_t w;
2193 } FXLS8471Q_A_VECM_CNT_t;
2194 
2195 
2196 /*
2197 ** A_VECM_CNT - Bit field mask definitions
2198 */
2199 #define FXLS8471Q_A_VECM_CNT_A_VECM_CNT_MASK ((uint8_t) 0xFF)
2200 #define FXLS8471Q_A_VECM_CNT_A_VECM_CNT_SHIFT ((uint8_t) 0)
2201 
2202 
2203 /*------------------------------*/
2204 
2205 
2206 
2207 /*--------------------------------
2208 ** Register: A_VECM_INITX_MSB
2209 ** Enum: FXLS8471Q_A_VECM_INITX_MSB
2210 ** --
2211 ** Offset 0x63 - Acceleration vectormagnitude X-axis reference value MSB
2212 ** ------------------------------*/
2213 typedef union {
2214  struct {
2215  uint8_t a_vecm_initx : 6; /* Most significant 6 bits of the signed 14-bit initial X-axis value */
2216 
2217  } b;
2218  uint8_t w;
2219 } FXLS8471Q_A_VECM_INITX_MSB_t;
2220 
2221 
2222 /*
2223 ** A_VECM_INITX_MSB - Bit field mask definitions
2224 */
2225 #define FXLS8471Q_A_VECM_INITX_MSB_A_VECM_INITX_MASK ((uint8_t) 0x3F)
2226 #define FXLS8471Q_A_VECM_INITX_MSB_A_VECM_INITX_SHIFT ((uint8_t) 0)
2227 
2228 
2229 /*------------------------------*/
2230 
2231 
2232 
2233 /*--------------------------------
2234 ** Register: A_VECM_INITX_LSB
2235 ** Enum: FXLS8471Q_A_VECM_INITX_LSB
2236 ** --
2237 ** Offset 0x64 - Acceleration vectormagnitude X-axis reference value LSB
2238 ** ------------------------------*/
2239 typedef uint8_t FXLS8471Q_A_VECM_INITX_LSB_t;
2240 
2241 
2242 
2243 /*--------------------------------
2244 ** Register: A_VECM_INITY_MSB
2245 ** Enum: FXLS8471Q_A_VECM_INITY_MSB
2246 ** --
2247 ** Offset 0x65 - Acceleration vectormagnitude Y-axis reference value MSB
2248 ** ------------------------------*/
2249 typedef union {
2250  struct {
2251  uint8_t a_vecm_inity : 6; /* Most significant 6 bits of the signed 14-bit initial Y-axis value */
2252 
2253  } b;
2254  uint8_t w;
2255 } FXLS8471Q_A_VECM_INITY_MSB_t;
2256 
2257 
2258 /*
2259 ** A_VECM_INITY_MSB - Bit field mask definitions
2260 */
2261 #define FXLS8471Q_A_VECM_INITY_MSB_A_VECM_INITY_MASK ((uint8_t) 0x3F)
2262 #define FXLS8471Q_A_VECM_INITY_MSB_A_VECM_INITY_SHIFT ((uint8_t) 0)
2263 
2264 
2265 /*------------------------------*/
2266 
2267 
2268 
2269 /*--------------------------------
2270 ** Register: A_VECM_INITY_LSB
2271 ** Enum: FXLS8471Q_A_VECM_INITY_LSB
2272 ** --
2273 ** Offset 0x66 - Acceleration vectormagnitude y-axis reference value LSB
2274 ** ------------------------------*/
2275 typedef uint8_t FXLS8471Q_A_VECM_INITY_LSB_t;
2276 
2277 
2278 
2279 /*--------------------------------
2280 ** Register: A_VECM_INITZ_MSB
2281 ** Enum: FXLS8471Q_A_VECM_INITZ_MSB
2282 ** --
2283 ** Offset 0x67 - Acceleration vectormagnitude Y-axis reference value MSB
2284 ** ------------------------------*/
2285 typedef union {
2286  struct {
2287  uint8_t a_vecm_initz : 6; /* Most significant 6 bits of the signed 14-bit initial Z-axis value */
2288 
2289  } b;
2290  uint8_t w;
2291 } FXLS8471Q_A_VECM_INITZ_MSB_t;
2292 
2293 
2294 /*
2295 ** A_VECM_INITZ_MSB - Bit field mask definitions
2296 */
2297 #define FXLS8471Q_A_VECM_INITZ_MSB_A_VECM_INITZ_MASK ((uint8_t) 0x3F)
2298 #define FXLS8471Q_A_VECM_INITZ_MSB_A_VECM_INITZ_SHIFT ((uint8_t) 0)
2299 
2300 
2301 /*------------------------------*/
2302 
2303 
2304 
2305 /*--------------------------------
2306 ** Register: A_VECM_INITZ_LSB
2307 ** Enum: FXLS8471Q_A_VECM_INITZ_LSB
2308 ** --
2309 ** Offset 0x68 - Acceleration vectormagnitude Z-axis reference value LSB
2310 ** ------------------------------*/
2311 typedef uint8_t FXLS8471Q_A_VECM_INITZ_LSB_t;
2312 
2313 
2314 
2315 /*--------------------------------
2316 ** Register: A_FFMT_THS_X_MSB
2317 ** Enum: FXLS8471Q_A_FFMT_THS_X_MSB
2318 ** --
2319 ** Offset 0x73 - X-axis FMT threshold MSB
2320 ** ------------------------------*/
2321 typedef union {
2322  struct {
2323  uint8_t a_ffmt_ths_x : 7; /* 7-bit MSB of X-axis acceleration threshold */
2324 
2325  uint8_t a_ffmt_ths_xyz_en : 1;
2326  } b;
2327  uint8_t w;
2328 } FXLS8471Q_A_FFMT_THS_X_MSB_t;
2329 
2330 
2331 /*
2332 ** A_FFMT_THS_X_MSB - Bit field mask definitions
2333 */
2334 #define FXLS8471Q_A_FFMT_THS_X_MSB_A_FFMT_THS_X_MASK ((uint8_t) 7F)
2335 #define FXLS8471Q_A_FFMT_THS_X_MSB_A_FFMT_THS_X_SHIFT ((uint8_t) 0)
2336 
2337 #define FXLS8471Q_A_FFMT_THS_X_MSB_A_FFMT_THS_XYZ_EN_MASK ((uint8_t) 0x80)
2338 #define FXLS8471Q_A_FFMT_THS_X_MSB_A_FFMT_THS_XYZ_EN_SHIFT ((uint8_t) 7)
2339 
2340 
2341 /*
2342 ** A_FFMT_THS_X_MSB - Bit field value definitions
2343 */
2344 #define FXLS8471Q_A_FFMT_THS_X_MSB_A_FFMT_THS_XYZ_EN_EN ((uint8_t) 0x80) /* the ASIC ignores the common 7-bit */
2345  /* G_FFMT_THS value located in register x17 */
2346  /* when executing the FFMT function, and the */
2347  /* following independent threshold values are */
2348  /* used for each axis */
2349 #define FXLS8471Q_A_FFMT_THS_X_MSB_A_FFMT_THS_XYZ_EN_DIS ((uint8_t) 0x00) /* the ASIC uses the ffmt_ths[6:0] value */
2350  /* located in register x17[6:0] as a common */
2351  /* threshold for the X, Y, and Z-axis */
2352  /* acceleration detection. The common */
2353  /* unsigned 7-bit acceleration threshold has */
2354  /* a fixed resolution of 63 mg/LSB, with a */
2355  /* range of 0-127 counts */
2356 /*------------------------------*/
2357 
2358 
2359 
2360 /*--------------------------------
2361 ** Register: A_FFMT_THS_X_LSB
2362 ** Enum: FXLS8471Q_A_FFMT_THS_X_LSB
2363 ** --
2364 ** Offset 0x74 - X-axis FMT threshold LSB
2365 ** ------------------------------*/
2366 typedef union {
2367  struct {
2368  uint8_t a_ffmt_ths_x : 6;
2369  } b;
2370  uint8_t w;
2371 } FXLS8471Q_A_FFMT_THS_X_LSB_t;
2372 
2373 
2374 /*
2375 ** A_FFMT_THS_X_LSB - Bit field mask definitions
2376 */
2377 #define FXLS8471Q_A_FFMT_THS_X_LSB_A_FFMT_THS_X_MASK ((uint8_t) 0x3F)
2378 #define FXLS8471Q_A_FFMT_THS_X_LSB_A_FFMT_THS_X_SHIFT ((uint8_t) 0)
2379 
2380 
2381 /*------------------------------*/
2382 
2383 
2384 
2385 /*--------------------------------
2386 ** Register: A_FFMT_THS_Y_MSB
2387 ** Enum: FXLS8471Q_A_FFMT_THS_Y_MSB
2388 ** --
2389 ** Offset 0x75 - Y-axis FMT threshold MSB
2390 ** ------------------------------*/
2391 typedef union {
2392  struct {
2393  uint8_t a_ffmt_ths_y : 7;
2394  uint8_t a_ffmt_trans_ths_en : 1;
2395  } b;
2396  uint8_t w;
2397 } FXLS8471Q_A_FFMT_THS_Y_MSB_t;
2398 
2399 
2400 /*
2401 ** A_FFMT_THS_Y_MSB - Bit field mask definitions
2402 */
2403 #define FXLS8471Q_A_FFMT_THS_Y_MSB_A_FFMT_THS_Y_MASK ((uint8_t) 0x7F)
2404 #define FXLS8471Q_A_FFMT_THS_Y_MSB_A_FFMT_THS_Y_SHIFT ((uint8_t) 0)
2405 
2406 #define FXLS8471Q_A_FFMT_THS_Y_MSB_A_FFMT_TRANS_THS_EN_MASK ((uint8_t) 0x80)
2407 #define FXLS8471Q_A_FFMT_THS_Y_MSB_A_FFMT_TRANS_THS_EN_SHIFT ((uint8_t) 7)
2408 
2409 
2410 /*------------------------------*/
2411 
2412 
2413 
2414 /*--------------------------------
2415 ** Register: A_FFMT_THS_Y_LSB
2416 ** Enum: FXLS8471Q_A_FFMT_THS_Y_LSB
2417 ** --
2418 ** Offset 0x76 - Y-axis FMT threshold LSB
2419 ** ------------------------------*/
2420 typedef union {
2421  struct {
2422  uint8_t a_ffmt_ths_y : 6;
2423  } b;
2424  uint8_t w;
2425 } FXLS8471Q_A_FFMT_THS_Y_LSB_t;
2426 
2427 
2428 /*
2429 ** A_FFMT_THS_Y_LSB - Bit field mask definitions
2430 */
2431 #define FXLS8471Q_A_FFMT_THS_Y_LSB_A_FFMT_THS_Y_MASK ((uint8_t) 0x3F)
2432 #define FXLS8471Q_A_FFMT_THS_Y_LSB_A_FFMT_THS_Y_SHIFT ((uint8_t) 0)
2433 
2434 
2435 /*------------------------------*/
2436 
2437 
2438 
2439 /*--------------------------------
2440 ** Register: A_FFMT_THS_Z_MSB
2441 ** Enum: FXLS8471Q_A_FFMT_THS_Z_MSB
2442 ** --
2443 ** Offset 0x77 - Z-axis FMT threshold MSB
2444 ** ------------------------------*/
2445 typedef union {
2446  struct {
2447  uint8_t a_ffmt_ths_z : 7;
2448  } b;
2449  uint8_t w;
2450 } FXLS8471Q_A_FFMT_THS_Z_MSB_t;
2451 
2452 
2453 /*
2454 ** A_FFMT_THS_Z_MSB - Bit field mask definitions
2455 */
2456 #define FXLS8471Q_A_FFMT_THS_Z_MSB_A_FFMT_THS_Z_MASK ((uint8_t) 0x7F)
2457 #define FXLS8471Q_A_FFMT_THS_Z_MSB_A_FFMT_THS_Z_SHIFT ((uint8_t) 0)
2458 
2459 
2460 /*------------------------------*/
2461 
2462 
2463 
2464 /*--------------------------------
2465 ** Register: A_FFMT_THS_Z_LSB
2466 ** Enum: FXLS8471Q_A_FFMT_THS_Z_LSB
2467 ** --
2468 ** Offset 0x78 - Z-axis FMT threshold LSB
2469 ** ------------------------------*/
2470 typedef union {
2471  struct {
2472  uint8_t a_ffmt_ths_x : 6;
2473  } b;
2474  uint8_t w;
2475 } FXLS8471Q_A_FFMT_THS_Z_LSB_t;
2476 
2477 
2478 /*
2479 ** A_FFMT_THS_Z_LSB - Bit field mask definitions
2480 */
2481 #define FXLS8471Q_A_FFMT_THS_Z_LSB_A_FFMT_THS_X_MASK ((uint8_t) 0x3F)
2482 #define FXLS8471Q_A_FFMT_THS_Z_LSB_A_FFMT_THS_X_SHIFT ((uint8_t) 0)
2483 
2484 
2485 /*------------------------------*/
2486 
2487 
2488 #endif /* _FXLS8471Q_H_ */
FXLS8471Q_A_VECM_THS_LSB_t
uint8_t FXLS8471Q_A_VECM_THS_LSB_t
Definition: fxls8471q.h:2177
FXLS8471Q_A_VECM_INITZ_LSB_t
uint8_t FXLS8471Q_A_VECM_INITZ_LSB_t
Definition: fxls8471q.h:2311
FXLS8471Q_OUT_Z_LSB_t
uint8_t FXLS8471Q_OUT_Z_LSB_t
Definition: fxls8471q.h:268
FXLS8471Q_A_VECM_INITY_LSB_t
uint8_t FXLS8471Q_A_VECM_INITY_LSB_t
Definition: fxls8471q.h:2275
FXLS8471Q_OUT_Z_MSB_t
uint8_t FXLS8471Q_OUT_Z_MSB_t
Definition: fxls8471q.h:259
FXLS8471Q_OUT_X_LSB_t
uint8_t FXLS8471Q_OUT_X_LSB_t
Definition: fxls8471q.h:230
FXLS8471Q_A_VECM_INITX_LSB_t
uint8_t FXLS8471Q_A_VECM_INITX_LSB_t
Definition: fxls8471q.h:2239
FXLS8471Q_OUT_Y_MSB_t
uint8_t FXLS8471Q_OUT_Y_MSB_t
Definition: fxls8471q.h:240
FXLS8471Q_OUT_Y_LSB_t
uint8_t FXLS8471Q_OUT_Y_LSB_t
Definition: fxls8471q.h:249
FXLS8471Q_OUT_X_MSB_t
uint8_t FXLS8471Q_OUT_X_MSB_t
Definition: fxls8471q.h:221
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