ISSDK  1.8
IoT Sensing Software Development Kit
dbap.h
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1 /*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 /**
8  * @file dbap.h
9  * @brief The fxps7250.h contains the FXPS7250 pressure sensor register definitions, access macros, and
10  * its bit mask.
11  */
12 #ifndef FXPS7250_H_
13 #define FXPS7250_H_
14 
15 #define FXPS7250D4_WHOAMI_VALUE (0xC4)
16 
17 /**
18  **
19  ** FXPS7250 Sensor Internal Registers
20  */
21 enum {
22  FXPS7250_COUNT = 0x00,
23  FXPS7250_DEVSTAT = 0x01,
24  FXPS7250_DEVSTAT1 = 0x02,
25  FXPS7250_DEVSTAT2 = 0x03,
26  FXPS7250_DEVSTAT3 = 0x04,
27  /* Reserved: 0x05 - 0x0D */
28  FXPS7250_TEMPERATURE = 0x0E,
29  /* Reserved: 0x0F - 0x0F */
30  FXPS7250_DEVLOCK_WR = 0x10,
31  /* Reserved: 0x11 - 0x13 */
32  FXPS7250_UF_REGION_W = 0x14,
33  FXPS7250_UF_REGION_R = 0x15,
34  FXPS7250_COMMTYPE = 0x16,
35  /* Reserved: 0x17 - 0x19 */
36  FXPS7250_SOURCEID_0 = 0x1A,
37  FXPS7250_SOURCEID_1 = 0x1B,
38  /* Reserved: 0x1C - 0x21 */
39  FXPS7250_TIMING_CFG = 0x22,
40  /* Reserved: 0x22 - 0x3C */
41  FXPS7250_SPI_CFG = 0x3D,
42  FXPS7250_WHO_AM_I = 0x3E,
43  FXPS7250_I2C_ADDRESS = 0x3F,
44  FXPS7250_DSP_CFG_U1 = 0x40,
45  FXPS7250_DSP_CFG_U2 = 0x41,
46  FXPS7250_DSP_CFG_U3 = 0x42,
47  FXPS7250_DSP_CFG_U4 = 0x43,
48  FXPS7250_DSP_CFG_U5 = 0x44,
49  FXPS7250_INT_CFG = 0x45,
50  FXPS7250_P_INT_HI_L = 0x46,
51  FXPS7250_P_INT_HI_H = 0x47,
52  FXPS7250_P_INT_LO_L = 0x48,
53  FXPS7250_P_INT_LO_H = 0x49,
54  /* Reserved: 0x4A - 0x4B */
55  FXPS7250_P_CAL_ZERO_L = 0x4C,
56  FXPS7250_P_CAL_ZERO_H = 0x4D,
57  /* Reserved: 0x4E - 0x5E */
58  FXPS7250_DSP_STAT = 0x60,
59  FXPS7250_DEVSTAT_COPY = 0x61,
60  FXPS7250_SNSDATA0_L = 0x62,
61  FXPS7250_SNSDATA0_H = 0x63,
62  FXPS7250_SNSDATA1_L = 0x64,
63  FXPS7250_SNSDATA1_H = 0x65,
64  FXPS7250_SNSDATA0_TIME0 = 0x66,
65  FXPS7250_SNSDATA0_TIME1 = 0x67,
66  FXPS7250_SNSDATA0_TIME2 = 0x68,
67  FXPS7250_SNSDATA0_TIME3 = 0x69,
68  FXPS7250_SNSDATA0_TIME4 = 0x6A,
69  FXPS7250_SNSDATA0_TIME5 = 0x6B,
70  FXPS7250_P_MAX_L = 0x6C,
71  FXPS7250_P_MAX_H = 0x6D,
72  FXPS7250_P_MIN_L = 0x6E,
73  FXPS7250_P_MIN_H = 0x6F,
74  /* Reserved: 0x70 - 0x77 */
75  FXPS7250_FRT0 = 0x78,
76  FXPS7250_FRT1 = 0x79,
77  FXPS7250_FRT2 = 0x7A,
78  FXPS7250_FRT3 = 0x7B,
79  FXPS7250_FRT4 = 0x7C,
80  FXPS7250_FRT5 = 0x7D,
81  /* Reserved: 0x7E - 0x9F */
82  FXPS7250_DSP_CFG_F = 0xA0,
83  /* Reserved: 0xA1 - 0xAE */
84  FXPS7250_CRC_F_A = 0xAF,
85  /* Reserved: 0xB0 - 0xBE */
86  FXPS7250_CRC_F_B = 0xBF,
87  FXPS7250_ICTYPEID = 0xC0,
88  FXPS7250_ICREVID = 0xC1,
89  FXPS7250_ICMFGID = 0xC2,
90  /* Reserved: 0xC3 - 0xC3 */
91  FXPS7250_PN0 = 0xC4,
92  FXPS7250_PN1 = 0xC5,
93  FXPS7250_SN0 = 0xC6,
94  FXPS7250_SN1 = 0xC7,
95  FXPS7250_SN2 = 0xC8,
96  FXPS7250_SN3 = 0xC9,
97  FXPS7250_SN4 = 0xCA,
98  FXPS7250_ASICWFR = 0xCB,
99  FXPS7250_ASICWFR_X = 0xCC,
100  FXPS7250_ASICWFR_Y = 0xCD,
101  /* Reserved: 0xCE - 0xCE */
102  FXPS7250_CRC_F_C = 0xCF,
103  FXPS7250_ASICWLOT_L = 0xD0,
104  FXPS7250_ASICWLOT_H = 0xD1,
105  /* Reserved: 0xD2 - 0xDE */
106  FXPS7250_CRC_F_D = 0xDF,
107  FXPS7250_USERDATA_0 = 0xE0,
108  FXPS7250_USERDATA_1 = 0xE1,
109  FXPS7250_USERDATA_2 = 0xE2,
110  FXPS7250_USERDATA_3 = 0xE3,
111  FXPS7250_USERDATA_4 = 0xE4,
112  FXPS7250_USERDATA_5 = 0xE5,
113  FXPS7250_USERDATA_6 = 0xE6,
114  FXPS7250_USERDATA_7 = 0xE7,
115  FXPS7250_USERDATA_8 = 0xE8,
116  FXPS7250_USERDATA_9 = 0xE9,
117  FXPS7250_USERDATA_A = 0xEA,
118  FXPS7250_USERDATA_B = 0xEB,
119  FXPS7250_USERDATA_C = 0xEC,
120  FXPS7250_USERDATA_D = 0xED,
121  FXPS7250_USERDATA_E = 0xEE,
122  FXPS7250_CRC_UF0 = 0xEF,
123  FXPS7250_USERDATA_10 = 0xF0,
124  FXPS7250_USERDATA_11 = 0xF1,
125  FXPS7250_USERDATA_12 = 0xF2,
126  FXPS7250_USERDATA_13 = 0xF3,
127  FXPS7250_USERDATA_14 = 0xF4,
128  FXPS7250_USERDATA_15 = 0xF5,
129  FXPS7250_USERDATA_16 = 0xF6,
130  FXPS7250_USERDATA_17 = 0xF7,
131  FXPS7250_USERDATA_18 = 0xF8,
132  FXPS7250_USERDATA_19 = 0xF9,
133  FXPS7250_USERDATA_1A = 0xFA,
134  FXPS7250_USERDATA_1B = 0xFB,
135  FXPS7250_USERDATA_1C = 0xFC,
136  FXPS7250_USERDATA_1D = 0xFD,
137  FXPS7250_USERDATA_1E = 0xFE,
138  FXPS7250_CRC_UF1 = 0xFF,
139 };
140 
141 /*--------------------------------
142 ** Register: COUNT
143 ** Enum: FXPS7250_COUNT
144 ** --
145 ** Offset : 0x00 - Rolling counter register.
146 ** ------------------------------*/
147 typedef uint8_t FXPS7250_COUNT_t;
148 
149 /*--------------------------------
150 ** Register: DEVSTAT
151 ** Enum: FXPS7250_DEVSTAT
152 ** --
153 ** Offset : 0x01 - Device Status Register.
154 ** ------------------------------*/
155 typedef union {
156  struct {
157  uint8_t devinit : 1;
158  uint8_t devres : 1;
159  uint8_t testmode : 1;
160  uint8_t supply_err : 1;
161  uint8_t memtemp_err : 1;
162  uint8_t comm_err : 1;
163  uint8_t _reserved_ : 1;
164  uint8_t dsp_err : 1;
165  } b;
166  uint8_t w;
167 } FXPS7250_DEVSTAT_t;
168 
169 /*
170 ** DEVSTAT - Bit field mask definitions
171 */
172 #define FXPS7250_DEVSTAT_DEVINIT_MASK ((uint8_t) 0x01)
173 #define FXPS7250_DEVSTAT_DEVINIT_SHIFT ((uint8_t) 0)
174 
175 #define FXPS7250_DEVSTAT_DEVRES_MASK ((uint8_t) 0x02)
176 #define FXPS7250_DEVSTAT_DEVRES_SHIFT ((uint8_t) 1)
177 
178 #define FXPS7250_DEVSTAT_TESTMODE_MASK ((uint8_t) 0x04)
179 #define FXPS7250_DEVSTAT_TESTMODE_SHIFT ((uint8_t) 2)
180 
181 #define FXPS7250_DEVSTAT_SUPPLY_ERR_MASK ((uint8_t) 0x08)
182 #define FXPS7250_DEVSTAT_SUPPLY_ERR_SHIFT ((uint8_t) 3)
183 
184 #define FXPS7250_DEVSTAT_MEMTEMP_ERR_MASK ((uint8_t) 0x10)
185 #define FXPS7250_DEVSTAT_MEMTEMP_ERR_SHIFT ((uint8_t) 4)
186 
187 #define FXPS7250_DEVSTAT_COMM_ERR_MASK ((uint8_t) 0x20)
188 #define FXPS7250_DEVSTAT_COMM_ERR_SHIFT ((uint8_t) 5)
189 
190 #define FXPS7250_DEVSTAT_DSP_ERR_MASK ((uint8_t) 0x80)
191 #define FXPS7250_DEVSTAT_DSP_ERR_SHIFT ((uint8_t) 7)
192 
193 
194 /*
195 ** DEVSTAT - Bit field value definitions
196 */
197 #define FXPS7250_DEVSTAT_DEVINIT_INIT ((uint8_t) 0x01) /* Indicates if the device is initializing. */
198 #define FXPS7250_DEVSTAT_DEVINIT_NORMAL ((uint8_t) 0x00) /* Device is operating normally. */
199 #define FXPS7250_DEVSTAT_DEVRES_RESET ((uint8_t) 0x02) /* Indicates if the device has reset. */
200 #define FXPS7250_DEVSTAT_DEVRES_NOT_RESET ((uint8_t) 0x00) /* Device is operating normally. */
201 #define FXPS7250_DEVSTAT_TESTMODE_ISACTIVE ((uint8_t) 0x04) /* Indicates if the device is in test mode. */
202 #define FXPS7250_DEVSTAT_TESTMODE_INACTIVE ((uint8_t) 0x00) /* Test mode is not active. */
203 #define FXPS7250_DEVSTAT_SUPPLY_ERR ((uint8_t) 0x08) /* Indicates if an error is flagged in DEVSTAT1. */
204 #define FXPS7250_DEVSTAT_NOT_SUPPLY_ERR ((uint8_t) 0x00) /* No error is flagged in DEVSTAT1. */
205 #define FXPS7250_DEVSTAT_MEMTEMP_ERR ((uint8_t) 0x10) /* Indicates if an error is flagged in DEVSTAT2. */
206 #define FXPS7250_DEVSTAT_NOT_MEMTEMP_ERR ((uint8_t) 0x00) /* No error is flagged in DEVSTAT2. */
207 #define FXPS7250_DEVSTAT_COMM_ERR ((uint8_t) 0x20) /* Indicates if an error is flagged in DEVSTAT3. */
208 #define FXPS7250_DEVSTAT_NOT_COMM_ERR ((uint8_t) 0x00) /* No error is flagged in DEVSTAT3. */
209 #define FXPS7250_DEVSTAT_DSP_ERR ((uint8_t) 0x80) /* Indicates if an error is flagged in the pressure DSP. */
210 #define FXPS7250_DEVSTAT_NOT_DSP_ERR ((uint8_t) 0x00) /* No error is flagged in the pressure DSP. */
211 
212 /*--------------------------------
213 ** Register: DEVSTAT1
214 ** Enum: FXPS7250_DEVSTAT1
215 ** --
216 ** Offset : 0x02 - Device Status Register.
217 ** ------------------------------*/
218 typedef union {
219  struct {
220  uint8_t cont_err : 1;
221  uint8_t intregf_err : 1;
222  uint8_t intreg_err : 1;
223  uint8_t intrega_err : 1;
224  uint8_t _reserved1_ : 1;
225  uint8_t vccov_err : 1;
226  uint8_t _reserved2_ : 1;
227  uint8_t vccuv_err : 1;
228 
229  } b;
230  uint8_t w;
231 } FXPS7250_DEVSTAT1_t;
232 
233 
234 /*
235 ** DEVSTAT - Bit field mask definitions
236 */
237 #define FXPS7250_DEVSTAT1_CONT_ERR_MASK ((uint8_t) 0x01)
238 #define FXPS7250_DEVSTAT1_CONT_ERR_SHIFT ((uint8_t) 0)
239 
240 #define FXPS7250_DEVSTAT1_INTREGF_ERR_MASK ((uint8_t) 0x02)
241 #define FXPS7250_DEVSTAT1_INTREGF_ERR_SHIFT ((uint8_t) 1)
242 
243 #define FXPS7250_DEVSTAT1_INTREG_ERR_MASK ((uint8_t) 0x04)
244 #define FXPS7250_DEVSTAT1_INTREG_ERR_SHIFT ((uint8_t) 2)
245 
246 #define FXPS7250_DEVSTAT1_INTREGA_ERR_MASK ((uint8_t) 0x08)
247 #define FXPS7250_DEVSTAT1_INTREGA_ERR_SHIFT ((uint8_t) 3)
248 
249 #define FXPS7250_DEVSTAT1_VCCOV_ERR_MASK ((uint8_t) 0x20)
250 #define FXPS7250_DEVSTAT1_VCCOV_ERR_SHIFT ((uint8_t) 5)
251 
252 #define FXPS7250_DEVSTAT1_VCCUV_ERR_MASK ((uint8_t) 0x80)
253 #define FXPS7250_DEVSTAT1_VCCUV_ERR_SHIFT ((uint8_t) 7)
254 
255 
256 /*
257 ** DEVSTAT - Bit field value definitions
258 */
259 #define FXPS7250_DEVSTAT1_CONT_ERR ((uint8_t) 0x01) /* Indicates if an error is flagged by the continuity monitor. */
260 #define FXPS7250_DEVSTAT1_NO_CONT_ERR ((uint8_t) 0x00) /* No error is flagged by the continuity monitor. */
261 #define FXPS7250_DEVSTAT1_INTREGF_ERR ((uint8_t) 0x02) /* Indicates if the OTP regulator voltage is out of range. */
262 #define FXPS7250_DEVSTAT1_NO_INTREGF_ERR ((uint8_t) 0x00) /* The OTP regulator voltage is in range. */
263 #define FXPS7250_DEVSTAT1_INTREG_ERR ((uint8_t) 0x04) /* Indicates if the digital regulator voltage is out of range. */
264 #define FXPS7250_DEVSTAT1_NO_INTREG_ERR ((uint8_t) 0x00) /* The digital regulator voltage is in range. */
265 #define FXPS7250_DEVSTAT1_INTREGA_ERR ((uint8_t) 0x08) /* Indicates if the analog regulator voltage is out of range. */
266 #define FXPS7250_DEVSTAT1_NO_INTREGA_ERR ((uint8_t) 0x00) /* The analog regulator voltage is out of range. */
267 #define FXPS7250_DEVSTAT1_VCCOV_ERR ((uint8_t) 0x20) /* Indicates if the Vcc voltage goes above the recommended maximum level. */
268 #define FXPS7250_DEVSTAT1_NO_VCCOV_ERR ((uint8_t) 0x00) /* The Vcc voltage is below the recommended maximum level. */
269 #define FXPS7250_DEVSTAT1_VCCUV_ERR ((uint8_t) 0x80) /* Indicates if the Vcc voltage goes below the recommended minimum level. */
270 #define FXPS7250_DEVSTAT1_NO_VCCUV_ERR ((uint8_t) 0x00) /* The Vcc voltage is above the recommended minimum level. */
271 
272 /*--------------------------------
273 ** Register: DEVSTAT2
274 ** Enum: FXPS7250_DEVSTAT2
275 ** --
276 ** Offset : 0x03 - Device Status Register.
277 ** ------------------------------*/
278 typedef union {
279  struct {
280  uint8_t _reserved1_ : 2;
281  uint8_t temp0_err : 1;
282  uint8_t _reserved2_ : 1;
283  uint8_t u_w_active : 1;
284  uint8_t u_rw_err : 1;
285  uint8_t u_otp_err : 1;
286  uint8_t f_otp_err : 1;
287 
288  } b;
289  uint8_t w;
290 } FXPS7250_DEVSTAT2_t;
291 
292 
293 /*
294 ** DEVSTAT - Bit field mask definitions
295 */
296 #define FXPS7250_DEVSTAT2_TEMP0_ERR_MASK ((uint8_t) 0x04)
297 #define FXPS7250_DEVSTAT2_TEMP0_ERR_SHIFT ((uint8_t) 2)
298 
299 #define FXPS7250_DEVSTAT2_U_W_ACTIVE_MASK ((uint8_t) 0x10)
300 #define FXPS7250_DEVSTAT2_U_W_ACTIVE_SHIFT ((uint8_t) 4)
301 
302 #define FXPS7250_DEVSTAT2_U_RW_ERR_MASK ((uint8_t) 0x20)
303 #define FXPS7250_DEVSTAT2_U_RW_ERR_SHIFT ((uint8_t) 5)
304 
305 #define FXPS7250_DEVSTAT2_U_OTP_ERR_MASK ((uint8_t) 0x40)
306 #define FXPS7250_DEVSTAT2_U_OTP_ERR_SHIFT ((uint8_t) 6)
307 
308 #define FXPS7250_DEVSTAT2_F_OTP_ERR_MASK ((uint8_t) 0x80)
309 #define FXPS7250_DEVSTAT2_F_OTP_ERR_SHIFT ((uint8_t) 7)
310 
311 
312 /*
313 ** DEVSTAT - Bit field value definitions
314 */
315 #define FXPS7250_DEVSTAT2_TEMP0_ERR ((uint8_t) 0x02) /* Indicates if temperature is outside of the recommended range. */
316 #define FXPS7250_DEVSTAT2_TEMP0_OK ((uint8_t) 0x00) /* Indicates if temperature is inside of the recommended range. */
317 #define FXPS7250_DEVSTAT2_U_W_ACTIVE ((uint8_t) 0x10) /* Indicates if a user initiated OTP write is in progress. */
318 #define FXPS7250_DEVSTAT2_U_W_INACTIVE ((uint8_t) 0x00) /* Indicates if a user initiated OTP write is in progress. */
319 #define FXPS7250_DEVSTAT2_U_RW_ERR ((uint8_t) 0x20) /* Indicates if there is an error present in any user writable */
320  /* registers. */
321 #define FXPS7250_DEVSTAT2_NO_U_RW_ERR ((uint8_t) 0x00) /* Indicates if there are no errors present in any user writable */
322  /* registers. */
323 #define FXPS7250_DEVSTAT2_U_OTP_ERR ((uint8_t) 0x40) /* Indicates if a fault is detected in the user OTP array. */
324 #define FXPS7250_DEVSTAT2_NO_U_OTP_ERR ((uint8_t) 0x00) /* Indicates if no faults are detected in the user OTP array. */
325 #define FXPS7250_DEVSTAT2_F_OTP_ERR ((uint8_t) 0x80) /* Indicates if a fault is detected in the factory OTP array. */
326 #define FXPS7250_DEVSTAT2_NO_F_OTP_ERR ((uint8_t) 0x00) /* Indicates if no faults are detected in the factory OTP array. */
327 
328 /*--------------------------------
329 ** Register: DEVSTAT3
330 ** Enum: FXPS7250_DEVSTAT3
331 ** --
332 ** Offset : 0x04 - Device Status Register.
333 ** ------------------------------*/
334 typedef union {
335  struct {
336  uint8_t _reserved_ : 6;
337  uint8_t osctrain_err : 1;
338  uint8_t miso_err : 1;
339 
340  } b;
341  uint8_t w;
342 } FXPS7250_DEVSTAT3_t;
343 
344 
345 /*
346 ** DEVSTAT - Bit field mask definitions
347 */
348 
349 #define FXPS7250_DEVSTAT3_OSCTRAIN_ERR_MASK ((uint8_t) 0x40)
350 #define FXPS7250_DEVSTAT3_OSCTRAIN_ERR_SHIFT ((uint8_t) 6)
351 
352 #define FXPS7250_DEVSTAT3_MISO_ERR_MASK ((uint8_t) 0x80)
353 #define FXPS7250_DEVSTAT3_MISO_ERR_SHIFT ((uint8_t) 7)
354 
355 
356 /*
357 ** DEVSTAT - Bit field value definitions
358 */
359 
360 #define FXPS7250_DEVSTAT3_OSCTRAIN_ERR ((uint8_t) 0x40) /* Indicates if an error is detected in the oscillator settings */
361  /* or communication timing. */
362 #define FXPS7250_DEVSTAT3_NO_OSCTRAIN_ERR ((uint8_t) 0x00) /* Indicates if no error is detected in the oscillator settings */
363  /* or communication timing. */
364 #define FXPS7250_DEVSTAT3_MISO_ERR ((uint8_t) 0x80) /* Indicates if a data mismatch has occurred in the MISO data set. */
365 #define FXPS7250_DEVSTAT3_NO_MISO_ERR ((uint8_t) 0x00) /* Indicates if no data mismatch has occurred in the MISO data set. */
366 
367 /*--------------------------------
368 ** Register: TEMP
369 ** Enum: FXPS7250_TEMP
370 ** --
371 ** Offset : 0x0E - Temperature Data Registers.
372 ** ------------------------------*/
373 typedef uint8_t FXPS7250_TEMP_t;
374 
375 
376 
377 /*--------------------------------
378 ** Register: DEVLOCK_WR
379 ** Enum: FXPS7250_DEVLOCK_WR
380 ** --
381 ** Offset : 0x10 - Lock Register Writes Register.
382 ** ------------------------------*/
383 typedef union {
384  struct {
385  uint8_t reset : 2;
386  uint8_t _reserved1_ : 1;
387  uint8_t sup_err_dis : 1;
388  uint8_t _reserved2_ : 3;
389  uint8_t endinit : 1;
390 
391  } b;
392  uint8_t w;
393 } FXPS7250_DEVLOCK_WR_t;
394 
395 
396 /*
397 ** DEVLOCK_WR - Bit field mask definitions
398 */
399 #define FXPS7250_DEVLOCK_WR_RESET_MASK ((uint8_t) 0x01)
400 #define FXPS7250_DEVLOCK_WR_RESET_SHIFT ((uint8_t) 0)
401 
402 #define FXPS7250_DEVLOCK_WR_SUP_ERR_MASK ((uint8_t) 0x08)
403 #define FXPS7250_DEVLOCK_WR_SUP_ERR_SHIFT ((uint8_t) 3)
404 
405 #define FXPS7250_DEVLOCK_WR_ENDINIT_MASK ((uint8_t) 0x80)
406 #define FXPS7250_DEVLOCK_WR_ENDINIT_SHIFT ((uint8_t) 7)
407 
408 
409 /*
410 ** DEVLOCK_WR - Bit field value definitions
411 */
412 #define FXPS7250_DEVLOCK_WR_RESET00 ((uint8_t) 0x00) /* First element in the reset sequence. */
413 #define FXPS7250_DEVLOCK_WR_RESET01 ((uint8_t) 0x01) /* Final element in the reset sequence. */
414 #define FXPS7250_DEVLOCK_WR_RESET10 ((uint8_t) 0x02) /* No Effect. */
415 #define FXPS7250_DEVLOCK_WR_RESET11 ((uint8_t) 0x03) /* Second element in the reset sequence. */
416 #define FXPS7250_DEVLOCK_WR_SUP_BLOCKED ((uint8_t) 0x08) /* Indicates if supply error reporting is blocked by the user. */
417 #define FXPS7250_DEVLOCK_WR_SUP_ALLOWED ((uint8_t) 0x00) /* Indicates if supply error reporting is allowed by the user. */
418 #define FXPS7250_DEVLOCK_WR_ENDINIT_FINISHED ((uint8_t) 0x80) /* Indicates if the device has finished initializing. */
419 #define FXPS7250_DEVLOCK_WR_ENDINIT_RUNNING ((uint8_t) 0x00) /* Indicates if the device is still initializing. */
420 
421 /*--------------------------------
422 ** Register: UF_REGION_W
423 ** Enum: FXPS7250_UF_REGION_W
424 ** --
425 ** Offset : 0x14 - Used to load OTP registers for reading.
426 ** ------------------------------*/
427 typedef union {
428  struct {
429  uint8_t empty : 4;
430  uint8_t region_load : 4;
431  } b;
432  uint8_t w;
433 } FXPS7250_UF_REGION_W_t;
434 
435 
436 /*
437 ** UF_REGION_W - Bit field mask definitions
438 */
439 #define FXPS7250_UF_REGION_W_REGION_LOAD_MASK ((uint8_t) 0xA0)
440 #define FXPS7250_UF_REGION_W_REGION_LOAD_SHIFT ((uint8_t) 4)
441 
442 /*
443 ** UF_REGION_W - Bit field value definitions
444 */
445 #define FXPS7250_UF_REGION_W_REGION_LOAD_A0_AF ((uint8_t) 0xA0) /* Loads addresses A0 through AF */
446 #define FXPS7250_UF_REGION_W_REGION_LOAD_B0_BF ((uint8_t) 0xB0) /* Loads addresses B0 through BF */
447 #define FXPS7250_UF_REGION_W_REGION_LOAD_C0_CF ((uint8_t) 0xC0) /* Loads addresses C0 through CF */
448 #define FXPS7250_UF_REGION_W_REGION_LOAD_D0_DF ((uint8_t) 0xD0) /* Loads addresses D0 through DF */
449 #define FXPS7250_UF_REGION_W_REGION_LOAD_E0_EF ((uint8_t) 0xE0) /* Loads addresses E0 through EF */
450 #define FXPS7250_UF_REGION_W_REGION_LOAD_F0_FF ((uint8_t) 0xF0) /* Loads addresses F0 through FF */
451 
452 
453 /*--------------------------------
454 ** Register: UF_REGION_R
455 ** Enum: FXPS7250_UF_REGION_R
456 ** --
457 ** Offset : 0x15 - Used to read OTP registers. Should be loaded by UF_REGION_W first.
458 ** ------------------------------*/
459 typedef union {
460  struct {
461  uint8_t empty : 4;
462  uint8_t region_active : 4;
463  } b;
464  uint8_t w;
465 } FXPS7250_UF_REGION_R_t;
466 
467 
468 /*
469 ** UF_REGION_R - Bit field mask definitions
470 */
471 #define FXPS7250_UF_REGION_R_REGION_ACTIVE_MASK ((uint8_t) 0xA0)
472 #define FXPS7250_UF_REGION_R_REGION_ACTIVE_SHIFT ((uint8_t) 4)
473 
474 
475 /*
476 ** UF_R_REGION_R - Bit field value definitions
477 */
478 #define FXPS7250_UF_REGION_W_REGION_ACTIVE_00 ((uint8_t) 0x00) /* Load of addresses is in progress. */
479 #define FXPS7250_UF_REGION_W_REGION_ACTIVE_A0_AF ((uint8_t) 0xA0) /* Reads addresses A0 through AF. Must be loaded first. */
480 #define FXPS7250_UF_REGION_W_REGION_ACTIVE_B0_BF ((uint8_t) 0xB0) /* Reads addresses B0 through BF. Must be loaded first. */
481 #define FXPS7250_UF_REGION_W_REGION_ACTIVE_C0_CF ((uint8_t) 0xC0) /* Reads addresses C0 through CF. Must be loaded first. */
482 #define FXPS7250_UF_REGION_W_REGION_ACTIVE_D0_DF ((uint8_t) 0xD0) /* Reads addresses D0 through DF. Must be loaded first. */
483 #define FXPS7250_UF_REGION_W_REGION_ACTIVE_E0_EF ((uint8_t) 0xE0) /* Reads addresses E0 through EF. Must be loaded first. */
484 #define FXPS7250_UF_REGION_W_REGION_ACTIVE_F0_FF ((uint8_t) 0xF0) /* Reads addresses F0 through FF. Must be loaded first. */
485 
486 
487 /*--------------------------------
488 ** Register: COMMTYPE
489 ** Enum: FXPS7250_COMTYPE
490 ** --
491 ** Offset : 0x16 - 3 bit register that determines the communication protocol.
492 ** ------------------------------*/
493 typedef union {
494  struct {
495  uint8_t commtype : 3;
496  uint8_t _reserved_ : 5;
497  } b;
498  uint8_t w;
499 } FXPS7250_COMMTYPE_t;
500 
501 
502 /*
503 ** COMMTYPE - Bit field mask definitions
504 */
505 #define FXPS7250_COMMTYPE_COMMTYPE_MASK ((uint8_t) 0x00)
506 #define FXPS7250_COMMTYPE_COMMTYPE_SHIFT ((uint8_t) 0)
507 
508 
509 /*
510 ** COMMTYPE - Bit field value definitions
511 */
512 #define FXPS7250_COMMTYPE_32BIT_SPI_NO_SELFTEST_DEBUG0 ((uint8_t) 0x00) /* 32-bit SPI communication protocol with no internal test, in debug mode */
513 #define FXPS7250_COMMTYPE_32BIT_SPI_SELFTEST ((uint8_t) 0x01) /* 32-bit SPI communication protocol with internal test on startup */
514 #define FXPS7250_COMMTYPE_32BIT_SPI_NO_SELFTEST_DEBUG1 ((uint8_t) 0x02) /* 32-bit SPI communication protocol with no internal test, in debug mode */
515 #define FXPS7250_COMMTYPE_32BIT_SPI_NO_SELFTEST_DEBUG2 ((uint8_t) 0x04) /* 32-bit SPI communication protocol with no internal test, in debug mode */
516 #define FXPS7250_COMMTYPE_I2C_PIN3_INT0 ((uint8_t) 0x06) /* I2C communication protocol, with PIN 3 working as an interrupt */
517 #define FXPS7250_COMMTYPE_I2C_PIN3_INT1 ((uint8_t) 0x07) /* I2C communication protocol, with PIN 3 working as an interrupt */
518 
519 /*--------------------------------
520 ** Register: SOURCEID_0
521 ** Enum: FXPS7250_SOURCEID_0
522 ** --
523 ** Offset : 0x1A - Contains Source ID information used in SPI mode.
524 ** ------------------------------*/
525 typedef union {
526  struct {
527  uint8_t sourceid_0 : 4;
528  uint8_t _reserved_ : 3;
529  uint8_t sid0_en : 1;
530  } b;
531  uint8_t w;
532 } FXPS7250_SOURCEID_0_t;
533 
534 
535 /*
536 ** SOURCEID_0 - Bit field mask definitions
537 */
538 #define FXPS7250_SOURCEID_0_SOURCEID_0_MASK ((uint8_t) 0x01)
539 #define FXPS7250_SOURCEID_0_SOURCEID_0_SHIFT ((uint8_t) 0)
540 
541 #define FXPS7250_SOURCEID_0_SID0_EN_MASK ((uint8_t) 0x80)
542 #define FXPS7250_SOURCEID_0_SID0_EN_SHIFT ((uint8_t) 7)
543 
544 
545 /*
546 ** SOURCEID_0 - Bit field value definitions
547 */
548 #define FXPS7250_SOURCEID_0_SOURCEID_0 ((uint8_t) 0x01) /* The stream of data to be sent if sid0_en is true */
549 #define FXPS7250_SOURCEID_0_SID0_EN ((uint8_t) 0x80) /* Enables reading of data or an error response for those source-id bits */
550 
551 /*--------------------------------
552 ** Register: SOURCEID_1
553 ** Enum: FXPS7250_SOURCEID_1
554 ** --
555 ** Offset : 0x1B - Contains Source ID information used in SPI mode.
556 ** ------------------------------*/
557 typedef union {
558  struct {
559  uint8_t sourceid_1 : 4;
560  uint8_t _reserved_ : 3;
561  uint8_t sid1_en : 1;
562  } b;
563  uint8_t w;
564 } FXPS7250_SOURCEID_1_t;
565 
566 
567 /*
568 ** SOURCEID_1 - Bit field mask definitions
569 */
570 #define FXPS7250_SOURCEID_1_SOURCEID_1_MASK ((uint8_t) 0x01)
571 #define FXPS7250_SOURCEID_1_SOURCEID_1_SHIFT ((uint8_t) 0)
572 
573 #define FXPS7250_SOURCEID_1_SID1_EN_MASK ((uint8_t) 0x80)
574 #define FXPS7250_SOURCEID_1_SID1_EN_SHIFT ((uint8_t) 7)
575 
576 
577 /*
578 ** SOURCEID_1 - Bit field value definitions
579 */
580 #define FXPS7250_SOURCEID_1_SOURCEID_10 ((uint8_t) 0x01) /* Stream of data that is sent if sid1_en is true */
581 #define FXPS7250_SOURCEID_1_SID1_EN ((uint8_t) 0x80) /* Enables reading of data or an error response for those source-id bits */
582 
583 
584 /*--------------------------------
585 ** Register: TIMING_CFG
586 ** Enum: FXPS7250_TIMING_CFG
587 ** --
588 ** Offset : 0x22 - Contains user specified configurations for protocol timing.
589 ** ------------------------------*/
590 typedef union {
591  struct {
592  uint8_t ck_cal_en : 1;
593  uint8_t _reserved1_ : 2;
594  uint8_t ck_cal_rst : 1;
595  uint8_t osctrain_sel : 1;
596  uint8_t _reserved2_ : 3;
597  } b;
598  uint8_t w;
599 } FXPS7250_TIMING_CFG_t;
600 
601 
602 /*
603 ** TIMING_CFG - Bit field mask definitions
604 */
605 #define FXPS7250_TIMING_CFG_CK_CAL_EN_MASK ((uint8_t) 0x01)
606 #define FXPS7250_TIMING_CFG_CK_CAL_EN_SHIFT ((uint8_t) 0)
607 
608 #define FXPS7250_TIMING_CFG_CK_CAL_RST_MASK ((uint8_t) 0x08)
609 #define FXPS7250_TIMING_CFG_CK_CAL_RST_SHIFT ((uint8_t) 3)
610 
611 #define FXPS7250_TIMING_CFG_OSCTRAIN_SEL_MASK ((uint8_t) 0x10)
612 #define FXPS7250_TIMING_CFG_OSCTRAIN_SEL_SHIFT ((uint8_t) 4)
613 
614 /*
615 ** TIMING_CFG - Bit field value definitions
616 */
617 #define FXPS7250_TIMING_CFG_CK_CAL_EN ((uint8_t) 0x01) /* Enables clock oscillator training over SPI or I2C */
618 #define FXPS7250_TIMING_CFG_CK_CAL_EN_DIS ((uint8_t) 0x00) /* Clock oscillator training is disabled */
619 #define FXPS7250_TIMING_CFG_CK_CAL_RST ((uint8_t) 0x08) /* Resets the oscillator training to default */
620 #define FXPS7250_TIMING_CFG_CK_CAL_KEEP ((uint8_t) 0x00) /* Training value is maintained at last trained value */
621 #define FXPS7250_TIMING_CFG_OSCTRAIN_SEL ((uint8_t) 0x10) /* Sets the protocol to SPI if FXPS7250_COMMTYPE_COMMTYPE=0x00 or */
622  /* FXPS7250_COMMTYPE_COMMTYPE=0x01. Otherwise has no effect. */
623 #define FXPS7250_TIMING_CFG_OSCTRAIN_DISABLE ((uint8_t) 0x00) /* Disables oscillator training. */
624 
625 
626 /*--------------------------------
627 ** Register: SPI_CFG
628 ** Enum: FXPS7250_SPI_CFG
629 ** --
630 ** Offset : 0x3D - SPI Configuration Control Register.
631 ** ------------------------------*/
632 typedef union {
633  struct {
634  uint8_t spicrcseed : 4;
635  uint8_t spi_crc_len : 2;
636  uint8_t datasize : 1;
637  uint8_t _reserved_ : 1;
638 
639 
640  } b;
641  uint8_t w;
642 } FXPS7250_SPI_CFG_t;
643 
644 
645 /*
646 ** SPI_CFG - Bit field mask definitions
647 */
648 #define FXPS7250_SPI_CFG_SPICRCSEED_MASK ((uint8_t) 0x01)
649 #define FXPS7250_SPI_CFG_SPICRCSEED_SHIFT ((uint8_t) 0)
650 
651 #define FXPS7250_SPI_CFG_SPI_CRC_LEN_MASK ((uint8_t) 0x10)
652 #define FXPS7250_SPI_CFG_SPI_CRC_LEN_SHIFT ((uint8_t) 4)
653 
654 #define FXPS7250_SPI_CFG_DATASIZE_MASK ((uint8_t) 0x40)
655 #define FXPS7250_SPI_CFG_DATASIZE_SHIFT ((uint8_t) 6)
656 
657 
658 /*
659 ** SPI_CFG - Bit field value definitions
660 */
661 #define FXPS7250_SPI_CFG_SPICRCSEED ((uint8_t) 0x01) /* CRCSeed is non-zero. For use with CRC_LEN. */
662 #define FXPS7250_SPI_CFG_SPICRCSEED_ZERO ((uint8_t) 0x00) /* CRCSeed is zero. For use with CRC_LEN. */
663 #define FXPS7250_SPI_CFG_SPI_CRC_LEN_00 ((uint8_t) 0x00) /* Sets the length of the CRC Seed to 8, 4, or 3 bits */
664  /* based on whether the CRC Seed is 0 or non-zero. */
665 #define FXPS7250_SPI_CFG_SPI_CRC_LEN_01 ((uint8_t) 0x10) /* Sets the length of the CRC Seed to 8, 4, or 3 bits */
666  /* based on whether the CRC Seed is 0 or non-zero. */
667 #define FXPS7250_SPI_CFG_SPI_CRC_LEN_10 ((uint8_t) 0x20) /* Sets the length of the CRC Seed to 8, 4, or 3 bits */
668  /* based on whether the CRC Seed is 0 or non-zero. */
669 #define FXPS7250_SPI_CFG_SPI_CRC_LEN_11 ((uint8_t) 0x30) /* Sets the length of the CRC Seed to 8, 4, or 3 bits */
670  /* based on whether the CRC Seed is 0 or non-zero. */
671 #define FXPS7250_SPI_CFG_DATASIZE_16 ((uint8_t) 0x40) /* Sets SPI datafield size to 16 bits. */
672 #define FXPS7250_SPI_CFG_DATASIZE_12 ((uint8_t) 0x00) /* Sets SPI datafield size to 12 bits. */
673 
674 
675 /*--------------------------------
676 ** Register: WHO_AM_I
677 ** Enum: FXPS7250_WHO_AM_I
678 ** --
679 ** Offset : 0x3E - Device Identification Register.
680 ** ------------------------------*/
681 //typedef union {
682 // struct {
683 // uint8_t WHO_AM_I : 8; /* The device identification register. */
684 // } b;
685 // uint8_t w;
686 //} FXPS7250_WHO_AM_I_t;
687 typedef uint8_t FXPS7250_WHO_AM_I_t;
688 
689 
690 /*
691 ** WHO_AM_I - Bit field mask definitions
692 */
693 #define FXPS7250_WHO_AM_I_MASK ((uint8_t) 0x01)
694 #define FXPS7250_WHO_AM_I_SHIFT ((uint8_t) 0)
695 
696 
697 /*
698 ** WHO_AM_I - Bit field value definitions
699 */
700 #define FXPS7250_WHO_AM_I_1 ((uint8_t) 0x01) /* Non-zero value in the register returns the value in the register. */
701 #define FXPS7250_WHO_AM_I_DEFAULT ((uint8_t) 0x00) /* A zero value WHO_AM_I register returns the default value: C4h. */
702 
703 
704 /*--------------------------------
705 ** Register: I2C_ADDRESS
706 ** Enum: FXPS7250_I2C_ADDRESS
707 ** --
708 ** Offset : 0x3F - This register contains the I2C identifier.
709 ** ------------------------------*/
710 typedef uint8_t FXPS7250_I2C_ADDRESS_t;
711 
712 
713 /*--------------------------------
714 ** Register: DSP_CFG_U1
715 ** Enum: FXPS7250_DSP_CFG_U1
716 ** --
717 ** Offset : 0x40 - User Configuration #1 Register.
718 ** ------------------------------*/
719 typedef union {
720  struct {
721  uint8_t user_range : 2; /* User Range Selection Bits. */
722  uint8_t _reserved_ : 2; /* Reserved. */
723  uint8_t lpf : 4; /* Low Pass Filter Selection Bits. */
724  } b;
725  uint8_t w;
726 } FXPS7250_DSP_CFG_U1_t;
727 
728 
729 /*
730 ** DSP_CFG_U1 - Bit field mask definitions
731 */
732 #define FXPS7250_DSP_CFG_U1_USER_RANGE_MASK ((uint8_t) 0x00)
733 #define FXPS7250_DSP_CFG_U1_USER_RANGE_SHIFT ((uint8_t) 0)
734 
735 #define FXPS7250_DSP_CFG_U1_LPF_MASK ((uint8_t) 0x10)
736 #define FXPS7250_DSP_CFG_U1_LPF_SHIFT ((uint8_t) 5)
737 
738 /*
739 ** DSP_CFG_U1 - Bit field value definitions
740 */
741 #define FXPS7250_DSP_CFG_U1_LPF_370HZ_2POLE ((uint8_t) 0x00) /* Default Low Pass Filter at 370hz and 2-pole. */
742 #define FXPS7250_DSP_CFG_U1_LPF_400HZ_3POLE ((uint8_t) 0x10) /* Alternate Low Pass Filter at 400hz and 3-pole. */
743 #define FXPS7250_DSP_CFG_U1_LPF_800HZ_4POLE ((uint8_t) 0x20) /* Alternate Low Pass Filter at 800hz and 4-pole. */
744 #define FXPS7250_DSP_CFG_U1_LPF_1000HZ_4POLE ((uint8_t) 0x40) /* Alternate Low Pass Filter at 1000hz and 4-pole. */
745 
746 
747 /*--------------------------------
748 ** Register: DSP_CFG_U4
749 ** Enum: FXPS7250_DSP_CFG_U4
750 ** --
751 ** Offset : 0x43 - User Configuration #4 Register.
752 ** ------------------------------*/
753 typedef union {
754  struct {
755  uint8_t _reserved0_ : 2; /* Reserved. */
756  uint8_t int_out : 1; /* Interrupt Pin Configuration. */
757  uint8_t _reserved_ : 5; /* Reserved. */
758  } b;
759  uint8_t w;
760 } FXPS7250_DSP_CFG_U4_t;
761 
762 
763 /*
764 ** DSP_CFG_U4 - Bit field mask definitions
765 */
766 #define FXPS7250_DSP_CFG_U4_INT_OUT_MASK ((uint8_t) 0x04)
767 #define FXPS7250_DSP_CFG_U4_INT_OUT_SHIFT ((uint8_t) 2)
768 
769 /*
770 ** DSP_CFG_U4 - Bit field value definitions
771 */
772 #define FXPS7250_DSP_CFG_U4_INT_OUT_ACTIVE_HIGH_PULL_DOWN ((uint8_t) 0x00) /* Open Drain, Active High with Pull-down Current. */
773 #define FXPS7250_DSP_CFG_U4_INT_OUT_ACTIVE_LOW_PULL_UP ((uint8_t) 0x04) /* Open Drain, Active Low with Pull-up Current. */
774 
775 
776 /*--------------------------------
777 ** Register: DSP_CFG_U5
778 ** Enum: FXPS7250_DSP_CFG_U5
779 ** --
780 ** Offset : 0x44 - User Configuration #5 Register.
781 ** ------------------------------*/
782 typedef union {
783  struct {
784  uint8_t _reserved_ : 4; /* Reserved. */
785  uint8_t st_ctrl : 4; /* Self-test Control Bits. */
786  } b;
787  uint8_t w;
788 } FXPS7250_DSP_CFG_U5_t;
789 
790 
791 /*
792 ** DSP_CFG_U5 - Bit field mask definitions
793 */
794 #define FXPS7250_DSP_CFG_U5_ST_CTRL_MASK ((uint8_t) 0x10)
795 #define FXPS7250_DSP_CFG_U5_ST_CTRL_SHIFT ((uint8_t) 4)
796 
797 /*
798 ** DSP_CFG_U5 - Bit field value definitions
799 */
800 #define FXPS7250_DSP_CFG_U5_STL_CTRL_NORMAL_SIGNAL ((uint8_t) 0x00) /* SNS_DATAx_X Contains: 16-bit Absolute Pressure. */
801 #define FXPS7250_DSP_CFG_U5_STL_CTRL_P_CELL_MODE_VERIFICATION ((uint8_t) 0x10) /* SNS_DATAx_X Contains: 16-bit Absolute Pressure. */
802 #define FXPS7250_DSP_CFG_U5_STL_CTRL_INHIBIT_SNS_DATA_X_WRITE0 ((uint8_t) 0x40) /* SNS_DATAx_X Contains: 0x0000. */
803 #define FXPS7250_DSP_CFG_U5_STL_CTRL_INHIBIT_SNS_DATA_X_WRITE1 ((uint8_t) 0x50) /* SNS_DATAx_X Contains: 0xAAAA. */
804 #define FXPS7250_DSP_CFG_U5_STL_CTRL_INHIBIT_SNS_DATA_X_WRITE2 ((uint8_t) 0x60) /* SNS_DATAx_X Contains: 0x5555. */
805 #define FXPS7250_DSP_CFG_U5_STL_CTRL_INHIBIT_SNS_DATA_X_WRITE3 ((uint8_t) 0x70) /* SNS_DATAx_X Contains: 0xFFFF. */
806 #define FXPS7250_DSP_CFG_U5_STL_CTRL_DIGITAL_SELF_TEST0 ((uint8_t) 0xC0) /* SNS_DATAx_X Contains: Digital Self Test Output. */
807 #define FXPS7250_DSP_CFG_U5_STL_CTRL_DIGITAL_SELF_TEST1 ((uint8_t) 0xD0) /* SNS_DATAx_X Contains: Digital Self Test Output. */
808 #define FXPS7250_DSP_CFG_U5_STL_CTRL_DIGITAL_SELF_TEST2 ((uint8_t) 0xE0) /* SNS_DATAx_X Contains: Digital Self Test Output. */
809 #define FXPS7250_DSP_CFG_U5_STL_CTRL_DIGITAL_SELF_TEST3 ((uint8_t) 0xF0) /* SNS_DATAx_X Contains: Digital Self Test Output. */
810 
811 
812 /*--------------------------------
813 ** Register: INT_CFG
814 ** Enum: FXPS7250_INT_CFG
815 ** --
816 ** Offset : 0x45 - Interrupt Configuration Register.
817 ** ------------------------------*/
818 typedef union {
819  struct {
820  uint8_t _reserved0_ : 3; /* Reserved. */
821  uint8_t int_polarity : 1; /* Interrupt Polarity Bit. */
822  uint8_t int_ps : 2; /* Programmable Pulse Stretch Time for Interrupt Output. */
823  uint8_t _reserved1_ : 1; /* Reserved. */
824  } b;
825  uint8_t w;
826 } FXPS7250_INT_CFG_t;
827 
828 
829 /*
830 ** INT_CFG - Bit field mask definitions
831 */
832 #define FXPS7250_INT_CFG_INT_POLARITY_MASK ((uint8_t) 0x08)
833 #define FXPS7250_INT_CFG_INT_POLARITY_SHIFT ((uint8_t) 3)
834 
835 #define FXPS7250_INT_CFG_INT_PS_MASK ((uint8_t) 0x10)
836 #define FXPS7250_INT_CFG_INT_PS_SHIFT ((uint8_t) 4)
837 
838 /*
839 ** INT_CFG - Bit field value definitions
840 */
841 #define FXPS7250_INT_CFG_INT_POLARITY_OUTSIDE_RANGE ((uint8_t) 0x00) /* Interrupt activates if values are outside of the range. */
842 #define FXPS7250_INT_CFG_INT_POLARITY_INSIDE_RANGE ((uint8_t) 0x08) /* Interrupt activates if values are inside of the range. */
843 #define FXPS7250_INT_CFG_INT_PS_00 ((uint8_t) 0x00) /* Pulse Stretch of 0ms. */
844 #define FXPS7250_INT_CFG_INT_PS_01 ((uint8_t) 0x10) /* Pulse Stretch of 16,000ms - 16,512ms. */
845 #define FXPS7250_INT_CFG_INT_PS_10 ((uint8_t) 0x20) /* Pulse Stretch of 64,000ms - 60,512ms. */
846 #define FXPS7250_INT_CFG_INT_PS_11 ((uint8_t) 0x30) /* Pulse Stretch of 256,000ms - 256,512ms. */
847 
848 
849 /*--------------------------------
850 ** Register: PIN_INT_HI_L
851 ** Enum: FXPS7250_PIN_INT_HI_L
852 ** --
853 ** Offset : 0x46 - 8 LSBs of 16-bit High Interrupt Window Comparator Threshold Registers.
854 ** ------------------------------*/
855 typedef uint8_t FXPS7250_PIN_INT_HI_L_t;
856 
857 
858 /*--------------------------------
859 ** Register: PIN_INT_HI_M
860 ** Enum: FXPS7250_PIN_INT_HI_M
861 ** --
862 ** Offset : 0x47 - 8 MSBs of 16-bit High Interrupt Window Comparator Threshold Registers.
863 ** ------------------------------*/
864 typedef uint8_t FXPS7250_PIN_INT_HI_M_t;
865 
866 
867 /*--------------------------------
868 ** Register: PIN_INT_LO_L
869 ** Enum: FXPS7250_PIN_INT_LO_L
870 ** --
871 ** Offset : 0x48 - 8 LSBs of 16-bit Low Interrupt Window Comparator Threshold Registers.
872 ** ------------------------------*/
873 typedef uint8_t FXPS7250_PIN_INT_LO_L_t;
874 
875 
876 /*--------------------------------
877 ** Register: PIN_INT_LO_H
878 ** Enum: FXPS7250_PIN_INT_LO_H
879 ** --
880 ** Offset : 0x49 - 8 MSBs of 16-bit Low Interrupt Window Comparator Threshold Registers.
881 ** ------------------------------*/
882 typedef uint8_t FXPS7250_PIN_INT_LO_H_t;
883 
884 
885 /*--------------------------------
886 ** Register: P_CAL_ZERO_L
887 ** Enum: FXPS7250_P_CAL_ZERO_L
888 ** --
889 ** Offset : 0x4C - 8 LSBs of 16-bit Pressure Calibration Registers.
890 ** ------------------------------*/
891 typedef uint8_t FXPS7250_P_CAL_ZERO_L_t;
892 
893 
894 /*--------------------------------
895 ** Register: P_CAL_ZERO_H
896 ** Enum: FXPS7250_P_CAL_ZERO_H
897 ** --
898 ** Offset : 0x4D - 8 MSBs of 16-bit Pressure Calibration Registers.
899 ** ------------------------------*/
900 typedef uint8_t FXPS7250_P_TGT2_LSB_t;
901 
902 
903 /*--------------------------------
904 ** Register: DSP_STAT
905 ** Enum: FXPS7250_DSP_STAT
906 ** --
907 ** Offset : 0x60 - DSP Specific Status Register.
908 ** ------------------------------*/
909 typedef union {
910  struct {
911  uint8_t st_error : 1; /* Self-Test Error Flag. */
912  uint8_t cm_error : 1; /* Common Mode Error Status bit. */
913  uint8_t st_active : 1; /* Self-Test Active Bit. */
914  uint8_t st_incmplt : 1; /* Self-Test Incomplete Bit. Set after device reset and cleared when an ST is run. */
915  uint8_t _reserved0_ : 1; /* Reserved. */
916  uint8_t pabs_low : 1; /* Status Bit for low overage limit of absolute pressure. */
917  uint8_t pabs_high : 1; /* Status Bit for high overage limit of absolute pressure. */
918  uint8_t _reserved1_ : 1; /* Reserved. */
919  } b;
920  uint8_t w;
921 } FXPS7250_DSP_STAT_t;
922 
923 
924 /*
925 ** DSP_STAT - Bit field mask definitions
926 */
927 #define FXPS7250_DSP_STAT_ST_ERROR_MASK ((uint8_t) 0x01)
928 #define FXPS7250_DSP_STAT_ST_ERROR_SHIFT ((uint8_t) 0)
929 
930 #define FXPS7250_DSP_STAT_CM_ERROR_MASK ((uint8_t) 0x02)
931 #define FXPS7250_DSP_STAT_CM_ERROR_SHIFT ((uint8_t) 1)
932 
933 #define FXPS7250_DSP_STAT_ST_ACTIVE_MASK ((uint8_t) 0x04)
934 #define FXPS7250_DSP_STAT_ST_ACTIVE_SHIFT ((uint8_t) 2)
935 
936 #define FXPS7250_DSP_STAT_ST_INCMPLT_MASK ((uint8_t) 0x08)
937 #define FXPS7250_DSP_STAT_ST_INCMPLT_SHIFT ((uint8_t) 3)
938 
939 #define FXPS7250_DSP_STAT_PABS_LOW_MASK ((uint8_t) 0x20)
940 #define FXPS7250_DSP_STAT_PABS_LOW_SHIFT ((uint8_t) 5)
941 
942 #define FXPS7250_DSP_STAT_PABS_HIGH_MASK ((uint8_t) 0x40)
943 #define FXPS7250_DSP_STAT_PABS_HIGH_SHIFT ((uint8_t) 6)
944 
945 /*
946 ** DSP_STAT - Bit field value definitions
947 */
948 #define FXPS7250_DSP_STAT_ST_ERROR_CLR ((uint8_t) 0x00) /* No Self-Test Error has been flagged. */
949 #define FXPS7250_DSP_STAT_ST_ERROR_FLAGGED ((uint8_t) 0x01) /* A Self-Test Error has been flagged. */
950 #define FXPS7250_DSP_STAT_CM_ERROR_CLR ((uint8_t) 0x00) /* No Common Mode Error has been flagged. */
951 #define FXPS7250_DSP_STAT_CM_ERROR_FLAGGED ((uint8_t) 0x02) /* A Common Mode Error has been flagged. */
952 #define FXPS7250_DSP_STAT_ST_ACTIVE_INACTIVE ((uint8_t) 0x00) /* No Self-Test Mode is currently active. */
953 #define FXPS7250_DSP_STAT_ST_ACTIVE_ACTIVE ((uint8_t) 0x04) /* A Self-Test Mode is currently active. */
954 #define FXPS7250_DSP_STAT_ST_INCMPLT_FALSE ((uint8_t) 0x00) /* An analog or digital Self-Test has been run since the last reset. */
955 #define FXPS7250_DSP_STAT_ST_INCMPLT_TRUE ((uint8_t) 0x08) /* An analog or digital Self-Test has not been run since the last reset. */
956 #define FXPS7250_DSP_STAT_PABS_LOW_IN_RANGE ((uint8_t) 0x00) /* Absolute Pressure is below the out-of-range lower limit */
957 #define FXPS7250_DSP_STAT_PABS_LOW_NOT_IN_RANGE ((uint8_t) 0x20) /* Absolute Pressure is above the out-of-range lower limit */
958 #define FXPS7250_DSP_STAT_PABS_HIGH_IN_RANGE ((uint8_t) 0x00) /* Absolute Pressure is below the out-of-range higher limit */
959 #define FXPS7250_DSP_STAT_PABS_HIGH_NOT_IN_RANGE ((uint8_t) 0x40) /* Absolute Pressure is above the out-of-range higher limit */
960 
961 /*--------------------------------
962 ** Register: DEVSTAT_COPY
963 ** Enum: FXPS7250_DEVSTAT_COPY
964 ** --
965 ** Offset : 0x61 - Device Status Copy Register.
966 ** ------------------------------*/
967 typedef union {
968  struct {
969  uint8_t devinit : 1;
970  uint8_t devres : 1;
971  uint8_t testmode : 1;
972  uint8_t supply_err : 1;
973  uint8_t memtemp_err : 1;
974  uint8_t comm_err : 1;
975  uint8_t _reserved_ : 1;
976  uint8_t dsp_err : 1;
977 
978  } b;
979  uint8_t w;
980 } FXPS7250_DEVSTAT_COPY_t;
981 
982 
983 /*
984 ** DEVSTAT - Bit field mask definitions
985 */
986 #define FXPS7250_DEVSTAT_DEVINIT_MASK ((uint8_t) 0x01)
987 #define FXPS7250_DEVSTAT_DEVINIT_SHIFT ((uint8_t) 0)
988 
989 #define FXPS7250_DEVSTAT_DEVRES_MASK ((uint8_t) 0x02)
990 #define FXPS7250_DEVSTAT_DEVRES_SHIFT ((uint8_t) 1)
991 
992 #define FXPS7250_DEVSTAT_TESTMODE_MASK ((uint8_t) 0x04)
993 #define FXPS7250_DEVSTAT_TESTMODE_SHIFT ((uint8_t) 2)
994 
995 #define FXPS7250_DEVSTAT_SUPPLY_ERR_MASK ((uint8_t) 0x08)
996 #define FXPS7250_DEVSTAT_SUPPLY_ERR_SHIFT ((uint8_t) 3)
997 
998 #define FXPS7250_DEVSTAT_MEMTEMP_ERR_MASK ((uint8_t) 0x10)
999 #define FXPS7250_DEVSTAT_MEMTEMP_ERR_SHIFT ((uint8_t) 4)
1000 
1001 #define FXPS7250_DEVSTAT_COMM_ERR_MASK ((uint8_t) 0x20)
1002 #define FXPS7250_DEVSTAT_COMM_ERR_SHIFT ((uint8_t) 5)
1003 
1004 #define FXPS7250_DEVSTAT_DSP_ERR_MASK ((uint8_t) 0x80)
1005 #define FXPS7250_DEVSTAT_DSP_ERR_SHIFT ((uint8_t) 7)
1006 
1007 
1008 /*
1009 ** DEVSTAT - Bit field value definitions
1010 */
1011 #define FXPS7250_DEVSTAT_DEVINIT_INIT ((uint8_t) 0x01) /* Indicates if the device is initializing. */
1012 #define FXPS7250_DEVSTAT_DEVINIT_NOT_INIT ((uint8_t) 0x00) /* Device is operating normally. */
1013 #define FXPS7250_DEVSTAT_DEVRES_RESET ((uint8_t) 0x02) /* Indicates if the device has reset. */
1014 #define FXPS7250_DEVSTAT_DEVRES_NOT_RESET ((uint8_t) 0x00) /* Device is operating normally. */
1015 #define FXPS7250_DEVSTAT_TESTMODE_ISACTIVE ((uint8_t) 0x04) /* Indicates if the device is in test mode. */
1016 #define FXPS7250_DEVSTAT_TESTMODE_INACTIVE ((uint8_t) 0x00) /* Test mode is not active. */
1017 #define FXPS7250_DEVSTAT_SUPPLY_ERR ((uint8_t) 0x08) /* Indicates if an error is flagged in DEVSTAT1. */
1018 #define FXPS7250_DEVSTAT_NOT_SUPPLY_ERR ((uint8_t) 0x00) /* No error is flagged in DEVSTAT1. */
1019 #define FXPS7250_DEVSTAT_MEMTEMP_ERR ((uint8_t) 0x10) /* Indicates if an error is flagged in DEVSTAT2. */
1020 #define FXPS7250_DEVSTAT_NOT_MEMTEMP_ERR ((uint8_t) 0x00) /* No error is flagged in DEVSTAT2. */
1021 #define FXPS7250_DEVSTAT_COMM_ERR ((uint8_t) 0x20) /* Indicates if an error is flagged in DEVSTAT3. */
1022 #define FXPS7250_DEVSTAT_NOT_COMM_ERR ((uint8_t) 0x00) /* No error is flagged in DEVSTAT3. */
1023 #define FXPS7250_DEVSTAT_DSP_ERR ((uint8_t) 0x80) /* Indicates if an error is flagged in the pressure DSP. */
1024 #define FXPS7250_DEVSTAT_NOT_DSP_ERR ((uint8_t) 0x00) /* No error is flagged in the pressure DSP. */
1025 
1026 /*--------------------------------
1027 ** Register: SNSDATA0_L
1028 ** Enum: FXPS7250_SNSDATA0_L
1029 ** --
1030 ** Offset : 0x62 - 8 LSBs of 16-bit Sensor Data #0 Registers.
1031 ** ------------------------------*/
1032 typedef uint8_t FXPS7250_SNSDATA0_L_t;
1033 
1034 
1035 /*--------------------------------
1036 ** Register: SNSDATA0_H
1037 ** Enum: FXPS7250_SNSDATA0_H
1038 ** --
1039 ** Offset : 0x63 - 8 MSBs of 16-bit Sensor Data #0 Registers.
1040 ** ------------------------------*/
1041 typedef uint8_t FXPS7250_SNSDATA0_H_t;
1042 
1043 /*--------------------------------
1044 ** Register: SNSDATA1_L
1045 ** Enum: FXPS7250_SNSDATA1_L
1046 ** --
1047 ** Offset : 0x64 - 8 LSBs of 16-bit Sensor Data #1 Registers.
1048 ** ------------------------------*/
1049 typedef uint8_t FXPS7250_SNSDATA1_L_t;
1050 
1051 
1052 /*--------------------------------
1053 ** Register: SNSDATA1_H
1054 ** Enum: FXPS7250_SNSDATA1_H
1055 ** --
1056 ** Offset : 0x65 - 8 MSBs of 16-bit Sensor Data #1 Registers.
1057 ** ------------------------------*/
1058 typedef uint8_t FXPS7250_SNSDATA1_H_t;
1059 
1060 /*--------------------------------
1061 ** Register: SNSDATA0_TIME0
1062 ** Enum: FXPS7250_SNSDATA0_TIME0
1063 ** --
1064 ** Offset : 0x66 - First 8 bits of 48-bit Sensor Data Time Stamp Register.
1065 ** ------------------------------*/
1066 typedef uint8_t FXPS7250_SNSDATA_TIME0_t;
1067 
1068 /*--------------------------------
1069 ** Register: SNSDATA0_TIME1
1070 ** Enum: FXPS7250_SNSDATA0_TIME1
1071 ** --
1072 ** Offset : 0x67 - Second 8 bits of 48-bit Sensor Data 0 Time Stamp Register.
1073 ** ------------------------------*/
1074 typedef uint8_t FXPS7250_SNSDATA_TIME1_t;
1075 
1076 /*--------------------------------
1077 ** Register: SNSDATA0_TIME2
1078 ** Enum: FXPS7250_SNSDATA0_TIME2
1079 ** --
1080 ** Offset : 0x68 - Third 8 bits of 48-bit Sensor Data Time Stamp Register.
1081 ** ------------------------------*/
1082 typedef uint8_t FXPS7250_SNSDATA_TIME2_t;
1083 
1084 /*--------------------------------
1085 ** Register: SNSDATA0_TIME3
1086 ** Enum: FXPS7250_SNSDATA0_TIME3
1087 ** --
1088 ** Offset : 0x69 - Fourth 8 bits of 48-bit Sensor Data Time Stamp Register.
1089 ** ------------------------------*/
1090 typedef uint8_t FXPS7250_SNSDATA_TIME3_t;
1091 
1092 /*--------------------------------
1093 ** Register: SNSDATA0_TIME4
1094 ** Enum: FXPS7250_SNSDATA0_TIME4
1095 ** --
1096 ** Offset : 0x6A - Fifth 8 bits of 48-bit Sensor Data Time Stamp Register.
1097 ** ------------------------------*/
1098 typedef uint8_t FXPS7250_SNSDATA_TIME4_t;
1099 
1100 /*--------------------------------
1101 ** Register: SNSDATA0_TIME5
1102 ** Enum: FXPS7250_SNSDATA0_TIME5
1103 ** --
1104 ** Offset : 0x6B - Sixth 8 bits of 48-bit Sensor Data Time Stamp Register.
1105 ** ------------------------------*/
1106 typedef uint8_t FXPS7250_SNSDATA_TIME5_t;
1107 
1108 /*--------------------------------
1109 ** Register: P_MAX_L
1110 ** Enum: FXPS7250_P_MAX_L
1111 ** --
1112 ** Offset : 0x6C - 8 LSBs of 16-bit Maximum Absolute Pressure Value Register.
1113 ** ------------------------------*/
1114 typedef uint8_t FXPS7250_P_MAX_L_t;
1115 
1116 /*--------------------------------
1117 ** Register: P_MAX_H
1118 ** Enum: FXPS7250_P_MAX_H
1119 ** --
1120 ** Offset : 0x6D - 8 MSBs of 16-bit Maximum Absolute Pressure Value Register.
1121 ** ------------------------------*/
1122 typedef uint8_t FXPS7250_P_MAX_H_t;
1123 
1124 /*--------------------------------
1125 ** Register: P_MIN_L
1126 ** Enum: FXPS7250_P_MIN_L
1127 ** --
1128 ** Offset : 0x6E - 8 LSBs of 16-bit Minimum Absolute Pressure Value Register.
1129 ** ------------------------------*/
1130 typedef uint8_t FXPS7250_P_MIN_L_t;
1131 
1132 /*--------------------------------
1133 ** Register: P_MIN_L
1134 ** Enum: FXPS7250_P_MIN_L
1135 ** --
1136 ** Offset : 0x6F - 8 MSBs of 16-bit Minimum Absolute Pressure Value Register.
1137 ** ------------------------------*/
1138 typedef uint8_t FXPS7250_P_MIN_H_t;
1139 
1140 /*--------------------------------
1141 ** Register: FRT0
1142 ** Enum: FXPS7250_FRT0
1143 ** --
1144 ** Offset : 0x78 - First 8 bits of 48-bit Free Running Timer Register.
1145 ** ------------------------------*/
1146 typedef uint8_t FXPS7250_FRT0_t;
1147 
1148 /*--------------------------------
1149 ** Register: FRT1
1150 ** Enum: FXPS7250_FRT1
1151 ** --
1152 ** Offset : 0x79 - Second 8 bits of 48-bit Free Running Timer Register.
1153 ** ------------------------------*/
1154 typedef uint8_t FXPS7250_FRT1_t;
1155 
1156 /*--------------------------------
1157 ** Register: FRT2
1158 ** Enum: FXPS7250_FRT2
1159 ** --
1160 ** Offset : 0x7A - Third 8 bits of 48-bit Free Running Timer Register.
1161 ** ------------------------------*/
1162 typedef uint8_t FXPS7250_FRT2_t;
1163 
1164 /*--------------------------------
1165 ** Register: FRT3
1166 ** Enum: FXPS7250_FRT3
1167 ** --
1168 ** Offset : 0x7B - Fourth 8 bits of 48-bit Free Running Timer Register.
1169 ** ------------------------------*/
1170 typedef uint8_t FXPS7250_FRT3_t;
1171 
1172 /*--------------------------------
1173 ** Register: FRT4
1174 ** Enum: FXPS7250_FRT4
1175 ** --
1176 ** Offset : 0x7C - Fifth 8 bits of 48-bit Free Running Timer Register.
1177 ** ------------------------------*/
1178 typedef uint8_t FXPS7250_FRT4_t;
1179 
1180 /*--------------------------------
1181 ** Register: FRT5
1182 ** Enum: FXPS7250_FRT5
1183 ** --
1184 ** Offset : 0x7D - Sixth 8 bits of 48-bit Free Running Timer Register.
1185 ** ------------------------------*/
1186 typedef uint8_t FXPS7250_FRT5_t;
1187 
1188 /*--------------------------------
1189 ** Register: ICTYPEID
1190 ** Enum: FXPS7250_ICTYPEID
1191 ** --
1192 ** Offset : 0xC0 - Contains IC type ID.
1193 ** ------------------------------*/
1194 typedef uint8_t FXPS7250_ICTYPEID_t;
1195 
1196 /*--------------------------------
1197 ** Register: ICREVID
1198 ** Enum: FXPS7250_ICREVID
1199 ** --
1200 ** Offset : 0xC1 - Contains IC revision ID.
1201 ** ------------------------------*/
1202 typedef uint8_t FXPS7250_ICREVID_t;
1203 
1204 /*--------------------------------
1205 ** Register: ICMFGID
1206 ** Enum: FXPS7250_ICMFGID
1207 ** --
1208 ** Offset : 0xC2 - Identifies NXP as the IC Manufacturer.
1209 ** ------------------------------*/
1210 typedef uint8_t FXPS7250_ICMFGID_t;
1211 
1212 /*--------------------------------
1213 ** Register: PN0
1214 ** Enum: FXPS7250_PN0
1215 ** --
1216 ** Offset : 0xC4 - Contains 8 MSB's out of 16-bits that represent the numeric portion of the device ID.
1217 ** ------------------------------*/
1218 typedef uint8_t FXPS7250_PN0_t;
1219 
1220 /*--------------------------------
1221 ** Register: PN1
1222 ** Enum: FXPS7250_PN1
1223 ** --
1224 ** Offset : 0xC5 - Contains 8 LSB's out of 16-bits that represent the numeric portion of the device ID.
1225 ** ------------------------------*/
1226 typedef uint8_t FXPS7250_PN1_t;
1227 
1228 /*--------------------------------
1229 ** Register: SN0
1230 ** Enum: FXPS7250_SN0
1231 ** --
1232 ** Offset : 0xC6 - Contains the first set of 8 bits out of 40-bits that represent the device serial number.
1233 ** ------------------------------*/
1234 typedef uint8_t FXPS7250_SN0_t;
1235 
1236 /*--------------------------------
1237 ** Register: SN1
1238 ** Enum: FXPS7250_SN1
1239 ** --
1240 ** Offset : 0xC7 - Contains the second set of 8 bits out of 40-bits that represent the device serial number.
1241 ** ------------------------------*/
1242 typedef uint8_t FXPS7250_SN1_t;
1243 
1244 /*--------------------------------
1245 ** Register: SN2
1246 ** Enum: FXPS7250_SN2
1247 ** --
1248 ** Offset : 0xC8 - Contains the third set of 8 bits out of 40-bits that represent the device serial number.
1249 ** ------------------------------*/
1250 typedef uint8_t FXPS7250_SN2_t;
1251 
1252 /*--------------------------------
1253 ** Register: SN3
1254 ** Enum: FXPS7250_SN3
1255 ** --
1256 ** Offset : 0xC9 - Contains the fourth set of 8 bits out of 40-bits that represent the device serial number.
1257 ** ------------------------------*/
1258 typedef uint8_t FXPS7250_SN3_t;
1259 
1260 /*--------------------------------
1261 ** Register: SN4
1262 ** Enum: FXPS7250_SN4
1263 ** --
1264 ** Offset : 0xCA - Contains the fifth set of 8 bits out of 40-bits that represent the device serial number.
1265 ** ------------------------------*/
1266 typedef uint8_t FXPS7250_SN4_t;
1267 
1268 /*--------------------------------
1269 ** Register: ASICWFR#
1270 ** Enum: FXPS7250_ASICWFR
1271 ** --
1272 ** Offset : 0xCB - Contains the device wafer ASIC number.
1273 ** ------------------------------*/
1274 typedef uint8_t FXPS7250_ASICWFR_t;
1275 
1276 /*--------------------------------
1277 ** Register: ASICWFR_X
1278 ** Enum: FXPS7250_ASICWFR_X
1279 ** --
1280 ** Offset : 0xCC - Contains the x coordinates for the device ASIC.
1281 ** ------------------------------*/
1282 typedef uint8_t FXPS7250_ASICWFR_X_t;
1283 
1284 /*--------------------------------
1285 ** Register: ASICWFR_Y
1286 ** Enum: FXPS7250_ASICWFR_Y
1287 ** --
1288 ** Offset : 0xCD - Contains the Y coordinates for the device ASIC.
1289 ** ------------------------------*/
1290 typedef uint8_t FXPS7250_ASICWFR_Y_t;
1291 
1292 /*--------------------------------
1293 ** Register: ASICWLOT_L
1294 ** Enum: FXPS7250_ASICWLOT_L
1295 ** --
1296 ** Offset : 0xD0 - Contains 8 LSB's of the device wafer ASIC lot number.
1297 ** ------------------------------*/
1298 typedef uint8_t FXPS7250_ASICWLOT_L_t;
1299 
1300 /*--------------------------------
1301 ** Register: ASICWLOT_H
1302 ** Enum: FXPS7250_ASICWLOT_H
1303 ** --
1304 ** Offset : 0xD1 - Contains 8 MSB's of the device wafer ASIC lot number.
1305 ** ------------------------------*/
1306 typedef uint8_t FXPS7250_ASICWLOT_H_t;
1307 
1308 /*--------------------------------
1309 ** Register: TRNS1WFR_X
1310 ** Enum: FXPS7250_TRNS1WFR_X
1311 ** --
1312 ** Offset : 0xD2 - Contains the x coordinates for the device wafer transducer.
1313 ** ------------------------------*/
1314 typedef uint8_t FXPS7250_TRNS1WFR_X_t;
1315 
1316 /*--------------------------------
1317 ** Register: TRNS1WFR_Y
1318 ** Enum: FXPS7250_TRNS1WFR_Y
1319 ** --
1320 ** Offset : 0xD3 - Contains the y coordinates for the device wafer transducer.
1321 ** ------------------------------*/
1322 typedef uint8_t FXPS7250_TRNS1WFR_Y_t;
1323 
1324 /*--------------------------------
1325 ** Register: TRNS1LOT_L
1326 ** Enum: FXPS7250_TRNS1LOT_L
1327 ** --
1328 ** Offset : 0xD4 - Contains 8 LSB's of the device transducer lot number.
1329 ** ------------------------------*/
1330 typedef uint8_t FXPS7250_TRNS1LOT_L_t;
1331 
1332 /*--------------------------------
1333 ** Register: TRNS1LOT_H
1334 ** Enum: FXPS7250_TRNS1LOT_H
1335 ** --
1336 ** Offset : 0xD5 - Contains 8 MSB's of the device transducer lot number.
1337 ** ------------------------------*/
1338 typedef uint8_t FXPS7250_TRNS1LOT_H_t;
1339 
1340 #endif /* FXPS7250_H_ */
FXPS7250_DEVSTAT_t::w
uint8_t w
Definition: dbap.h:166
FXPS7250_TRNS1LOT_H_t
uint8_t FXPS7250_TRNS1LOT_H_t
Definition: dbap.h:1338
FXPS7250_DEVSTAT3_t::osctrain_err
uint8_t osctrain_err
Definition: dbap.h:337
FXPS7250_DSP_STAT_t::st_error
uint8_t st_error
Definition: dbap.h:911
FXPS7250_DEVSTAT1_t::_reserved2_
uint8_t _reserved2_
Definition: dbap.h:226
FXPS7250_PIN_INT_LO_L_t
uint8_t FXPS7250_PIN_INT_LO_L_t
Definition: dbap.h:873
FXPS7250_INT_CFG_t::int_ps
uint8_t int_ps
Definition: dbap.h:822
FXPS7250_SPI_CFG_t::_reserved_
uint8_t _reserved_
Definition: dbap.h:637
FXPS7250_DSP_CFG_U4_t::_reserved_
uint8_t _reserved_
Definition: dbap.h:757
FXPS7250_SOURCEID_1_t::_reserved_
uint8_t _reserved_
Definition: dbap.h:560
FXPS7250_SNSDATA0_H_t
uint8_t FXPS7250_SNSDATA0_H_t
Definition: dbap.h:1041
FXPS7250_SN2_t
uint8_t FXPS7250_SN2_t
Definition: dbap.h:1250
FXPS7250_WHO_AM_I_t
uint8_t FXPS7250_WHO_AM_I_t
Definition: dbap.h:687
FXPS7250_SOURCEID_0_t::sid0_en
uint8_t sid0_en
Definition: dbap.h:529
FXPS7250_DEVSTAT_t::_reserved_
uint8_t _reserved_
Definition: dbap.h:163
FXPS7250_DEVSTAT_t::comm_err
uint8_t comm_err
Definition: dbap.h:162
FXPS7250_TRNS1WFR_X_t
uint8_t FXPS7250_TRNS1WFR_X_t
Definition: dbap.h:1314
FXPS7250_FRT2_t
uint8_t FXPS7250_FRT2_t
Definition: dbap.h:1162
FXPS7250_DEVSTAT_COPY_t::_reserved_
uint8_t _reserved_
Definition: dbap.h:975
FXPS7250_DSP_STAT_t::cm_error
uint8_t cm_error
Definition: dbap.h:912
FXPS7250_COUNT_t
uint8_t FXPS7250_COUNT_t
Definition: dbap.h:147
FXPS7250_DEVSTAT1_t::_reserved1_
uint8_t _reserved1_
Definition: dbap.h:224
FXPS7250_I2C_ADDRESS_t
uint8_t FXPS7250_I2C_ADDRESS_t
Definition: dbap.h:710
FXPS7250_DSP_STAT_t::pabs_high
uint8_t pabs_high
Definition: dbap.h:917
FXPS7250_FRT4_t
uint8_t FXPS7250_FRT4_t
Definition: dbap.h:1178
FXPS7250_DEVSTAT_t::supply_err
uint8_t supply_err
Definition: dbap.h:160
FXPS7250_SOURCEID_1_t::sid1_en
uint8_t sid1_en
Definition: dbap.h:561
FXPS7250_P_TGT2_LSB_t
uint8_t FXPS7250_P_TGT2_LSB_t
Definition: dbap.h:900
FXPS7250_DEVLOCK_WR_t::_reserved2_
uint8_t _reserved2_
Definition: dbap.h:388
FXPS7250_ASICWLOT_L_t
uint8_t FXPS7250_ASICWLOT_L_t
Definition: dbap.h:1298
FXPS7250_SNSDATA_TIME5_t
uint8_t FXPS7250_SNSDATA_TIME5_t
Definition: dbap.h:1106
FXPS7250_TEMP_t
uint8_t FXPS7250_TEMP_t
Definition: dbap.h:373
FXPS7250_TRNS1LOT_L_t
uint8_t FXPS7250_TRNS1LOT_L_t
Definition: dbap.h:1330
FXPS7250_DSP_STAT_t::st_active
uint8_t st_active
Definition: dbap.h:913
FXPS7250_TIMING_CFG_t::osctrain_sel
uint8_t osctrain_sel
Definition: dbap.h:595
FXPS7250_SNSDATA_TIME4_t
uint8_t FXPS7250_SNSDATA_TIME4_t
Definition: dbap.h:1098
FXPS7250_SOURCEID_0_t::_reserved_
uint8_t _reserved_
Definition: dbap.h:528
FXPS7250_DEVSTAT3_t::miso_err
uint8_t miso_err
Definition: dbap.h:338
FXPS7250_FRT0_t
uint8_t FXPS7250_FRT0_t
Definition: dbap.h:1146
FXPS7250_DSP_CFG_U1_t::_reserved_
uint8_t _reserved_
Definition: dbap.h:722
FXPS7250_ASICWFR_X_t
uint8_t FXPS7250_ASICWFR_X_t
Definition: dbap.h:1282
FXPS7250_UF_REGION_W_t::region_load
uint8_t region_load
Definition: dbap.h:430
FXPS7250_FRT3_t
uint8_t FXPS7250_FRT3_t
Definition: dbap.h:1170
FXPS7250_FRT5_t
uint8_t FXPS7250_FRT5_t
Definition: dbap.h:1186
FXPS7250_INT_CFG_t::_reserved1_
uint8_t _reserved1_
Definition: dbap.h:823
FXPS7250_COMMTYPE_t::commtype
uint8_t commtype
Definition: dbap.h:495
FXPS7250_DEVSTAT3_t::_reserved_
uint8_t _reserved_
Definition: dbap.h:336
FXPS7250_DEVSTAT1_t::vccuv_err
uint8_t vccuv_err
Definition: dbap.h:227
FXPS7250_DEVSTAT_t::memtemp_err
uint8_t memtemp_err
Definition: dbap.h:161
FXPS7250_SN0_t
uint8_t FXPS7250_SN0_t
Definition: dbap.h:1234
FXPS7250_DEVLOCK_WR_t::_reserved1_
uint8_t _reserved1_
Definition: dbap.h:386
FXPS7250_DSP_CFG_U4_t::_reserved0_
uint8_t _reserved0_
Definition: dbap.h:755
FXPS7250_ASICWLOT_H_t
uint8_t FXPS7250_ASICWLOT_H_t
Definition: dbap.h:1306
FXPS7250_P_MAX_L_t
uint8_t FXPS7250_P_MAX_L_t
Definition: dbap.h:1114
FXPS7250_DEVSTAT2_t::u_w_active
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