MCUXpresso SDK Changelog
ANACTRL
[2.4.0]
Improvements
Added some interrupt flags for devices containing BOD1 and BOD2 interrupt controls.
Added a control macro to enable/disable the 32MHz Crystal oscillator code in current driver.
Added a feature macro for bit field ENA_96MHZCLK in FRO192M_CTRL.
Added a feature macro for bit field BODCORE_INT_ENABLE in BOD_DCDC_INT_CTRL.
[2.3.1]
Bug Fixes
Added casts to prevent overflow caused by capturing large target clock.
[2.3.0]
Improvements
Added AUX_BIAS control APIs.
[2.2.0]
Improvements
Added some macros to separate the scenes that some bit fields are reserved for some devices.
Optimized the comments.
Optimized the code implementation inside some functions.
[2.1.2]
Bug Fixes
Fixed MISRA C-2012 rule 10.3 and rule 17.7.
[2.1.1]
Bug Fixes
Removed AnalogTestBus configuration to align with new header.
[2.1.0]
Improvements
Updates for LPC55xx A1.
Removed the control of bitfield FRO192M_CTRL_ENA_48MHZCLK, XO32M_CTRL_ACBUF_PASS_ENABLE.
Removed status bits in ANACTRL_STATUS: PMU_ID OSC_ID FINAL_TEST_DONE_VECT.
Removed API ANACTRL_EnableAdcVBATDivider() and APIs which operate the RingOSC registers.
Removed the configurations of 32 MHz Crystal oscillator voltage source supply control register.
Added API ANACTRL_ClearInterrupts().
[2.0.0]
Initial version.
AOI
[2.0.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.0.1]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.8, 2.2.
[2.0.0]
Initial version.
CACHE64
[2.0.9]
Improvements
Removed assert(false) in CACHE64_GetInstanceByAddr.
[2.0.8]
Improvements
Updated function CACHE64_GetInstanceByAddr() to support some devices that provide alias of cacheable memory section.
[2.0.7]
Improvements
Check input parameter “size_byte” must be larger than 0.
[2.0.6]
Bug Fixes
Fixed overflow for CACHE64_GetInstanceByAddr()/CACHE64_CleanCacheByRange()/CACHE64_InvalidateCacheByRange() APIs.
[2.0.5]
Improvement
Made use of FSL_FEATURE_CACHE64_CTRL_HAS_NO_WRITE_BUF feature
[2.0.4]
Improvement
Disable cache policy feature on SoC without CACHE64_POLSEL IP.
Bug Fixes
Fixed doxygen issue.
[2.0.3]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.3.
[2.0.2]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.1, 10.3, 10.4 and 14.4.
Fixed doxygen issue.
[2.0.1]
Improvements
Moved CLCR register configuration out of the while loop, it’s unnecessary to repeat this operation.
[2.0.0]
Initial version.
CACHE LPCAC
[2.1.1]
Bug Fixes
Fixed an issue of L1CACHE_InvalidateCodeCache() function, to clean cache the LPCAC_CTRL[CLR_LPCAC] should be set not clear.
[2.1.0]
Improvements
Supported more features, such as write buffer contron, write buffer limit and so on.
[2.0.0]
Initial version.
CDOG
[2.1.3]
Re-design multiple instance IRQs and Clocks
Add fix for RESTART command errata
[2.1.2]
Support multiple IRQs
Fix default CONTROL values
[2.1.1]
Remove bit CONTROL[CONTROL_CTRL].
[2.1.0]
Rename CWT to CDOG.
[2.0.2]
Fix MISRA-2012 issues.
[2.0.1]
Fix doxygen issues.
[2.0.0]
Initial version.
CLOCK
[2.3.3]
Bug Fixes
Fixed an issue that ss_progmodfm_t, ss_progmoddp_t, and ss_modwvctrl_t use wrong shift value.
[2.3.2]
Improvements
Add errata workaround for pll lock bit in CLOCK_SetPLL0Freq() and CLOCK_SetPLL1Freq().
[2.0.0]
Initial version.
CMP
[2.2.1]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.1, rule 10.4, and rule 17.7.
[2.2.0]
Improvements:
Added API to configure the sampling mode and clock divider of the CMP Filter.
Supported CMP filter sampling mode configuration.
[2.1.0]
New Features:
Added API to get default CMP user configuration structure.
Supported CMP filter clock divider settings.
Combined the settings of VREF source and VREF value into one API CMP_SetVREF().
Extracted CMP input source selection from CMP_Init() to CMP_SetInputChannels().
Improvements:
Formatted API naming, variable naming and comment style for better readability.
Added comments for APIs in source file.
[2.0.1]
Bug Fixes
Fixed missing ‘const’ qualifier for structure variable in function parameter.
[2.0.0]
Initial version.
COMMON
[2.5.0]
New Features
Added new APIs InitCriticalSectionMeasurementContext, DisableGlobalIRQEx and EnableGlobalIRQEx so that user can measure the execution time of the protected sections.
[2.4.3]
Improvements
Enable irqs that mount under irqsteer interrupt extender.
[2.4.2]
Improvements
Add the macros to convert peripheral address to secure address or non-secure address.
[2.4.1]
Improvements
Improve for the macro redefinition error when integrated with zephyr.
[2.4.0]
New Features
Added EnableIRQWithPriority, IRQ_SetPriority, and IRQ_ClearPendingIRQ for ARM.
Added MSDK_EnableCpuCycleCounter, MSDK_GetCpuCycleCount for ARM.
[2.3.3]
New Features
Added NETC into status group.
[2.3.2]
Improvements
Make driver aarch64 compatible
[2.3.1]
Bug Fixes
Fixed MAKE_VERSION overflow on 16-bit platforms.
[2.3.0]
Improvements
Split the driver to common part and CPU architecture related part.
[2.2.10]
Bug Fixes
Fixed the ATOMIC macros build error in cpp files.
[2.2.9]
Bug Fixes
Fixed MISRA C-2012 issue, 5.6, 5.8, 8.4, 8.5, 8.6, 10.1, 10.4, 17.7, 21.3.
Fixed SDK_Malloc issue that not allocate memory with required size.
[2.2.8]
Improvements
Included stddef.h header file for MDK tool chain.
New Features:
Added atomic modification macros.
[2.2.7]
Other Change
Added MECC status group definition.
[2.2.6]
Other Change
Added more status group definition.
Bug Fixes
Undef __VECTOR_TABLE to avoid duplicate definition in cmsis_clang.h
[2.2.5]
Bug Fixes
Fixed MISRA C-2012 rule-15.5.
[2.2.4]
Bug Fixes
Fixed MISRA C-2012 rule-10.4.
[2.2.3]
New Features
Provided better accuracy of SDK_DelayAtLeastUs with DWT, use macro SDK_DELAY_USE_DWT to enable this feature.
Modified the Cortex-M7 delay count divisor based on latest tests on RT series boards, this setting lets result be closer to actual delay time.
[2.2.2]
New Features
Added include RTE_Components.h for CMSIS pack RTE.
[2.2.1]
Bug Fixes
Fixed violation of MISRA C-2012 Rule 3.1, 10.1, 10.3, 10.4, 11.6, 11.9.
[2.2.0]
New Features
Moved SDK_DelayAtLeastUs function from clock driver to common driver.
[2.1.4]
New Features
Added OTFAD into status group.
[2.1.3]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed the rule: rule-10.3.
[2.1.2]
Improvements
Add SUPPRESS_FALL_THROUGH_WARNING() macro for the usage of suppressing fallthrough warning.
[2.1.1]
Bug Fixes
Deleted and optimized repeated macro.
[2.1.0]
New Features
Added IRQ operation for XCC toolchain.
Added group IDs for newly supported drivers.
[2.0.2]
Bug Fixes
MISRA C-2012 issue fixed.
Fixed the rule: rule-10.4.
[2.0.1]
Improvements
Removed the implementation of LPC8XX Enable/DisableDeepSleepIRQ() function.
Added new feature macro switch “FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION” for specific SoCs which have no noncacheable sections, that helps avoid an unnecessary complex in link file and the startup file.
Updated the align(x) to attribute(aligned(x)) to support MDK v6 armclang compiler.
[2.0.0]
Initial version.
CRC
[2.0.4]
Improvements
Release peripheral from reset if necessary in init function.
[2.0.3]
Bug fix:
Fix MISRA issues.
[2.0.2]
Bug fix:
Fix MISRA issues.
[2.0.1]
Bug fix:
DATA and DATALL macro definition moved from header file to source file.
[2.0.0]
Initial version.
CTIMER
[2.3.3]
Bug Fixes
Fix CERT INT30-C INT31-C issue.
Make API CTIMER_SetupPwm and CTIMER_UpdatePwmDutycycle return fail if pulse width register overflow.
[2.3.2]
Bug Fixes
Clear unexpected DMA request generated by RESET_PeripheralReset in API CTIMER_Init to avoid trigger DMA by mistake.
[2.3.1]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.7 and 12.2.
[2.3.0]
Improvements
Added the CTIMER_SetPrescale(), CTIMER_GetCaptureValue(), CTIMER_EnableResetMatchChannel(), CTIMER_EnableStopMatchChannel(), CTIMER_EnableRisingEdgeCapture(), CTIMER_EnableFallingEdgeCapture(), CTIMER_SetShadowValue(),APIs Interface to reduce code complexity.
[2.2.2]
Bug Fixes
Fixed SetupPwm() API only can use match 3 as period channel issue.
[2.2.1]
Bug Fixes
Fixed use specified channel to setting the PWM period in SetupPwmPeriod() API.
Fixed Coverity Out-of-bounds issue.
[2.2.0]
Improvements
Updated three API Interface to support Users to flexibly configure the PWM period and PWM output.
Bug Fixes
MISRA C-2012 issue fixed: rule 8.4.
[2.1.0]
Improvements
Added the CTIMER_GetOutputMatchStatus() API Interface.
Added feature macro for FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 and FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT.
[2.0.3]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3, 10.4, 10.6, 10.7 and 11.9.
[2.0.2]
New Features
Added new API “CTIMER_GetTimerCountValue” to get the current timer count value.
Added a control macro to enable/disable the RESET and CLOCK code in current driver.
Added a new feature macro to update the API of CTimer driver for lpc8n04.
[2.0.1]
Improvements
API Interface Change
Changed API interface by adding CTIMER_SetupPwmPeriod API and CTIMER_UpdatePwmPulsePeriod API, which both can set up the right PWM with high resolution.
[2.0.0]
Initial version.
DAC
[2.1.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.1.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules.
[2.1.0]
New Features
Added support for period trigger mode.
Added support for sync trigger between dac instances.
Added support for configuring DAC sync cycles.
Added support for internal reference current selection.
Enabled buffer mode manually for K4 series board.
[2.0.2]
Bug Fixes
Fixed MISRA C-2012 rule 10.3 and rule 17.7.
[2.0.1]
New Features
Added a control macro to enable/disable the CLOCK code in current driver.
[2.0.0]
Initial version.
LPC_DMA
[2.5.3]
Improvements
Add assert in DMA_SetChannelXferConfig to prevent XFERCOUNT value overflow.
[2.5.2]
Bug Fixes
Use separate “SET” and “CLR” registers to modify shared registers for all channels, in case of thread-safe issue.
[2.5.1]
Bug Fixes
Fixed violation of the MISRA C-2012 rule 11.6.
[2.5.0]
Improvements
Added a new api DMA_SetChannelXferConfig to set DMA xfer config.
[2.4.4]
Bug Fixes
Fixed the issue that DMA_IRQHandle might generate redundant callbacks.
Fixed the issue that DMA driver cannot support channel bigger then 32.
Fixed violation of the MISRA C-2012 rule 13.5.
[2.4.3]
Improvements
Added features FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn/FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE/FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE to support the descriptor align size not constant in the two instances.
[2.4.2]
Bug Fixes
Fixed violation of the MISRA C-2012 rule 8.4.
[2.4.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 5.7, 8.3.
[2.4.0]
Improvements
Added new APIs DMA_LoadChannelDescriptor/DMA_ChannelIsBusy to support polling transfer case.
Bug Fixes
Added address alignment check for descriptor source and destination address.
Added DMA_ALLOCATE_DATA_TRANSFER_BUFFER for application buffer allocation.
Fixed the sign-compare warning.
Fixed violations of the MISRA C-2012 rules 18.1, 10.4, 11.6, 10.7, 14.4, 16.3, 20.7, 10.8, 16.1, 17.7, 10.3, 3.1, 18.1.
[2.3.0]
Bug Fixes
Removed DMA_HandleIRQ prototype definition from header file.
Added DMA_IRQHandle prototype definition in header file.
[2.2.5]
Improvements
Added new API DMA_SetupChannelDescriptor to support configuring wrap descriptor.
Added wrap support in function DMA_SubmitChannelTransfer.
[2.2.4]
Bug Fixes
Fixed the issue that macro DMA_CHANNEL_CFER used wrong parameter to calculate DSTINC.
[2.2.3]
Bug Fixes
Improved DMA driver Deinit function for correct logic order.
Improvements
Added API DMA_SubmitChannelTransferParameter to support creating head descriptor directly.
Added API DMA_SubmitChannelDescriptor to support ping pong transfer.
Added macro DMA_ALLOCATE_HEAD_DESCRIPTOR/DMA_ALLOCATE_LINK_DESCRIPTOR to simplify DMA descriptor allocation.
[2.2.2]
Bug Fixes
Do not use software trigger when hardware trigger is enabled.
[2.2.1]
Bug Fixes
Fixed Coverity issue.
[2.2.0]
Improvements
Changed API DMA_SetupDMADescriptor to non-static.
Marked APIs below as deprecated.
DMA_PrepareTransfer.
DMA_Submit transfer.
Added new APIs as below:
DMA_SetChannelConfig.
DMA_PrepareChannelTransfer.
DMA_InstallDescriptorMemory.
DMA_SubmitChannelTransfer.
DMA_SetChannelConfigValid.
DMA_DoChannelSoftwareTrigger.
DMA_LoadChannelTransferConfig.
[2.0.1]
Improvements
Added volatile for DMA descriptor member xfercfg to avoid optimization.
[2.0.0]
Initial version.
DMIC
[2.3.2]
New Features
Supported 4 channels in driver.
[2.3.1]
Bug Fixes
Fixed the issue that DMIC_EnableChannelDma and DMIC_EnableChannelFifo did not clean relevant bits.
[2.3.0]
Improvements
Added new apis DMIC_ResetChannelDecimator/DMIC_EnableChannelGlobalSync/DMIC_DisableChannelGlobalSync.
[2.2.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 14.4, 17.7, 10.4, 10.3, 10.8, 14.3.
[2.2.0]
Bug Fixes
Corrected the usage of feature FSL_FEATURE_DMIC_IO_HAS_NO_BYPASS.
[2.1.1]
Improvements
Added feature FSL_FEATURE_DMIC_HAS_NO_IOCFG for IOCFG register.
[2.1.0]
New Features
Added API DMIC_EnbleChannelInterrupt/DMIC_EnbleChannelDma to replace API DMIC_SetOperationMode.
Added API DMIC_SetIOCFG and marked DMIC_ConfigIO as deprecated.
Added API DMIC_EnableChannelSignExtend to support sign extend feature.
[2.0.5]
Improvements
Changed some parameters’ value of DMIC_FifoChannel API, such as enable, resetn, and trig_level. This is not possible for the current code logic, so it improves the DMIC_FifoChannel logic and fixes incorrect math logic.
[2.0.4]
Bug Fixes
Fixed the issue that DMIC DMA driver(ver2.0.3) did not support calling DMIC_TransferReceiveDMA in DMA callback as it did before version 2.0.3. But calling DMIC_TransferReceiveDMA in callback is not recommended.
[2.0.3]
New Features
Supported linked transfer in DMIC DMA driver.
Added new API DMIC_EnableChannelFifo/DMIC_DoFifoReset/DMIC_InstallDMADescriptor.
[2.0.2]
New Features
Supported more channels in driver.
[2.0.1]
New Features
Added a control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.0]
Initial version.
DMIC_DMA
[2.4.0]
Bug Fixes
Fixed the issue that DMIC_TransferAbortReceiveDMA can not disable dmic and dma request issue.
[2.3.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3.
[2.3.0]
Refer DMIC driver change log 2.0.1 to 2.3.0
ENC
[2.2.1]
Improvements
Release peripheral from reset if necessary in init function.
[2.2.0]
New Features
Supported input filter prescaler.
[2.1.0]
Improvements
Supported period measurement function.
[2.0.2]
Improvements
Added feature macro for CTRL2[SABIE] and CTRL2[SABIRQ] bits.
[2.0.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1, 10.3, 10.4, 10.6, 17.7.
[2.0.0]
Initial version.
FLEXCOMM
[2.0.2]
Bug Fixes
Fixed typos in FLEXCOMM15_DriverIRQHandler().
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 10.7, 10.8, 11.3, 11.6, 11.8, 11.9, 13.5.
Improvements
Added instance calculation in FLEXCOMM16_DriverIRQHandler() to align with Flexcomm 14 and 15.
[2.0.1]
Improvements
Added more IRQHandler code in drivers to adapt new devices.
[2.0.0]
Initial version.
FLEXSPI
[2.6.3]
Bug Fixes
Fixed an issue which cause IPCR1[IPAREN] cleared by mistake.
[2.6.2]
Bug Fixes
Wait Bus IDLE before operation of FLEXSPI_SoftwareReset(), FLEXSPI_TransferBlocking() and FLEXSPI_TransferNonBlocking().
[2.6.1]
Bug Fixes
Updated code of reset peripheral.
Updated FLEXSPI_UpdateLUT() to check if input lut address is not in Flexspi AMBA region.
Updated FLEXSPI_Init() to check if input AHB buffer size exceeded maximum AHB size.
[2.6.0]
New Features
Added new API to set AHB memory-mapped flash base address.
Added support of DLLxCR[REFPHASEGAP] bit field, it is recommended to set it as 0x2 if DLL calibration is enabled.
[2.5.1]
Bugfixes
Fixed handling of W1C bits in the INTR register
Removed FIFO resets from FLEXSPI_CheckAndClearError
FLEXSPI_TransferBlocking is observing IPCMDDONE and then fetches the final status of the transfer
Fixed issue that FLEXSPI2_DriverIRQHandler not defined.
[2.5.0]
Improvements
Supported word un-aligned access for write/read blocking/non-blocking API functions.
Fixed dead loop issue in DLL update function when using FRO clock source.
Fixed violations of the MISRA C-2012 Rule 10.3.
[2.4.0]
Improvements
Isolated IP command parallel mode and AHB command parallel mode using feature MACRO.
Supported new column address shift feature for external memory.
[2.3.5]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 14.2.
[2.3.4]
Bug Fixes
Updated flexspi_config_t structure and FlexSPI_Init to support new feature FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_CONBINATION.
[2.3.3]
Bug Fixes
Removed feature FSL_FEATURE_FLEXSPI_DQS_DELAY_PS for DLL delay setting. Changed to use feature FSL_FEATURE_FLEXSPI_DQS_DELAY_MIN to set slave delay target as 0 for DLL enable and clock frequency higher than 100MHz.
[2.3.2]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 8.4, 8.5, 10.1, 10.3, 10.4, 11.6 and 14.4.
[2.3.1]
Bug Fixes
Wait for bus to be idle before using it as access to external flash with new setting in FLEXSPI_SetFlashConfig() API.
Fixed the potential buffer overread and Tx FIFO overwrite issue in FLEXSPI_WriteBlocking.
[2.3.0]
New Features
Added new API FLEXSPI_UpdateDllValue for users to update DLL value after updating flexspi root clock.
Corrected grammatical issues for comments.
Added support for new feature FSL_FEATURE_FLEXSPI_DQS_DELAY_PS in DLL configuration.
[2.2.2]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.1, 10.3 and 10.4.
Updated _flexspi_command from named enumerator into anonymous enumerator.
[2.2.1]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.1, 10.3, 10.4, 10.8, 11.9, 14.4, 15.7, 16.4, 17.7, 7.3.
Fixed IAR build warning Pe167.
Fixed the potential buffer overwrite and Rx FIFO overread issue in FLEXSPI_ReadBlocking.
[2.2.0]
Bug Fixes
Fixed flag name typos: kFLEXSPI_IpTxFifoWatermarkEmpltyFlag to kFLEXSPI_IpTxFifoWatermarkEmptyFlag; kFLEXSPI_IpCommandExcutionDoneFlag to kFLEXSPI_IpCommandExecutionDoneFlag.
Fixed comments typos such as sequencen->sequence, levle->level.
Fixed FLSHCR2[ARDSEQID] field clean issue.
Updated flexspi_config_t structure and FlexSPI_Init to support new feature FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN and FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN.
Updated flexspi_flags_t structure to support new feature FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN.
[2.1.1]
Improvements
Defaulted enable prefetch for AHB RX buffer configuration in FLEXSPI_GetDefaultConfig, which is align with the reset value in AHBRXBUFxCR0.
Added software workaround for ERR011377 in FLEXSPI_SetFlashConfig; added some delay after DLL lock status set to ensure correct data read/write.
[2.1.0]
New Features
Added new API FLEXSPI_UpdateRxSampleClock for users to update read sample clock source after initialization.
Added reset peripheral operation in FLEXSPI_Init if required.
[2.0.5]
Bug Fixes
Fixed FLEXSPI_UpdateLUT cannot do partial update issue.
[2.0.4]
Bug Fixes
Reset flash size to zero for all ports in FLEXSPI_Init; fixed the possible out-of-range flash access with no error reported.
[2.0.3]
Bug Fixes
Fixed AHB receive buffer size configuration issue. The FLEXSPI_AHBRXBUFCR0_BUFSZ field should configure 64 bits size, and currently the AHB receive buffer size is in bytes which means 8-bit, so the correct configuration should be config->ahbConfig.buffer[i].bufferSize / 8.
[2.0.2]
New Features
Supported DQS write mask enable/disable feature during set FLEXSPI configuration.
Provided new API FLEXSPI_TransferUpdateSizeEDMA for users to update eDMA transfer size(SSIZE/DSIZE) per DMA transfer.
Bug Fixes
Fixed invalid operation of FLEXSPI_Init to enable AHB bus Read Access to IP RX FIFO.
Fixed incorrect operation of FLEXSPI_Init to configure IP TX FIFO watermark.
[2.0.1]
Bug Fixes
Fixed the flag clear issue and AHB read Command index configuration issue in FLEXSPI_SetFlashConfig.
Updated FLEXSPI_UpdateLUT function to update LUT table from any index instead of previous command index.
Added bus idle wait in FLEXSPI_SetFlashConfig and FLEXSPI_UpdateLUT to ensure bus is idle before any change to FlexSPI controller.
Updated interrupt API FLEXSPI_TransferNonBlocking and interrupt handle flow FLEXSPI_TransferHandleIRQ.
Updated eDMA API FLEXSPI_TransferEDMA.
[2.0.0]
Initial version.
FLEXSPI DMA Driver
[2.2.1]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.1, 10.3, 10.4, 10.8.
[2.2.0]
Bug Fixes
Fixed violations of the MISRA C-2012 Rule 10.1, 10.3.
New Features
Updated name of FLEXSPI_TransferGetTransferCountDMA API.
[2.1.1]
New Features
Updated driver to support feature FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES.
[2.1.0]
Bug Fixes
Updated enumaration flexspi_dma_transfer_nsize_t and remove the unsupported items.
New Features
Updated driver for deprecating the multiple linked descriptors inside FLEXSPI_TransferDMA, only up to one linked descriptor is needed according to hardware update.
[2.0.0]
Initial version.
FREQME
[2.1.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.1.1]
Fixed MISRA issues.
[2.1.0]
Updated register name.
[2.0.0]
Initial version.
GINT
[2.1.1]
Improvements
Added support for platforms with PORT_POL and PORT_ENA registers without arrays.
[2.1.0]
Improvements
Updated for platforms which only has one port.
[2.0.3]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.8.
[2.0.2]
Bug Fixes
Fixed issue for MISRA-2012 check.
Fixed rule 17.7.
[2.0.1]
Added control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.0]
Initial version.
GPIO
[2.1.7]
Improvements
Enhanced GPIO_PinInit to enable clock internally.
[2.1.6]
Bug Fixes
Clear bit before set it within GPIO_SetPinInterruptConfig() API.
[2.1.5]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 3.1, 10.6, 10.7, 17.7.
[2.1.4]
Improvements
Added API GPIO_PortGetInterruptStatus to retrieve interrupt status for whole port.
Corrected typos in header file.
[2.1.3]
Improvements
Updated “GPIO_PinInit” API. If it has DIRCLR and DIRSET registers, use them at set 1 or clean 0.
[2.1.2]
Improvements
Removed deprecated APIs.
[2.1.1]
Improvements
API interface changes:
Refined naming of APIs while keeping all original APIs, marking them as deprecated. Original APIs will be removed in next release. The mainin change is updating APIs with prefix of _PinXXX() and _PorortXXX
[2.1.0]
New Features
Added GPIO initialize API.
[2.0.0]
Initial version.
HSCMP
[2.0.4]
Improvements
Release peripheral from reset if necessary in init function.
[2.0.3]
Bug Fixes:
Fixed the violation of MISRA-2012 rule 17.7.
[2.0.2]
Bug Fixes:
The current API LPCMP_ClearStatusFlags has to check w1c bits.
[2.0.1]
Added control macro to enable/disable the CLOCK code in current driver.
[2.0.0]
Initial version.
I2C
[2.3.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.1.
Fixed issue that if master only sends address without data during I2C interrupt transfer, address nack cannot be detected.
[2.3.2]
Improvement
Enable or disable timeout option according to enableTimeout.
Bug Fixes
Fixed timeout value calculation error.
Fixed bug that the interrupt transfer cannot recover from the timeout error.
[2.3.1]
Improvement
Before master transfer with transactional APIs, enable master function while disable slave function and vise versa for slave transfer to avoid the one affecting the other.
Bug Fixes
Fixed bug in I2C_SlaveEnable that the slave enable/disable should not affect the other register bits.
[2.3.0]
Improvement
Added new return codes kStatus_I2C_EventTimeout and kStatus_I2C_SclLowTimeout, and added the check for event timeout and SCL timeout in I2C master transfer.
Fixed bug in slave transfer that the address match event should be invoked before not after slave transmit/receive event.
[2.2.0]
New Features
Added enumeration _i2c_status_flags to include all previous master and slave status flags, and added missing status flags.
Modified I2C_GetStatusFlags to get all I2C flags.
Added API I2C_ClearStatusFlags to clear all clearable flags not just master flags.
Modified master transactional APIs to enable bus event timeout interrupt during transfer, to avoid glitch on bus causing transfer hangs indefinitely.
Bug Fixes
Fixed bug that status flags and interrupt enable masks share the same enumerations by adding enumeration _i2c_interrupt_enable for all master and slave interrupt sources.
[2.1.0]
Bug Fixes
Fixed bug that during master transfer, when master is nacked during slave probing or sending subaddress, the return status should be kStatus_I2C_Addr_Nak rather than kStatus_I2C_Nak.
Bug Fixes
Fixed MISRA issues.
Fixed rules 10.1, 10.4, 13.5.
New Features
Added macro I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK, so that user can configure whether to ignore the last byte being nacked by slave during master transfer.
[2.0.8]
Bug Fixes
Fixed I2C_MasterSetBaudRate issue that MSTSCLLOW and MSTSCLHIGH are incorrect when MSTTIME is odd.
[2.0.7]
Bug Fixes
Two dividers, CLKDIV and MSTTIME are used to configure baudrate. According to reference manual, in order to generate 400kHz baudrate, the clock frequency after CLKDIV must be less than 2mHz. Fixed the bug that, the clock frequency after CLKDIV may be larger than 2mHz using the previous calculation method.
Fixed MISRA 10.1 issues.
Fixed wrong baudrate calculation when feature FSL_FEATURE_I2C_PREPCLKFRG_8MHZ is enabled.
[2.0.6]
New Features
Added master timeout self-recovery support for feature FSL_FEATURE_I2C_TIMEOUT_RECOVERY.
Bug Fixes
Eliminated IAR Pa082 warning.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 10.7, 10.8, 11.3, 11.6, 11.8, 11.9, 13.5.
[2.0.5]
Bug Fixes
Fixed wrong assignment for datasize in I2C_InitTransferStateMachineDMA.
Fixed wrong working flow in I2C_RunTransferStateMachineDMA to ensure master can work in no start flag and no stop flag mode.
Fixed wrong working flow in I2C_RunTransferStateMachine and added kReceiveDataBeginState in _i2c_transfer_states to ensure master can work in no start flag and no stop flag mode.
Fixed wrong handle state in I2C_MasterTransferDMAHandleIRQ. After all the data has been transfered or nak is returned, handle state should be changed to idle.
Improvements
Rounded up the calculated divider value in I2C_MasterSetBaudRate.
[2.0.4]
Improvements
Updated the I2C_WATI_TIMEOUT macro to unified name I2C_RETRY_TIMES
Updated the “I2C_MasterSetBaudRate” API to support baudrate configuration for feature QN9090.
Bug Fixes
Fixed build warnning caused by uninitialized variable.
Fixed COVERITY issue of unchecked return value in I2C_RTOS_Transfer.
[2.0.3]
Improvements
Unified the component full name to FLEXCOMM I2C(DMA/FREERTOS) driver.
[2.0.2]
Improvements
In slave IRQ:
Changed slave receive process to first set the I2C_SLVCTL_SLVCONTINUE_MASK to acknowledge the received data, then do data receive.
Improved slave transmit process to set the I2C_SLVCTL_SLVCONTINUE_MASK immediately after writing the data.
[2.0.1]
Improvements
Added I2C_WATI_TIMEOUT macro to allow users to specify the timeout times for waiting flags in functional API and blocking transfer API.
[2.0.0]
Initial version.
I2S
[2.3.2]
Bug Fixes
Fixed warning for comparison between pointer and integer.
[2.3.1]
Bug Fixes
Updated the value of TX/RX software transfer state machine after transfer contents are submitted to avoid race condition.
[2.3.0]
Improvements
Added api I2S_InstallDMADescriptorMemory/I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA to support loop transfer.
Added api I2S_EmptyTxFifo to support blocking flush tx fifo.
Updated api I2S_TransferAbortDMA by removed the blocking flush tx fifo from this function.
Bug Fixes
Removed the while loop in abort transfer function to fix the dead loop issue under specific user case.
[2.2.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4.
[2.2.1]
Improvements
Added feature FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn for the SOC has parts of instance support secondary channel.
Bug Fixes
Added volatile statement for the state variable of i2s_handle and enable the mainline channel pair before enable interrupt to avoid the issue of code excution reordering which may cause the interrupt generated unexpectedly.
[2.2.0]
Improvements
Added 8/16/24 bits mono data format transfer support in I2S driver.
Added new apis I2S_SetBitClockRate.
Bug Fixes
Fixed the PA082 build warning.
Fixed the sign-compare warning.
Fixed violations of the MISRA C-2012 rules 10.4, 10.8, 11.9, 10.1, 11.3, 13.5, 11.8, 10.3, 10.7.
Fixed the Operand don’t affect result Coverity issue.
[2.1.0]
Improvements
Added a feature for the FLEXCOMM which supports I2S and has interconnection with DMIC.
Used a feature to control PDMDATA instead of I2S_CFG1_PDMDATA.
Added member bytesPerFrame in i2s_dma_handle_t, used for DMA transfer width configure, instead of using sizeof(uint32_t) hardcode.
Used the macro provided by DMA driver to define the I2S DMA descriptor.
Bug Fixes
Fixed the issue that I2S DMA driver always generated duplicate callback.
[2.0.3]
New Features
Added a feature to remove configuration for the second channel on LPC51U68.
[2.0.2]
New Features
Added ENABLE_IRQ handle after register I2S interrupt handle.
[2.0.1]
Improvements
Unified the component full name to FLEXCOMM I2S (DMA) driver.
[2.0.0]
Initial version.
I2S_DMA
[2.3.3]
Bug Fixes
Fixed data size limit does not match the macro DMA_MAX_TRANSFER_BYTES issue.
[2.3.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3.
[2.3.1]
Refer I2S driver change log 2.0.1 to 2.3.1
I3C
[2.13.1]
Bug Fixes
Disabled Rx auto-termination in repeated start interrupt event while transfer API doesn’t enable it.
Waited the completion event after loading all Tx data in Tx FIFO.
Improvements
Conditionally compile interrupt handling code to solve the problem of using this driver on CPU cores that do not support interrupts.
[2.13.0]
New features
Added the hot-join support for I3C bus initialization API.
Bug Fixes
Set read termination with START at the same time in case unknown issue.
Set MCTRL[TYPE] as 0 for DDR force exit.
Improvements
Added the API to reset device count assigned by ENTDAA.
Provided the method to set global macro I3C_MAX_DEVCNT to determine how many device addresses ENTDAA can allocate at one time.
Initialized target management static array based on instance number for the case that multiple instances are used at the same time.
[2.12.0]
Improvements
Added the slow clock parameter for Controller initialization function to calculate accurate timeout.
Bug Fixes
Fixed the issue that BAMATCH field can’t be 0. BAMATCH should be 1 for 1MHz slow clock.
[2.11.1]
Bug Fixes
Fixed the issue that interrupt API transmits extra byte when subaddress and data size are null.
Fixed the slow clock calculation issue.
[2.11.0]
New features
Added the START/ReSTART SCL delay setting for the Soc which supports this feature.
Bug Fixes
Fixed the issue that ENTDAA process waits Rx pending flag which causes problem when Rx watermark isn’t 0. Just check the Rx FIFO count.
[2.10.8]
Improvements
Support more instances.
[2.10.7]
Improvements
Fixed the potential compile warning.
[2.10.6]
New features
Added the I3C private read/write with 0x7E address as start.
[2.10.5]
New features
Added I3C HDR-DDR transfer support.
[2.10.4]
Improvements
Added one more option for master to not set RDTERM when doing I3C Common Command Code transfer.
[2.10.3]
Improvements
Masked the slave IBI/MR/HJ request functions with feature macro.
[2.10.2]
Bug Fixes
Added workaround for errata ERR051617: I3C working with I2C mode creates the unintended Repeated START before actual STOP on some platforms.
[2.10.1]
Bug Fixes
Fixed the issue that DAA function doesn’t wait until all Rx data is read out from FIFO after master control done flag is set.
Fixed the issue that DAA function could return directly although the disabled interrupts are not enabled back.
[2.10.0]
New features
Added I3C extended IBI data support.
[2.9.0]
Improvements
Added adaptive termination for master blocking transfer. Set termination with start signal when receiving bytes less than 256.
[2.8.2]
Improvements
Fixed the build warning due to armgcc strict check.
[2.8.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 17.7.
[2.8.0]
Improvements
Added API I3C_MasterProcessDAASpecifiedBaudrate for temporary baud rate adjustment when I3C master assigns dynamic address.
[2.7.1]
Bug Fixes
Fixed the issue that I3C slave handle STOP event before finishing data transmission.
[2.7.0]
Fixed the CCM problem in file fsl_i3c.c.
Fixed the FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND usage issue in I3C_GetDefaultConfig and I3C_Init.
[2.6.0]
Fixed the FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND usage issue in fsl_i3c.h.
Changed some static functions in fsl_i3c.c as non-static and define the functions in fsl_i3c.h to make I3C DMA driver reuse:
I3C_GetIBIType
I3C_GetIBIAddress
I3C_SlaveCheckAndClearError
Changed the handle pointer parameter in IRQ related funtions to void * type to make it reuse in I3C DMA driver.
Added new API I3C_SlaveRequestIBIWithSingleData for slave to request single data byte, this API could be used regardless slave is working in non-blocking interrupt or non-blocking dma.
Added new API I3C_MasterGetDeviceListAfterDAA for master application to get the device information list built up in DAA process.
[2.5.4]
Improved I3C driver to avoid setting state twice in the SendCommandState of I3C_RunTransferStateMachine.
Fixed MISRA violation of rule 20.9.
Fixed the issue that I3C_MasterEmitRequest did not use Type I3C SDR.
[2.5.3]
Updated driver for new feature FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH and FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND.
[2.5.2]
Updated driver for new feature FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM.
Fixed the issue that call to I3C_MasterTransferBlocking API did not generate STOP signal when NAK status was returned.
[2.5.1]
Improved the receive terminate size setting for interrupt transfer read, now it’s set at beginning of transfer if the receive size is less than 256 bytes.
[2.5.0]
Added new API I3C_MasterRepeatedStartWithRxSize to send repeated start signal with receive terminate size specified.
Fixed the status used in I3C_RunTransferStateMachine, changed to use pending interrupts as status to be handled in the state machine.
Fixed MISRA 2012 violation of rule 10.3, 10.7.
[2.4.0]
Bug Fixes
Fixed kI3C_SlaveMatchedFlag interrupt is not properly handled in I3C_SlaveTransferHandleIRQ when it comes together with interrupt kI3C_SlaveBusStartFlag.
Fixed the inaccurate I2C baudrate calculation in I3C_MasterSetBaudRate.
Added new API I3C_MasterGetIBIRules to get registered IBI rules.
Added new variable isReadTerm in struct _i3c_master_handle for transfer state routine to check if MCTRL.RDTERM is configured for read transfer.
Changed to emit Auto IBI in transfer state routine for slave start flag assertion.
Fixed the slave maxWriteLength and maxReadLength does not be configured into SMAXLIMITS register issue.
Fixed incorrect state for IBI in I3C master interrupt transfer IRQ handle routine.
Added isHotJoin in i3c_slave_config_t to request hot-join event during slave init.
[2.3.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 17.7.
Fixed incorrect HotJoin event index in I3C_GetIBIType.
[2.3.1]
Bug Fixes
Fixed the issue that call of I3C_MasterTransferBlocking/I3C_MasterTransferNonBlocking fails for the case which receive length 1 byte of data.
Fixed the issue that STOP signal is not sent when NAK status is detected during execution of I3C_MasterTransferBlocking function.
[2.3.0]
Improvements
Added I3C common driver APIs to initialize I3C with both master and slave configuration.
Updated I3C master transfer callback to function set structure to include callback invoke for IBI event and slave2master event.
Updated I3C master non-blocking transfer model and always enable the interrupts to be able to re-act to the slave start event and handle slave IBI.
[2.2.0]
Bug Fixes
Fixed the issue that I3C transfer size limit to 255 bytes.
[2.1.2]
Bug Fixes
Reset default hkeep value to kI3C_MasterHighKeeperNone in I3C_MasterGetDefaultConfig
[2.1.1]
Bug Fixes
Fixed incorrect FIFO reset operation in I3C Master Transfer APIs.
Fixed i3c slave IRQ handler issue, slave transmit could be underrun because tx FIFO is not filled in time right after start flag detected.
[2.1.0]
Added definitions and APIs for I3C slave functionality, updated previous I3C APIs to support I3C functionality.
[2.0.0]
Initial version.
I3C_DMA
[2.1.8]
Bug Fixes
Updated the logic to handle Rx termination and complete event to adapt different situation.
Improvements
Added the MCTRLDONE flag check after STOP request to ensure the completion of whole transfer operation.
[2.1.7]
Bug Fixes
Fixed the issue to use subaddress to read/write data with RT500/600 DMA.
[2.1.6]
Improvements
Added the FSL_FEATURE_I3C_HAS_NO_MASTER_DMA_WDATA_REG to select the correct register to write data based on specific Soc.
[2.1.5]
New features
Supported I3C HDR-DDR transfer with DMA.
Improvements
Added workaround for RT500/600 I3C DMA transfer.
Removed I3C IRQ handler calling in the Tx EDMA callback. Previously driver doesn’t use the END byte which can trigger the complete interrupt for controller sending and receiving, now let I3C event handler deal with I3C events.
Used linked DMA to transfer all I3C subaddress and data without handling of intermediate states, simplifying code logic.
Prepare the Tx DMA before I3C START to ensure there’s no time delay between START and transmitting data.
[2.1.4]
Improvements
Used linked DMA transfer to reduce the latency between DMA transfers previous data and the END byte.
[2.1.3]
Bug Fixes
Fixed the MISRA issue rule 10.4, 11.3.
[2.1.2]
Bug Fixes
Fixed the issue that I3C slave send the last byte data without using the END type register.
[2.1.1]
Bug Fixes
Fixed MISRA issue rule 9.1.
[2.1.0]
Improvements
Deleted legacy IBI data request code.
[2.0.1]
Bug Fixes
Fixed issue that bus STOP occurs when Tx FIFO still takes data.
Improvements
Fixed the build warning due to armgcc strict check.
[2.0.0]
Initial version.
INPUTMUX
[2.0.8]
Improvements
Updated a feature macro usage for function INPUTMUX_EnableSignal.
[2.0.7]
Improvements
Release peripheral from reset if necessary in init function.
[2.0.6]
Bug Fixes
Fixed the documentation wrong in API INPUTMUX_AttachSignal.
[2.0.5]
Bug Fixes
Fixed build error because some devices has no sct.
[2.0.4]
Bug Fixes
Fixed violations of the MISRA C-2012 rule 10.4, 12.2 in INPUTMUX_EnableSignal() function.
[2.0.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.4, 10.7, 12.2.
[2.0.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.4, 12.2.
[2.0.1]
Support channel mux setting in INPUTMUX_EnableSignal().
[2.0.0]
Initial version.
IOCON
[2.2.0]
Improvements
Removed duplicate macro defintions.
Renamed ‘IOCON_I2C_SLEW’ macro to ‘IOCON_I2C_MODE’ to match its companion ‘IOCON_GPIO_MODE’. The original is kept as a deprecated symbol.
[2.1.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3.
[2.1.1]
Updated left shift format with mask value instead of a constant value to automatically adapt to all platforms.
[2.1.0]
Added a new IOCON_PinMuxSet() function with a feature IOCON_ONE_DIMENSION for LPC845MAX board.
[2.0.0]
Initial version.
IPED
[2.2.0]
Renamed CSS to ELS.
[2.1.1]
Fix build error due to renamed symbols.
[2.1.0]
Add IPED_Config() (including FFR CMPA write) and IPED_Reconfig() features.
[2.0.0]
Initial version.
IRTC
[2.3.2]
Bug Fixes
Fixed API IRTC_GetDatetime read YEARMON, DAYS, HOURMIN, SECONDS registers issue.
[2.3.1]
Bug Fixes
Fixed MISRA C-2012 issue 10.4.
[2.3.0]
New Feature
Supported platforms with multiple IRTC instances.
[2.2.4]
Bug Fixes
Fixed MISRA C-2012 issue 10.1, 10.3, 10.4, 10.7, 12.2.
[2.2.3]
Bug Fixes
Updated undefined macro names by available ones.
[2.2.2]
Bug Fixes
Fixed MISRA C-2012 issue 10.3.
[2.2.1]
Bug Fixes
Fixed MISRA issues.
[2.2.0]
New Feature
Add new APIs for CLK_SEL and CLKO to select RTC clock and enable/disable output to peripherals.
Supported platforms without tamper feature.
[2.1.3]
Bug Fixes
Fixed MISRA C-2012 issue 10.1 and 10.4.
[2.1.2]
Bug Fixes
Fixed kIRTC_TamperFlag flag can’t be cleared issue.
[2.1.1]
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-10.1, rule-10.3, rule-10.4.
[2.1.0]
Bug Fixes
Fixed incorrect leap year check in IRTC_CheckDatetimeFormat.
New Feature
Added new APIs for new feature FSL_FEATURE_RTC_HAS_SUBSYSTEM.
Added new APIs for TAMPER, TAMPER QUEUE status get and clear.
Added new API to enable/disable 32 kHz RTC OSC clock during RTC register write.
Updated IRTC_SetTamperParams to support new feature FSL_FEATURE_RTC_HAS_FILTER23_CFG
Updated irtc_config_t to exclude member wakeupSelect for new feature FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE.
[2.0.2]
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-10.1, rule-10.3, rule-10.4, rule-10.6, rule-10.8, rule-11.9, rule-12.2, rule-15.5, rule-16.4, rule-17.7.
[2.0.1]
Bug Fixes
Fixed the issue of hard code in IRTC_Init.
[2.0.0]
Initial version.
ITRC
[2.4.0]
Rework the input signal definition for better flexibility
[2.3.0]
Update names of kITRC_SwEvent1/2 to kITRC_SwEvent0/1 to align with RM
[2.2.0]
Update driver to new version and input events
[2.1.0]
Make SYSCON glitch platform dependent.
[2.0.0]
Initial version.
LPADC
[2.9.1]
Bug Fixes
Fixed incorrect channel B FIFO selection logic.
[2.9.0]
Bug Fixes
Add code to handle the case where GCC[GAIN_CAL] is a signed number.
Split LPADC_FinishAutoCalibration function into two functions.
Improved LPADC driver.
[2.8.4]
Bug Fixes
Remove function ‘LPADC_SetOffsetValue’ assert statement, this statement may cause runtime errors in existing code.
[2.8.3]
Bug Fixes
Fixed SDK lpadc driver examples compile issue, move condition ‘commandId < ADC_CV_COUNT’ to a more appropriate location.
[2.8.2]
Bug Fixes
Fixed the violations of MISRA C-2012 rule 18.1, 10.3, 10.1 and 10.4.
[2.8.1]
Bug Fixes
Fixed LPADC sample mode enum name mistake.
[2.8.0]
Improvements
Release peripheral from reset if necessary in init function.
Bug Fixes
Fixed function LPADC_GetConvResult() issue.
Fixed function LPADC_SetConvCommandConfig() bugs.
[2.7.2]
Improvements
Use feature macros instead of header file macros.
Bug Fixes
Fixed the violations of MISRA C-2012 rule 10.1, 10.3, 10.4 and 14.3.
[2.7.1]
Improvements
Corrected descriptions of several functions.
Improved function LPADC_GetOffsetValue and LPADC_SetOffsetValue.
Revert changes of feature macros for lpadc.
Use feature macros instead of header file macros.
Bug Fixes
Fixed the violations of MISRA C-2012 rule 10.8.
Fixed the violations of MISRA C-2012 rule 10.1, 10.3, 10.4 and 14.3.
[2.7.0]
Improvements
Added supports of CFG2 register.
Removed some useless macros.
[2.6.2]
Bug Fixes
Fixed the violations of MISRA C-2012 rules.
Fixed LPADC driver code compile error issue.
[2.6.1]
Improvements
Updated the use of macros in the driver code.
[2.6.0]
Improvements
Added the API LPADC_SetOffset12BitValue() to configure 12bit ADC conversion offset trim value manually.
Added the API LPADC_SetOffset16BitValue() to configure 16bit ADC conversion offset trim value manually.
Added API to set offset calibration mode.
Added configuration of alternate channel.
Updated auto calibration API and added calibration value conversion API.
New feature
Added API LPADC_EnableHardwareTriggerCommandSelection() to enable trigger commands controlled by ADC_ETC.
Updated LPADC_DoAutoCalibration() to allow doing something else before the ADC inititialization to be totally complete. Enhance initialization duration time of the ADC.
Added two new APIs to get/set calibration value.
[2.5.2]
Improvements
Added while loop, LPADC_GetConvResult() will return only when the FIFO will not be empty.
[2.5.1]
Bug Fixes
Fixed some typos in Lpadc driver comments.
[2.5.0]
Improvements
Added missing items to enable trigger interrupts.
[2.4.0]
New features
Added APIs to get/clear trigger status flags.
[2.3.0]
Improvements
Removed LPADC_MeasureTemperature() function for the LPADC supports different temperature sensor calculation equations.
[2.2.1]
Improvements
Optimized LPADC_MeasureTemperature() function to support the specific series with flash solidified calibration value.
Clean doxygen warnings.
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.3, rule 10.8 and rule 17.7.
[2.2.0]
New Feature
Added API LPADC_MeasureTemperature() to get correct temperature from the internal sensor.
Improvements
Separated lpadc_conversion_resolution_mode_t with related feature macro.
Bug Fixes
Fixed the violations of MISRA C-2012 rules:
Rule 10.3, 10.4, 10.6, 10.7 and 17.7.
[2.1.1]
Improvements
Updated the gain calibration formula.
Used feature to segregate the new item kLPADC_TriggerPriorityPreemptSubsequently.
[2.1.0]
New Features
Added the API LPADC_SetOffsetValue() to support configure offset trim value manually.
Added the API LPADC_DoOffsetCalibration() to do offset calibration independently.
Improvements
Improved the usage of macros and removed invalid macros.
[2.0.2]
Improvements
Added support for platforms with 2 FIFOs and different calibration measures.
[2.0.1]
Bug Fixes
Ensured the API LPADC_SetConvCommandConfig configure related registers correctly.
[2.0.0]
Initial version.
MCAN
[2.4.2]
Bug Fixes
Fixed MISRA issue rule-10.3, rule-10.6, rule-10.7 and rule-15.7.
[2.4.1]
Bug Fixes
Fixed incorrect fifo1 status on message lost.
[2.4.0]
Improvements
Add MCAN_CalculateSpecifiedTimingValues() API to get CAN bit timing parameter with user-defined settings.
Add MCAN_FDCalculateSpecifiedTimingValues() API to get CANFD bit timing parameter with user-defined settings.
[2.3.2]
Bug Fixes
Fix MISRA C-2012 issue 10.1 and 10.4.
[2.3.1]
Bug Fixes
Fixed the issue that MCAN_TransferSendNonBlocking() API can’t send remote frame.
[2.3.0]
Improvements
Add MCAN_SetMessageRamConfig() API to perform global message RAM configure.
Add MCAN_EnterInitialMode() API.
[2.2.0]
Improvements
Add MCAN_SetBaudRate/MCAN_SetBaudRateFD APIs to make users easy to set CAN baud rate.
[2.1.8]
Bug Fixes
Add check FIFO status code in MCAN_ReadRxFifo() to avoid read back empty frame and wrong trigger the FIFO index increase.
[2.1.7]
Bug Fixes
Fixed the clear error flags issue in MCAN_TransferHandleIRQ() API.
Fixed the Solve Tx interrupt issue in MCAN_TransferHandleIRQ() API which may abort the unhandled transfers.
Remove disable global tx interrupt from MCAN_TransferAbortSend API.
[2.1.6]
Bug Fixes
Fixed the issue of writing 1 in the following functions.
MCAN_TransmitAddRequest
MCAN_TransmitCancelRequest
MCAN_ClearRxBufferStatusFlag
[2.1.5]
Bug Fixes
Fix MISRA C-2012 issue.
[2.1.4]
Improvements
Updated improve timing APIs to make it can calculate the CiA recommended timing configuration.
Implement Transmitter Delay Compensation feature.
Modify the default baudRateFD value to 2M.
Bug Fixes
Fixed the code error issue in MCAN_ClearStatusFlag() to avoid clear all flags.
[2.1.3]
Bug Fixes
Fixed the code error issue and simplified the algorithm in improved timing APIs.
MCAN_CalculateImprovedTimingValues
MCAN_FDCalculateImprovedTimingValues
[2.1.2]
Bug Fixes
Fixed the non-divisible case in improved timing APIs.
MCAN_CalculateImprovedTimingValues
MCAN_FDCalculateImprovedTimingValues
[2.1.1]
Bug Fixes
MISRA C-2012 issue check.
Fixed rules, containing: rule-10.1, rule-10.3, rule-10.4, rule-10.6, rule-10.7, rule-10.8, rule-11.9, rule-14.4, rule-15.5, rule-15.6, rule-15.7, rule-17.7, rule-18.4, rule-2.2, rule-21.15, rule-5.8, rule-8.3.
Fixed the Coverity issue of BAD_SHIFT in MCAN.
Fixed the issue of Pa082 warning.
Fixed the issue of dropping interrupt flags in handler function.
[2.1.0]
Bug Fixes
Fixed Coverity issue FORWARD_NULL.
Fixed Clang issue.
Fixed legacy issue in the driver and changed default bus data baud rate for CANFD.
Improvements
Implemented feature for improved timing configuration.
[2.0.3]
Improvements
Used memset to initialize the structure before using.
Added function definition comment in c file.
Updated source file license to SPDX BSD_3.
Corrected capital mistake of Fifo and fifo.
Reset the MCAN module in LPC drivers after clock enable.
[2.0.2]
Bug Fixes
Picked MISRA fixed in release 8 branch.
MISRA C 2012 fixed regarding FlexCAN and MCAN address update.
Improvements
Implemented for delay/retry in MCAN driver.
[2.0.1]
Improvements
LPC54608 chip did not support the FD feature, so added a feature macro for it.
[2.0.0]
Initial version.
MRT
[2.0.4]
Improvements
Don’t reset MRT when there is not system level MRT reset functions.
[2.0.3]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.1 and 10.4.
Fixed the wrong count value assertion in MRT_StartTimer API.
[2.0.2]
Bug Fixes
Fixed violations of MISRA C-2012 rule 10.4.
[2.0.1]
Added control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.0]
Initial version.
OPAMP
[2.2.0]
Improvements
Added OPAMP positive port gain and negative gain configuration functions.
[2.1.2]
Improvements
Release peripheral from reset if necessary in init function.
[2.1.1]
Bug Fixes
Fixed violations of the MISRA C-2012 rules.
[2.1.0]
Improvements
Updated opamp driver code, supports devices MCXN947 and MCXN548.
Added OPAMP_EnableRefBuffer() API to control bias voltage input buffer.
Added OPAMP_EnableTriggerMode() API to control OPAMP trigger mode.
[2.0.0]
Initial version.
OSTIMER
[2.2.3]
Improvements
Disable and clear pending interrupts before disabling the OSTIMER clock to avoid interrupts being executed when the clock is already disabled.
[2.2.2]
Improvements
Support devices with different OSTIMER instance name.
[2.2.1]
Improvements
Release peripheral from reset if necessary in init function.
[2.2.0]
Improvements
Move the PMC operation out of the OSTIMER driver to board specific files.
Added low level APIs to control OSTIMER MATCH and interrupt.
[2.1.2]
Bug Fixes
Fixed MISRA-2012 rule 10.8.
[2.1.1]
Bug Fixes
removes the suffix ‘n’ for some register names and bit fields’ names
Improvements
Added HW CODE GRAY feature supported by CODE GRAY in SYSCTRL register group.
[2.1.0]
Bug Fixes
Added a workaround to fix the issue that no interrupt was reported when user set smaller period.
Fixed violation of MISRA C-2012 rule 10.3 and 11.9.
Improvements
Added return value for the two APIs to set match value.
OSTIMER_SetMatchRawValue
OSTIMER_SetMatchValue
[2.0.3]
Bug Fixes
Fixed violation of MISRA C-2012 rule 10.3, 14.4, 17.7.
[2.0.2]
Improvements
Added support for OSTIMER0
[2.0.1]
Improvements
Removed the software reset function out of the initialization API.
Enabled interrupt directly instead of enabling deep sleep interrupt. Users need to enable the deep sleep interrupt in application code if needed.
[2.0.0]
Initial version.
PINT
[2.1.13]
Improvements
Added instance array for PINT to adapt more devices.
Used release reset instead of reset PINT which may clear other related registers out of PINT.
[2.1.12]
Bug Fixes
Fixed coverity issue.
[2.1.11]
Bug Fixes
Fixed MISRA C-2012 rule 10.7 violation.
[2.1.10]
New Features
Added the driver support for MCXN10 platform with combined interrupt handler.
[2.1.9]
Bug Fixes
Fixed MISRA-2012 rule 8.4.
[2.1.8]
Bug Fixes
Fixed MISRA-2012 rule 10.1 rule 10.4 rule 10.8 rule 18.1 rule 20.9.
[2.1.7]
Improvements
Added fully support for the SECPINT, making it can be used just like PINT.
[2.1.6]
Bug Fixes
Fixed the bug of not enabling common pint clock when enabling security pint clock.
[2.1.5]
Bug Fixes
Fixed issue for MISRA-2012 check.
Fixed rule 10.1 rule 10.3 rule 10.4 rule 10.8 rule 14.4.
Changed interrupt init order to make pin interrupt configuration more reasonable.
[2.1.4]
Improvements
Added feature to control distinguish PINT/SECPINT relevant interrupt/clock configurations for PINT_Init and PINT_Deinit API.
Swapped the order of clearing PIN interrupt status flag and clearing pending NVIC interrupt in PINT_EnableCallback and PINT_EnableCallbackByIndex function.
Bug Fixes
Fixed build issue caused by incorrect macro definitions.
[2.1.3]
Bug fix:
Updated PINT_PinInterruptClrStatus to clear PINT interrupt status when the bit is asserted and check whether was triggered by edge-sensitive mode.
Write 1 to IST corresponding bit will clear interrupt status only in edge-sensitive mode and will switch the active level for this pin in level-sensitive mode.
Fixed MISRA c-2012 rule 10.1, rule 10.6, rule 10.7.
Added FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS to distinguish IRQ relevant array definitions for SECPINT/PINT on lpc55s69 board.
Fixed PINT driver c++ build error and remove index offset operation.
[2.1.2]
Improvement:
Improved way of initialization for SECPINT/PINT in PINT_Init API.
[2.1.1]
Improvement:
Enabled secure pint interrupt and add secure interrupt handle.
[2.1.0]
Added PINT_EnableCallbackByIndex/PINT_DisableCallbackByIndex APIs to enable/disable callback by index.
[2.0.2]
Added control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.1]
Bug fix:
Updated PINT driver to clear interrupt only in Edge sensitive.
[2.0.0]
Initial version.
Power
[2.0.1]
Update BoD value when switch clock frequency.
[2.0.0]
Initial version.
POWERQUAD
[2.2.0]
New Features
Added new API PQ_Arctan2Fixed.
[2.1.1]
Bug Fixes
Remove PQ_WaitDone from PQ_ArctanFixed and PQ_ArctanhFixed because it is unnecessary.
[2.1.0]
Improvements
Fixed typo issue for biquad related function name.
Changed operator from “%” into “&” to reduce heavy cycle for biquad functions.
[2.0.5]
Improvements
Added a note in driver for FIR that powerquad has a hardware limitation, when using it for FIR increment calculation, the address of pSrc needs to be a continuous address.
[2.0.4]
Improvements
Supported the platforms which don’t have PowerQuad clock and reset control.
[2.0.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 8.4, 10.1, 10.3, 10.4, 10.6, and so on.
[2.0.2]
Bug Fixes
Fixed array size issue in fsl_powerquad_data.h file.
Fixed vector function pipeline issue.
[2.0.1]
Bug Fixes
Fixed build error in C++ mode.
[2.0.0]
Initial version.
PRINCE
Version 2.6.0
Renamed CSS to ELS.
Version 2.5.1
Fix build error due to renamed symbols.
Version 2.3.2
Fix documentation of enumeration.
Extend PRINCE example.
Version 2.3.1
Fix MISRA-2012 issues.
Add support for LPC55S0x series
Version 2.3.0
Add support for LPC55S1x and LPC55S2x series
Version 2.2.0
Add runtime checking of the A0 and A1 rev. of LPC55Sxx serie to support both silicone revisions.
Version 2.1.0
Update for the A1 rev. of LPC55Sxx serie.
[2.0.0]
Initial version.
PUFv3
[2.0.3]
Update for various PUF CTRL wrapper.
[2.0.2]
Fix MISRA issue in driver.
[2.0.1]
Fix PUF initialization issue and update driver to reflect SoC header changes.
[2.0.0]
Initial version.
PWM
[2.9.0]
Improvements
Support PWMX channel output for edge aligned PWM.
Forbid submodule 0 counter initialize with master sync and master reload mode.
[2.8.4]
Improvements
Support workaround for ERR051989. This function helps realize no phase delay between submodule 0 and other submodule.
[2.8.3]
Bug Fixes
Fixed MISRA C-2012 Rule 15.7
[2.8.2]
Bug Fixes
Fixed warning conversion from ‘int’ to ‘uint16_t’ on API PWM_Init.
Fixed warning unused variable ‘reg’ on API PWM_SetPwmForceOutputToZero.
[2.8.1]
Improvements
Release peripheral from reset if necessary in init function.
[2.8.0]
Improvements
Added API PWM_UpdatePwmPeriodAndDutycycle to update the PWM signal’s period and dutycycle for a PWM submodule.
Added API PWM_SetPeriodRegister and PWM_SetDutycycleRegister to merge duplicate code in API PWM_SetupPwm, PWM_UpdatePwmDutycycleHighAccuracy and PWM_UpdatePwmPeriodAndDutycycle
[2.7.1]
Improvements
Supported UPDATE_MASK bit in MASK register.
[2.7.0]
Improvements
Supported platforms which don’t have Capture feature with channel A and B.
Supported platforms which don’t have Submodule 3.
Added assert function in API PWM_SetPhaseDelay to prevent wrong argument.
[2.6.1]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.3.
[2.6.0]
Improvements
Added API PWM_SetPhaseDelay to set the phase delay from the master sync signal of submodule 0.
Added API PWM_SetFilterSampleCountthe to set number of consecutive samples that must agree prior to the input filter.
Added API PWM_SetFilterSamplePeriod to set set the sampling period of the fault pin input filter.
[2.5.1]
Bug Fixes
Fixed MISRA C-2012 rules: 10.1, 10.3, 10.4 , 10.6 and 10.8.
Fixed the issue that PWM_UpdatePwmDutycycle() can’t update duty cycle status value correct.
[2.5.0]
Improvements
Added API PWM_SetOouputToIdle to set pwm channel output to idle.
Added API PWM_GetPwmChannelState to get the pwm channel output duty cycle value.
Added API PWM_SetPwmForceOutputToZero to set the pwm channel output to zero logic.
Added API PWM_SetChannelOutput to set the pwm channel output state.
Added API PWM_SetClockMode to set the value of the clock prescaler.
Added API PWM_SetupPwmPhaseShift to set PWM which a special phase shift and 50% duty cycle.
Added API PWM_SetVALxValue/PWM_GetVALxValue to set/get PWM VALs registers values directly.
[2.4.0]
Improvements
Supported the PWM which can’t work in wait mode.
[2.3.0]
Improvements
Add PWM output enable&disbale API for SDK.
Bug Fixes
Fixed changing channel B configuration when parameter is kPWM_PWMX and PWMX configuration is not supported yet.
[2.2.1]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 10.3, 10.4.
Bug Fixes
Fixed the issue that PWM drivers computed VAL1 improperly.
Improvements
Updated calculation accuracy of reloadValue in dutyCycleToReloadValue function.
[2.2.0]
Improvements
Added new enumeration and two APIs to support enabling and disabling one or more PWM output triggers.
Added a new function to make the most of 16-bit resolution PWM.
Added one API to support updating fault status of PWM output.
Added one API to support PWM DMA write request.
Added three APIs to support PWM DMA capture read request.
Added one API to support get default fault config of PWM.
Added one API to support setting PWM fault disable mapping.
[2.1.0]
Improvements
Moved the configuration of fault input filter into a new API to avoid be initialized multiple times.
Bug Fixes
MISRA C-2012 issue fixed.
Fix rules, containing: rule-10.2, rule-10.3, rule-10.4, rule-10.7, rule-10.8, rule-14.4, rule-16.4.
[2.0.1]
Bug Fixes
Fixed the issue that PWM submodule may be initialized twice in function PWM_SetupPwm().
[2.0.0]
Initial version.
RESET
[2.4.0]
Improvements
Add RESET_ReleasePeripheralReset API.
[2.0.0]
Initial version.
SCTIMER
[2.5.1]
Bug Fixes
Fixed bug in SCTIMER_SetupCaptureAction: When kSCTIMER_Counter_H is selected, events 12-15 and capture registers 12-15 CAPn_H field can’t be used.
[2.5.0]
Improvements
Add SCTIMER_GetCaptureValue API to get capture value in capture registers.
[2.4.9]
Improvements
Supported platforms which don’t have system level SCTIMER reset.
[2.4.8]
Bug Fixes
Fixed the issue that the SCTIMER_UpdatePwmDutycycle() can’t writes MATCH_H bit and RELOADn_H.
[2.4.7]
Bug Fixes
Fixed the issue that the SCTIMER_UpdatePwmDutycycle() can’t configure 100% duty cycle PWM.
[2.4.6]
Bug Fixes
Fixed the issue where the H register was not written as a word along with the L register.
Fixed the issue that the SCTIMER_SetCOUNTValue() is not configured with high 16 bits in unify mode.
[2.4.5]
Bug Fixes
Fix SCT_EV_STATE_STATEMSKn macro build error.
[2.4.4]
Bug Fixes
Fix MISRA C-2012 issue 10.8.
[2.4.3]
Bug Fixes
Fixed the wrong way of writing CAPCTRL and REGMODE registers in SCTIMER_SetupCaptureAction.
[2.4.2]
Bug Fixes
Fixed SCTIMER_SetupPwm 100% duty cycle issue.
[2.4.1]
Bug Fixes
Fixed the issue that MATCHn_H bit and RELOADn_H bit could not be written.
[2.4.0]
[2.3.0]
Bug Fixes
Fixed the potential overflow issue of pulseperiod variable in SCTIMER_SetupPwm/SCTIMER_UpdatePwmDutycycle API.
Fixed the issue of SCTIMER_CreateAndScheduleEvent API does not correctly work with 32 bit unified counter.
Fixed the issue of position of clear counter operation in SCTIMER_Init API.
Improvements
Update SCTIMER_SetupPwm/SCTIMER_UpdatePwmDutycycle to support generate 0% and 100% PWM signal.
Add SCTIMER_SetupEventActiveDirection API to configure event activity direction.
Update SCTIMER_StartTimer/SCTIMER_StopTimer API to support start/stop low counter and high counter at the same time.
Add SCTIMER_SetCounterState/SCTIMER_GetCounterState API to write/read counter current state value.
Update APIs to make it meaningful.
SCTIMER_SetEventInState
SCTIMER_ClearEventInState
SCTIMER_GetEventInState
[2.2.0]
Improvements
Updated for 16-bit register access.
[2.1.3]
Bug Fixes
Fixed the issue of uninitialized variables in SCTIMER_SetupPwm.
Fixed the issue that the Low 16-bit and high 16-bit work independently in SCTIMER driver.
Improvements
Added an enumerable macro of unify counter for user.
kSCTIMER_Counter_U
Created new APIs for the RTC driver.
SCTIMER_SetupStateLdMethodAction
SCTIMER_SetupNextStateActionwithLdMethod
SCTIMER_SetCOUNTValue
SCTIMER_GetCOUNTValue
SCTIMER_SetEventInState
SCTIMER_ClearEventInState
SCTIMER_GetEventInState
Deprecated legacy APIs for the RTC driver.
SCTIMER_SetupNextStateAction
[2.1.2]
Bug Fixes
MISRA C-2012 issue fixed: rule 10.3, 10.4, 10.6, 10.7, 11.9, 14.2 and 15.5.
[2.1.1]
Improvements
Updated the register and macro names to align with the header of devices.
[2.1.0]
Bug Fixes
Fixed issue where SCT application level Interrupt handler function is occupied by SCT driver.
Fixed issue where wrong value for INSYNC field inside SCTIMER_Init function.
Fixed issue to change Default value for INSYNC field inside SCTIMER_GetDefaultConfig.
[2.0.1]
New Features
Added control macro to enable/disable the RESET and CLOCK code in current driver.
[2.0.0]
Initial version.
SPI
[2.3.2]
Bug Fixes
Fixed the txData from void * to const void * in transmit API
[2.3.1]
Improvements
Changed SPI_DUMMYDATA to 0x00.
[2.3.0]
Update version.
[2.2.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules.
[2.2.1]
Bug Fixes
Fixed MISRA 2012 10.4 issue.
Added code to clear FIFOs before transfer using DMA.
[2.2.0]
Bug Fixes
Fixed bug that slave gets stuck during interrupt transfer.
[2.1.1]
Improvements
Added timeout mechanism when waiting certain states in transfer driver.
Bug Fixes
Fixed MISRA 10.1, 5.7 issues.
[2.1.0]
Bug Fixes
Fixed Coverity issue of incrementing null pointer in SPI_TransferHandleIRQInternal.
Eliminated IAR Pa082 warnings.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 10.7, 10.8, 11.3, 11.6, 11.8, 11.9, 13.5.
New Features
Modified the definition of SPI_SSELPOL_MASK to support the socs that have only 3 SSEL pins.
[2.0.4]
Bug Fixes
Fixed the bug of using read only mode in DMA transfer. In DMA transfer mode, if transfer->txData is NULL, code attempts to read data from the address of 0x0 for configuring the last frame.
Fixed wrong assignment of handle->state. During transfer handle->state should be kSPI_Busy rather than kStatus_SPI_Busy.
Improvements
Rounded up the calculated divider value in SPI_MasterSetBaud.
[2.0.3]
Improvements
Added “SPI_FIFO_DEPTH(base)” with more definition.
[2.0.2]
Improvements
Unified the component full name to FLEXCOMM SPI(DMA/FREERTOS) driver.
[2.0.1]
Changed the data buffer from uint32_t to uint8_t which matches the real applications for SPI DMA driver.
Added dummy data setup API to allow users to configure the dummy data to be transferred.
Added new APIs for half-duplex transfer function. Users can not only send and receive data by one API in polling/interrupt/DMA way, but choose either to transmit first or to receive first. Besides, the PCS pin can be configured as assert status in transmission (between transmit and receive) by setting the isPcsAssertInTransfer to true.
[2.0.0]
Initial version.
SPI_DMA
[2.2.1]
Bug Fixes
Fixed MISRA 2012 11.6 issue..
[2.2.0]
Improvements
Supported dataSize larger than 1024 data transmit.
SYSCTL
[2.0.5]
Bug Fixes:
Fixed violations of MISRA C-2012 rule 8.3, 10.1, 10.4, 10.7.
[2.0.4]
Improvements:
Update macro name to align with the header of devices.
[2.0.3]
Improvements:
Update the register and macro name to align with the header of devices.
[2.0.2]
Removed kSYSCTL_Flexcomm3DataOut enumeration definition.
[2.0.1]
Fixed some typo error comments and improved driver integral ability.
[2.0.0]
Initial version.
USART
[2.8.5]
Bug Fixes
Fixed race condition during call of USART_EnableTxDMA and USART_EnableRxDMA.
[2.8.4]
Bug Fixes
Fixed exclusive access in USART_TransferReceiveNonBlocking and USART_TransferSendNonBlocking.
[2.8.3]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 10.3, 11.8.
[2.8.2]
Bug Fixes
Fixed violations of the MISRA C-2012 rules 14.2.
[2.8.1]
Bug Fixes
Fixed the Baud Rate Generator(BRG) configuration in 32kHz mode.
[2.8.0]
New Features
Added the rx timeout interrupts and status flags of bus status.
Added new rx timeout configuration item in usart_config_t.
Added API USART_SetRxTimeoutConfig for rx timeout configuration.
Improvements
When the calculated baudrate cannot meet user’s configuration, lower OSR value is allewed to use.
[2.7.0]
New Features
Added the missing interrupts and status flags of bus status.
Added the check of tx error, noise error framing error and parity error in interrupt handler.
[2.6.0]
Improvements
Used separate data for TX and RX in usart_transfer_t.
Bug Fixes
Fixed bug that when ring buffer is used, if some data is received in ring buffer first before calling USART_TransferReceiveNonBlocking, the received data count returned by USART_TransferGetReceiveCount is wrong.
New Features
Added missing API USART_TransferGetSendCountDMA get send count using DMA.
[2.5.0]
New Features
Added APIs USART_GetRxFifoCount/USART_GetTxFifoCount to get rx/tx FIFO data count.
Added APIs USART_SetRxFifoWatermark/USART_SetTxFifoWatermark to set rx/tx FIFO water mark.
Bug Fixes
Fixed DMA transfer blocking issue by enabling tx idle interrupt after DMA transmission finishes.
[2.4.0]
New Features
Modified usart_config_t, USART_Init and USART_GetDefaultConfig APIs so that the hardware flow control can be enabled during module initialization.
Bug Fixes
Fixed MISRA 10.4 violation.
[2.3.1]
Bug Fixes
Fixed bug that operation on INTENSET, INTENCLR, FIFOINTENSET and FIFOINTENCLR should use bitwise operation not ‘or’ operation.
Fixed bug that if rx interrupt occurrs before TX interrupt is enabled and after txDataSize is configured, the data will be sent early by mistake, thus TX interrupt will be enabled after data is sent out.
Improvements
Added check for baud rate’s accuracy that returns kStatus_USART_BaudrateNotSupport when the best achieved baud rate is not within 3% error of configured baud rate.
[2.3.0]
New Features
Added APIs to configure 9-bit data mode, set slave address and send address.
Modified USART_TransferReceiveNonBlocking and USART_TransferHandleIRQ to use 9-bit mode in multi-slave system.
[2.2.0]
New Features
Added the feature of supporting USART working at 32 kHz clocking mode.
Improvements
Modified USART_TransferHandleIRQ so that txState will be set to idle only when all data has been sent out to bus.
Modified USART_TransferGetSendCount so that this API returns the real byte count that USART has sent out rather than the software buffer status.
Added timeout mechanism when waiting for certain states in transfer driver.
Bug Fixes
Fixed MISRA 10.1 issues.
Fixed bug that operation on INTENSET, INTENCLR, FIFOINTENSET and FIFOINTENCLR should use bitwise operation not ‘or’ operation.
Fixed bug that if rx interrupt occurrs before TX interrupt is enabled and after txDataSize is configured, the data will be sent early by mistake, thus TX interrupt will be enabled after data is sent out.
[2.1.1]
Improvements
Added check for transmitter idle in USART_TransferHandleIRQ and USART_TransferSendDMACallback to ensure all the data would be sent out to bus.
Modified USART_ReadBlocking so that if more than one receiver errors occur, all status flags will be cleared and the most severe error status will be returned.
Bug Fixes
Eliminated IAR Pa082 warnings.
Fixed MISRA issues.
Fixed rules 10.1, 10.3, 10.4, 10.7, 10.8, 11.3, 11.6, 11.8, 11.9, 13.5.
[2.1.0]
New Features
Added features to allow users to configure the USART to synchronous transfer(master and slave) mode.
Bug Fixes
Modified USART_SetBaudRate to get more acurate configuration.
[2.0.3]
New Features
Added new APIs to allow users to enable the CTS which determines whether CTS is used for flow control.
[2.0.2]
Bug Fixes
Fixed the bug where transfer abort APIs could not disable the interrupts. The FIFOINTENSET register should not be used to disable the interrupts, so use the FIFOINTENCLR register instead.
[2.0.1]
Improvements
Unified the component full name to FLEXCOMM USART (DMA/FREERTOS) driver.
[2.0.0]
Initial version.
USART_DMA
[2.6.0]
Refer USART driver change log 2.0.1 to 2.6.0
UTICK
[2.0.5]
Improvements
Improved for SOC RW610.
[2.0.4]
Bug Fixes
Fixed compile fail issue of no-supporting PD configuration in utick driver.
[2.0.3]
Bug Fixes
Fixed violations of MISRA C-2012 rules: 8.4, 14.4, 17.7
[2.0.2]
Added new feature definition macro to enable/disable power control in drivers for some devices have no power control function.
[2.0.1]
Added control macro to enable/disable the CLOCK code in current driver.
[2.0.0]
Initial version.
VREF
[2.4.0]
Improvements
Support TEST_UNLOCK and TRIM0 registers read and write.
[2.3.0]
Improvements
Add feature macros for compatibility with some platforms that don’t have CSR[LPBG_BUF_EN] and UTRIM[TRIM2V1].
[2.2.2]
Bug Fixes
Fixed typo in vref_buffer_mode_t enumerator.
[2.2.1]
Improvements
Updated VREF driver code to reduce code redundancy.
[2.2.0]
Improvements
Remove API VREF_SetTrimVal and VREF_GetTrimVal
Add new API VREF_SetVrefTrimVal,VREF_SetTrim21Val,VREF_GetVrefTrimVal and VREF_GetTrim21Val
Updated VREF driver code to conform to VREF IP architecture.
[2.1.0]
Improvements
Remove API VREF_SetTrimVal and VREF_GetTrimVal
Add new API VREF_SetVrefTrimVal,VREF_SetTrim21Val,VREF_GetVrefTrimVal and VREF_GetTrim21Val
Updated VREF driver code to conform to VREF IP architecture.
Bug Fixes
Fix issue which progeam stuck in VREF_Init
[2.0.0]
Initial version.
WWDT
[2.1.9]
Bug Fixes
Fixed violation of the MISRA C-2012 rule 10.4.
[2.1.8]
Improvements
Updated the “WWDT_Init” API to add wait operation. Which can avoid the TV value read by CPU still be 0xFF (reset value) after WWDT_Init function returns.
[2.1.7]
Bug Fixes
Fixed the issue that the watchdog reset event affected the system from PMC.
Fixed the issue of setting watchdog WDPROTECT field without considering the backwards compatibility.
Fixed the issue of clearing bit fields by mistake in the function of WWDT_ClearStatusFlags.
[2.1.5]
Bug Fixes
deprecated a unusable API in WWWDT driver.
WWDT_Disable
[2.1.4]
Bug Fixes
Fixed violation of the MISRA C-2012 rules Rule 10.1, 10.3, 10.4 and 11.9.
Fixed the issue of the inseparable process interrupted by other interrupt source.
WWDT_Init
[2.1.3]
Bug Fixes
Fixed legacy issue when initializing the MOD register.
[2.1.2]
Improvements
Updated the “WWDT_ClearStatusFlags” API and “WWDT_GetStatusFlags” API to match QN9090. WDTOF is not set in case of WD reset. Get info from PMC instead.
[2.1.1]
New Features
Added new feature definition macro for devices which have no LCOK control bit in MOD register.
Implemented delay/retry in WWDT driver.
[2.1.0]
Improvements
Added new parameter in configuration when initializing WWDT module. This parameter, which must be set, allows the user to deliver the WWDT clock frequency.
[2.0.0]
Initial version.