Introduction

The Synchronous Sample Rate Converter (SSRC) software module converts a mono or stereo audio signal with a certain sampling frequency to an audio signal with a different sampling frequency. The sample rate converter works synchronously, meaning that input and output sampling rates are exactly known for a mutual clock reference.

To accomplish a professional sampling conversion quality and minimal system footprint, the SRC SW module contains highly optimized components.

The SSRC module supports the following features.

  • Multiple instances of the sample rate converter can run at the same time.

  • Supported sampling frequencies: 32 kHz, 44.1 kHz, and 48 kHz plus the halves and the quarters of these three sample rates. The input and output sample rates are freely selectable out of the supported sampling rates

  • Selectable Mono/Stereo Input/Output.

  • Selectable quality level: high quality/ very high quality.

Acronyms

Table 1 lists the acronyms used in this document.

Acronym

Description

Fs

Sampling Frequency

FsLOWow

Lowest sample rate used for the conversion Note: Input sample rate for up sampling and the output sample rate for down sampling

FsIN

Input sample rate

FsOUT

Output sample rate

MIPS

Million Instructions Per Second

SSRC

Synchronous sample rate converter

THD+N

Total Harmonic Distortion plus Noise Note: The THD+N is defined as the total power of the unwanted signal divided by the power of the wanted signal. The wanted signal is defined as a full scale, 1 kHz sine wave.

Parent topic:Introduction

Performance figures

The Total Harmonic Distortion Plus Noise (THD+N) of the converted signals is below - 76 (high-quality mode) and - 85 (very high-quality mode) for signal frequencies below 0.45*FsLOW (=90 % of the Nyquist range of the lowest sample clock)

Table 1 and Table 2 give the THD+N performance (FsIN on the vertical axis and FsOUT on the horizontal axis) for the two supported quality levels. The numbers in the tables give the worst-case THD+N measured for signal frequencies below 0.45*FsLOW. For each conversion ratio, 100 THD+N measurements were executed with signal frequencies linearly spread over the complete Nyquist range.

FsIN/ FsOUT

8000

11025

12000

16000

22050

24000

32000

44100

48000

8000

-92.1

-79.7

-80.1

-80.1

-79.6

-80.2

-79.4

-79.1

-79.2

11025

-79

-92.9

-80

-79.9

-80.2

-79.8

-79.9

-79.5

-78.9

12000

-79

-79.2

-92.7

-80.1

-79.8

-80.3

-79.8

-79.8

-79.5

16000

-81.7

-78.8

-80.2

-93

-78.3

-77.7

-78.3

-78.3

-77.9

22050

-77.5

-81.8

-78.2

-79

-93

-79.9

-79.8

-80.3

-79.9

24000

-77.4

-77.9

-81.2

-79.1

-79.2

-92.5

-80.1

-79.8

-79.9

32000

-81

-77.5

-78.9

-81.2

-78.7

-80.1

-92.9

-79.7

-79.2

44100

-79.1

-81.2

-76.7

-77.8

-82

-78.2

-79.1

-93

-79.7

48000

-78.7

-78.8

-81.1

-77.6

-77.9

-81.8

-79.1

-79.3

-93

FsIN/ FsOUT

8000

11025

12000

16000

22050

24000

32000

44100

48000

8000

-92.1

-86.6

-88.6

-91.5

-86.4

-89

-89.7

-89.3

-89.3

11025

-89.1

-92.9

-86.3

-86.3

-91.6

-86.3

-86.5

-89.7

-89.3

12000

-91.4

-88.4

-92.7

-89.6

-86.6

-91.5

-86.8

-86.6

-89.7

16000

-93.1

-88.4

-90.4

-93

-86.6

-88.8

-91.5

-86.5

-89.4

22050

-90.7

-93.5

-89.7

-89.3

-93

-86.5

-86.3

-91.5

-86.6

24000

-93.8

-90.5

-93.5

-91.7

-88.4

-92.5

-89.7

-86.6

-91.5

32000

-93.8

-91

-91.2

-93.3

-88.4

-90.5

-92.9

-86.7

-89

44100

-93.7

-93.6

-91.5

-90.6

-93.8

-89.8

-89.3

-93

-86.5

48000

-94.1

-92.6

-94

-94

-90.1

-93.7

-91.8

-88.4

-93

Parent topic:Introduction

Resource usage

This section lists the memory and processing requirements for the SSRC module.

Memory requirements

The following are the memory requirements for the SSRC module.

Memory item

Size in bytes

Instance memory (persistent)

548

Scratch memory (non-persistent)

15.536 1

Program memory for Arm9E and XScale

14k

Program memory for Arm7

15k

Parent topic:Resource usage

1 Worst case number for I/O buffers of 40 ms. If smaller I/O buffers are used, this number is smaller. The required scratch memory is roughly equal to 2 times the buffer size on the highest sample rate.

Processing requirements

The following tables give the MIPS performance of the SSRC module. The cycles are measured with zero wait state memory and for I/O buffers of 40 ms.

Note: The user processing 32-bit processing must refer to the very high-quality MIPS results.

On Arm7 and Arm9

FsIN / FsOUT

8000

11025

12000

16000

22050

24000

32000

44100

48000

8000

0.13

4.77

5.17

1.84

6.75

7.33

3.55

9.1

9.89

11025

5.42

0.18

5.58

6.84

2.53

7.75

9.71

4.89

10.31

12000

5.85

6.39

0.2

7.01

8.97

2.76

9.89

12.94

5.32

16000

1.69

7.74

7.99

0.26

9.54

10.33

3.68

13.5

14.65

22050

7.2

2.33

10.09

10.83

0.36

11.17

13.67

5.07

15.49

24000

7.79

8.33

2.53

11.7

12.78

0.39

14.03

17.94

5.51

32000

3.12

10.32

10.58

3.38

15.48

15.98

0.52

19.08

20.66

44100

9.96

4.3

13.65

14.4

4.65

20.18

21.67

0.72

22.34

48000

10.8

11.34

4.68

15.58

16.67

5.06

23.4

25.56

0.78

FsIN / FsOUT

8000

11025

12000

16000

22050

24000

32000

44100

48000

8000

0.07

7.71

8.24

2.28

10.5

11.28

4.41

13.44

14.48

11025

8.19

0.1

8.96

11.04

3.14

12

15.09

6.08

15.2

12000

8.76

9.52

0.1

11.3

14.48

3.41

15.36

20.07

6.61

16000

2.14

11.73

12.01

0.14

15.41

16.48

4.55

21

22.56

22050

10.78

2.94

15.39

16.38

0.19

17.92

22.08

6.27

24

24000

11.57

12.34

3.2

17.51

19.04

0.21

22.61

28.97

6.83

32000

4.19

15.48

15.77

4.27

23.46

24.01

0.28

30.83

32.96

44100

14.78

5.77

20.56

21.56

5.89

30.77

32.75

0.38

35.83

48000

15.92

16.7

6.28

23.15

24.69

6.41

35.02

38.08

0.42

FsIN / FsOUT

8000

11025

12000

16000

22050

24000

32000

44100

48000

8000

0.13

13.61

14.52

4.43

19.03

20.43

8.8

25.06

26.99

11025

14.85

0.18

15.91

19.47

6.1

21.82

27.35

12.13

28.38

12000

15.84

17.36

0.2

19.97

25.4

6.64

27.85

36.26

13.21

16000

4.25

21.24

21.79

0.26

27.22

29.03

8.86

38.07

40.85

22050

20.02

5.85

27.72

29.7

0.36

31.81

38.94

12.2

43.63

24000

21.45

22.98

6.37

31.68

34.71

0.39

39.94

50.8

13.28

32000

8.39

28.74

29.29

8.5

42.48

43.58

0.52

54.43

58.07

44100

28.11

11.57

38.05

40.03

11.71

55.43

59.4

0.72

63.62

48000

30.19

31.71

12.59

42.9

45.96

12.74

63.36

69.42

0.78

Parent topic:Processing requirements

On Arm9e and XScale

FsIN / FsOUT

8000

11025

12000

16000

22050

24000

32000

44100

48000

8000

0.03

1.14

1.25

0.54

1.95

2.14

1.04

3.85

4.23

11025

1.31

0.05

1.36

1.62

0.75

2.23

2.78

1.44

4.38

12000

1.43

1.57

0.05

1.68

2.13

0.82

2.84

3.72

1.57

16000

0.5

1.86

1.93

0.07

2.27

2.5

1.09

3.9

4.29

22050

2.19

0.69

2.42

2.61

0.1

2.72

3.24

1.5

4.46

24000

2.4

2.52

0.75

2.86

3.15

0.1

3.35

4.25

1.63

32000

0.92

3.12

3.18

1.01

3.72

3.86

0.14

4.55

4.99

44100

4.28

1.27

4.15

4.37

1.39

4.83

5.23

0.19

5.43

48000

4.7

4.9

1.39

4.8

5.03

1.51

5.72

6.3

0.21

FsIN / FsOUT

8000

11025

12000

16000

22050

24000

32000

44100

48000

8000

0.06

1.87

2.02

1.07

3.09

3.36

2.07

6.09

6.63

11025

2.27

0.09

2.25

2.66

1.47

3.56

4.4

2.85

7.01

12000

2.45

2.76

0.09

2.75

3.43

1.6

4.5

5.83

3.1

16000

0.99

3.23

3.36

0.13

3.73

4.05

2.14

6.17

6.72

22050

3.69

1.36

4.14

4.55

0.17

4.51

5.31

2.95

7.13

24000

4.01

4.28

1.48

4.9

5.51

0.19

5.51

6.85

3.21

32000

1.83

5.26

5.39

1.98

6.46

6.71

0.25

7.47

8.09

44100

7.22

2.52

6.94

7.38

2.72

8.27

9.1

0.35

9.02

48000

7.85

8.33

2.74

8.02

8.57

2.97

9.81

11.03

0.38

FsIN / FsOUT

8000

11025

12000

16000

22050

24000

32000

44100

48000

8000

0.03

1.21

1.33

0.61

2.08

2.29

1.17

4.1

4.51

11025

1.47

0.05

1.44

1.72

0.84

2.38

2.97

1.61

4.66

12000

1.62

1.76

0.05

1.78

2.26

0.91

3.03

3.98

1.75

16000

0.55

2.1

2.17

0.07

2.42

2.65

1.22

4.16

4.57

22050

2.49

0.76

2.73

2.95

0.1

2.88

3.45

1.68

4.75

24000

2.75

2.86

0.83

3.23

3.52

0.1

3.56

4.53

1.83

32000

1

3.56

3.63

1.11

4.2

4.34

0.14

4.84

5.3

44100

4.86

1.38

4.74

4.98

1.53

5.46

5.89

0.19

5.75

48000

5.38

5.55

1.5

5.5

5.71

1.66

6.47

7.05

0.21

FsIN / FsOUT

8000

11025

12000

16000

22050

24000

32000

44100

48000

8000

0.06

2.11

2.29

1.2

3.55

3.86

2.31

6.99

7.61

11025

2.62

0.09

2.52

3.01

1.66

4.07

5.07

3.19

8

12000

2.85

3.15

0.09

3.11

3.9

1.81

5.17

6.75

3.47

16000

1.09

3.73

3.85

0.13

4.22

4.57

2.41

7.1

7.72

22050

4.32

1.5

4.79

5.23

0.17

5.05

6.02

3.32

8.15

24000

4.74

4.99

1.64

5.69

6.3

0.19

6.22

7.8

3.61

32000

1.98

6.18

6.3

2.18

7.45

7.71

0.25

8.44

9.14

44100

8.43

2.72

8.18

8.64

3.01

9.59

10.47

0.35

10.1

48000

9.26

9.66

2.97

9.49

9.97

3.27

11.39

12.59

0.38

Parent topic:Processing requirements

On Cortex-A8 for worst case of 48000 Hz to 44100 Hz

Mode

MIPs

Mono at High Quality

3.13

Stereo at High Quality

3.61

Mono at Very High Quality

4.13

Stereo at Very High Quality

6.52

Parent topic:Processing requirements

Parent topic:Resource usage

Parent topic:Introduction